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git01.mediatek.com / filogic / rdk-b / meta-filogic / cc8110b742035c30bc4faf2e4b4716d34c459ca1 / . / recipes-wifi / linux-mt76 / files / patches-3.x / 0019-mtk-wifi-mt76-mt7996-add-debug-tool.patch
blob: e6aae938ec19edb93aef0e9cc1a98c641ce7c89d [file] [log] [blame]
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]1From fe15bfb3335bcbdf95fed1563646d84154607b42 Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]2From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Fri, 24 Mar 2023 14:02:32 +0800
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]4Subject: [PATCH 019/116] mtk: wifi: mt76: mt7996: add debug tool
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]5
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]6Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
7
8Add PSM bit in sta_info
9
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]10Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]11
12Remove the duplicate function in mtk_debugfs.c & mtk_debug_i.c
13Only enable mt7996_mcu_fw_log_2_host function in mcu.c
14
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]15Signed-off-by: MeiChia Chiu <meichia.chiu@mediatek.com>
16
17Support more ids category NDPA/NDP TXD/FBK and debug log recommended by
18CTD members.
19
20This commit equals to run the follwoing commands on Logan driver:
21command:
221. iwpriv ra0 set fw_dbg=1:84
232. iwpriv ra0 set fw_dbg=2:84
243. iwpriv ra0 set fw_dbg=1:101
25
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]26Signed-off-by: Howard Hsu <howard-yh.hsu@mediatek.com>
27
28mtk: wifi: mt76: mt7996: add wtbl_info support for mt7992
29
30Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
31
32mtk: wifi: mt76: mt7996: add mt7992 & mt7996 CR debug offset revision
33
34Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
35
36mtk: wifi: mt76: mt7992: refactor code for FW log
37
38Refactor code for FW log.
39
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]40Signed-off-by: Benjamin Lin <benjamin-jw.lin@mediatek.com>
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]41
42mtk: wifi: mt76: mt7996: support disable muru debug info when recording fwlog
43
44When we record fwlog, we will also enable recording muru debug info log by
45default. However, in certain test scenarios, this can result in
46recording too many logs, causing inconvenience during issue analysis.
47Therefore, this commit adds an debug option, fw_debug_muru_disable, in
48debugfs. User can modify this option to enable/disable recording muru
49debug info log.
50
51[Usage]
52Set:
53$ echo val > debugfs/fw_debug_muru_disable
54Get:
55$ cat debugfs/fw_debug_muru_disable
56
57val can be the following values:
580 = enable recording muru debug info (Default value)
591 = disable recording muru debug info
60
61Signed-off-by: Howard Hsu <howard-yh.hsu@mediatek.com>
62
63mtk: wifi: mt76: mt7996: add adie id & ver dump
64
65Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
66---
67 mt76.h | 2 +
68 mt7996/Makefile | 4 +
69 mt7996/coredump.c | 10 +-
70 mt7996/coredump.h | 7 +
71 mt7996/debugfs.c | 128 ++-
72 mt7996/mac.c | 3 +
73 mt7996/mt7996.h | 13 +
74 mt7996/mtk_debug.h | 2286 ++++++++++++++++++++++++++++++++++++++
75 mt7996/mtk_debugfs.c | 2507 ++++++++++++++++++++++++++++++++++++++++++
76 mt7996/mtk_mcu.c | 39 +
77 mt7996/mtk_mcu.h | 19 +
78 tools/fwlog.c | 25 +-
79 12 files changed, 5018 insertions(+), 25 deletions(-)
80 create mode 100644 mt7996/mtk_debug.h
81 create mode 100644 mt7996/mtk_debugfs.c
82 create mode 100644 mt7996/mtk_mcu.c
83 create mode 100644 mt7996/mtk_mcu.h
84
85diff --git a/mt76.h b/mt76.h
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]86index 7f3ec40..b421a98 100644
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]87--- a/mt76.h
88+++ b/mt76.h
89@@ -399,6 +399,8 @@ struct mt76_txwi_cache {
90 struct sk_buff *skb;
91 void *ptr;
92 };
93+
94+ unsigned long jiffies;
95 };
96
97 struct mt76_rx_tid {
98diff --git a/mt7996/Makefile b/mt7996/Makefile
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]99index 07c8b55..a056b40 100644
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]100--- a/mt7996/Makefile
101+++ b/mt7996/Makefile
102@@ -1,4 +1,6 @@
103 # SPDX-License-Identifier: ISC
104+EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
105+EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG
106
107 obj-$(CONFIG_MT7996E) += mt7996e.o
108
109@@ -6,3 +8,5 @@ mt7996e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
110 debugfs.o mmio.o
111
112 mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o
113+
114+mt7996e-y += mtk_debugfs.o mtk_mcu.o
115diff --git a/mt7996/coredump.c b/mt7996/coredump.c
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]116index 60b8808..a7f91b5 100644
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]117--- a/mt7996/coredump.c
118+++ b/mt7996/coredump.c
119@@ -195,7 +195,7 @@ mt7996_coredump_fw_stack(struct mt7996_dev *dev, u8 type, struct mt7996_coredump
120 }
121 }
122
123-static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type)
124+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
125 {
126 struct mt7996_crash_data *crash_data = dev->coredump.crash_data[type];
127 struct mt7996_coredump *dump;
128@@ -206,7 +206,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
129
130 len = hdr_len;
131
132- if (coredump_memdump && crash_data->memdump_buf_len)
133+ if (full_dump && coredump_memdump && crash_data->memdump_buf_len)
134 len += sizeof(*dump_mem) + crash_data->memdump_buf_len;
135
136 sofar += hdr_len;
137@@ -248,6 +248,9 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
138 mt7996_coredump_fw_state(dev, type, dump, &exception);
139 mt7996_coredump_fw_stack(dev, type, dump, exception);
140
141+ if (!full_dump)
142+ goto skip_dump_mem;
143+
144 /* gather memory content */
145 dump_mem = (struct mt7996_coredump_mem *)(buf + sofar);
146 dump_mem->len = crash_data->memdump_buf_len;
147@@ -255,6 +258,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
148 memcpy(dump_mem->data, crash_data->memdump_buf,
149 crash_data->memdump_buf_len);
150
151+skip_dump_mem:
152 mutex_unlock(&dev->dump_mutex);
153
154 return dump;
155@@ -264,7 +268,7 @@ int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
156 {
157 struct mt7996_coredump *dump;
158
159- dump = mt7996_coredump_build(dev, type);
160+ dump = mt7996_coredump_build(dev, type, true);
161 if (!dump) {
162 dev_warn(dev->mt76.dev, "no crash dump data found\n");
163 return -ENODATA;
164diff --git a/mt7996/coredump.h b/mt7996/coredump.h
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]165index 01ed373..93cd84a 100644
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]166--- a/mt7996/coredump.h
167+++ b/mt7996/coredump.h
168@@ -75,6 +75,7 @@ struct mt7996_mem_region {
169 const struct mt7996_mem_region *
170 mt7996_coredump_get_mem_layout(struct mt7996_dev *dev, u8 type, u32 *num);
171 struct mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type);
172+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump);
173 int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type);
174 int mt7996_coredump_register(struct mt7996_dev *dev);
175 void mt7996_coredump_unregister(struct mt7996_dev *dev);
176@@ -92,6 +93,12 @@ static inline int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
177 return 0;
178 }
179
180+static inline struct
181+mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
182+{
183+ return NULL;
184+}
185+
186 static inline struct
187 mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type)
188 {
189diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]190index 62c03d0..344c759 100644
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]191--- a/mt7996/debugfs.c
192+++ b/mt7996/debugfs.c
193@@ -295,11 +295,39 @@ mt7996_fw_debug_wm_set(void *data, u64 val)
194 DEBUG_SPL,
195 DEBUG_RPT_RX,
196 DEBUG_RPT_RA = 68,
197- } debug;
198+ DEBUG_IDS_SND = 84,
199+ DEBUG_IDS_PP = 93,
200+ DEBUG_IDS_RA = 94,
201+ DEBUG_IDS_BF = 95,
202+ DEBUG_IDS_SR = 96,
203+ DEBUG_IDS_RU = 97,
204+ DEBUG_IDS_MUMIMO = 98,
205+ DEBUG_IDS_ERR_LOG = 101,
206+ };
207+ u8 debug_category[] = {
208+ DEBUG_TXCMD,
209+ DEBUG_CMD_RPT_TX,
210+ DEBUG_CMD_RPT_TRIG,
211+ DEBUG_SPL,
212+ DEBUG_RPT_RX,
213+ DEBUG_RPT_RA,
214+ DEBUG_IDS_SND,
215+ DEBUG_IDS_PP,
216+ DEBUG_IDS_RA,
217+ DEBUG_IDS_BF,
218+ DEBUG_IDS_SR,
219+ DEBUG_IDS_RU,
220+ DEBUG_IDS_MUMIMO,
221+ DEBUG_IDS_ERR_LOG,
222+ };
223 bool tx, rx, en;
224 int ret;
225+ u8 i;
226
227 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
228+#ifdef CONFIG_MTK_DEBUG
229+ dev->fw_debug_wm = val;
230+#endif
231
232 if (dev->fw_debug_bin)
233 val = MCU_FW_LOG_RELAY;
234@@ -314,18 +342,21 @@ mt7996_fw_debug_wm_set(void *data, u64 val)
235 if (ret)
236 return ret;
237
238- for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) {
239- if (debug == 67)
240- continue;
241-
242- if (debug == DEBUG_RPT_RX)
243+ for (i = 0; i < ARRAY_SIZE(debug_category); i++) {
244+ if (debug_category[i] == DEBUG_RPT_RX)
245 val = en && rx;
246 else
247 val = en && tx;
248
249- ret = mt7996_mcu_fw_dbg_ctrl(dev, debug, val);
250+ ret = mt7996_mcu_fw_dbg_ctrl(dev, debug_category[i], val);
251 if (ret)
252 return ret;
253+
254+ if (debug_category[i] == DEBUG_IDS_SND && en) {
255+ ret = mt7996_mcu_fw_dbg_ctrl(dev, debug_category[i], 2);
256+ if (ret)
257+ return ret;
258+ }
259 }
260
261 return 0;
262@@ -397,6 +428,39 @@ remove_buf_file_cb(struct dentry *f)
263 return 0;
264 }
265
266+static int
267+mt7996_fw_debug_muru_set(void *data)
268+{
269+ struct mt7996_dev *dev = data;
270+ enum {
271+ DEBUG_BSRP_STATUS = 256,
272+ DEBUG_TX_DATA_BYTE_CONUT,
273+ DEBUG_RX_DATA_BYTE_CONUT,
274+ DEBUG_RX_TOTAL_BYTE_CONUT,
275+ DEBUG_INVALID_TID_BSR,
276+ DEBUG_UL_LONG_TERM_PPDU_TYPE,
277+ DEBUG_DL_LONG_TERM_PPDU_TYPE,
278+ DEBUG_PPDU_CLASS_TRIG_ONOFF,
279+ DEBUG_AIRTIME_BUSY_STATUS,
280+ DEBUG_UL_OFDMA_MIMO_STATUS,
281+ DEBUG_RU_CANDIDATE,
282+ DEBUG_MEC_UPDATE_AMSDU,
283+ } debug;
284+ int ret;
285+
286+ if (dev->fw_debug_muru_disable)
287+ return 0;
288+
289+ for (debug = DEBUG_BSRP_STATUS; debug <= DEBUG_MEC_UPDATE_AMSDU; debug++) {
290+ ret = mt7996_mcu_muru_dbg_info(dev, debug,
291+ dev->fw_debug_bin & BIT(0));
292+ if (ret)
293+ return ret;
294+ }
295+
296+ return 0;
297+}
298+
299 static int
300 mt7996_fw_debug_bin_set(void *data, u64 val)
301 {
302@@ -405,17 +469,23 @@ mt7996_fw_debug_bin_set(void *data, u64 val)
303 .remove_buf_file = remove_buf_file_cb,
304 };
305 struct mt7996_dev *dev = data;
306+ int ret;
307
308- if (!dev->relay_fwlog)
309+ if (!dev->relay_fwlog) {
310 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
311 1500, 512, &relay_cb, NULL);
312- if (!dev->relay_fwlog)
313- return -ENOMEM;
314+ if (!dev->relay_fwlog)
315+ return -ENOMEM;
316+ }
317
318 dev->fw_debug_bin = val;
319
320 relay_reset(dev->relay_fwlog);
321
322+ ret = mt7996_fw_debug_muru_set(dev);
323+ if (ret)
324+ return ret;
325+
326 return mt7996_fw_debug_wm_set(dev, dev->fw_debug_wm);
327 }
328
329@@ -785,6 +855,30 @@ mt7996_rf_regval_set(void *data, u64 val)
330 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7996_rf_regval_get,
331 mt7996_rf_regval_set, "0x%08llx\n");
332
333+static int
334+mt7996_fw_debug_muru_disable_set(void *data, u64 val)
335+{
336+ struct mt7996_dev *dev = data;
337+
338+ dev->fw_debug_muru_disable = !!val;
339+
340+ return 0;
341+}
342+
343+static int
344+mt7996_fw_debug_muru_disable_get(void *data, u64 *val)
345+{
346+ struct mt7996_dev *dev = data;
347+
348+ *val = dev->fw_debug_muru_disable;
349+
350+ return 0;
351+}
352+
353+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_muru_disable,
354+ mt7996_fw_debug_muru_disable_get,
355+ mt7996_fw_debug_muru_disable_set, "%lld\n");
356+
357 int mt7996_init_debugfs(struct mt7996_phy *phy)
358 {
359 struct mt7996_dev *dev = phy->dev;
360@@ -820,10 +914,17 @@ int mt7996_init_debugfs(struct mt7996_phy *phy)
361 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir,
362 mt7996_rdd_monitor);
363 }
364+ debugfs_create_file("fw_debug_muru_disable", 0600, dir, dev,
365+ &fops_fw_debug_muru_disable);
366
367 if (phy == &dev->phy)
368 dev->debugfs_dir = dir;
369
370+#ifdef CONFIG_MTK_DEBUG
371+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
372+ mt7996_mtk_init_debugfs(phy, dir);
373+#endif
374+
375 return 0;
376 }
377
378@@ -835,7 +936,11 @@ mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen,
379 unsigned long flags;
380 void *dest;
381
382+ if (!dev->relay_fwlog)
383+ return;
384+
385 spin_lock_irqsave(&lock, flags);
386+
387 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
388 if (dest) {
389 *(u32 *)dest = hdrlen + len;
390@@ -868,9 +973,6 @@ void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int
391 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
392 };
393
394- if (!dev->relay_fwlog)
395- return;
396-
397 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++);
398 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
399 hdr.len = *(__le16 *)data;
400diff --git a/mt7996/mac.c b/mt7996/mac.c
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]401index d88bbfb..1f53d23 100644
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]402--- a/mt7996/mac.c
403+++ b/mt7996/mac.c
404@@ -936,6 +936,9 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
405 id = mt76_token_consume(mdev, &t);
406 if (id < 0)
407 return id;
408+#ifdef CONFIG_MTK_DEBUG
409+ t->jiffies = jiffies;
410+#endif
411
412 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
413 memset(txwi_ptr, 0, MT_TXD_SIZE);
414diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]415index e12ad31..696e16f 100644
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]416--- a/mt7996/mt7996.h
417+++ b/mt7996/mt7996.h
418@@ -362,6 +362,7 @@ struct mt7996_dev {
419 u8 fw_debug_wa;
420 u8 fw_debug_bin;
421 u16 fw_debug_seq;
422+ bool fw_debug_muru_disable;
423
424 struct dentry *debugfs_dir;
425 struct rchan *relay_fwlog;
426@@ -374,6 +375,17 @@ struct mt7996_dev {
427 spinlock_t reg_lock;
428
429 u8 wtbl_size_group;
430+
431+#ifdef CONFIG_MTK_DEBUG
432+ u16 wlan_idx;
433+ struct {
434+ u8 sku_disable;
435+ u32 fw_dbg_module;
436+ u8 fw_dbg_lv;
437+ u32 bcn_total_cnt[__MT_MAX_BAND];
438+ } dbg;
439+ const struct mt7996_dbg_reg_desc *dbg_reg;
440+#endif
441 };
442
443 enum {
444@@ -670,6 +682,7 @@ u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
445
446 #ifdef CONFIG_MTK_DEBUG
447 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
448+int mt7996_mcu_muru_dbg_info(struct mt7996_dev *dev, u16 item, u8 val);
449 #endif
450
451 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
452diff --git a/mt7996/mtk_debug.h b/mt7996/mtk_debug.h
453new file mode 100644
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]454index 0000000..27d8f1c
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]455--- /dev/null
456+++ b/mt7996/mtk_debug.h
457@@ -0,0 +1,2286 @@
458+#ifndef __MTK_DEBUG_H
459+#define __MTK_DEBUG_H
460+
461+#ifdef CONFIG_MTK_DEBUG
462+#define NO_SHIFT_DEFINE 0xFFFFFFFF
463+#define BITS(m, n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
464+
465+#define GET_FIELD(_field, _reg) \
466+ ({ \
467+ (((_reg) & (_field##_MASK)) >> (_field##_SHIFT)); \
468+ })
469+
470+#define __DBG_OFFS(id) (dev->dbg_reg->offs_rev[(id)])
471+
472+enum dbg_offs_rev {
473+ AGG_AALCR2,
474+ AGG_AALCR3,
475+ AGG_AALCR4,
476+ AGG_AALCR5,
477+ AGG_AALCR6,
478+ AGG_AALCR7,
479+ MIB_TDRCR0,
480+ MIB_TDRCR1,
481+ MIB_TDRCR2,
482+ MIB_TDRCR3,
483+ MIB_TDRCR4,
484+ MIB_RSCR26,
485+ MIB_TSCR18,
486+ MIB_TRDR0,
487+ MIB_TRDR2,
488+ MIB_TRDR3,
489+ MIB_TRDR4,
490+ MIB_TRDR5,
491+ MIB_TRDR6,
492+ MIB_TRDR7,
493+ MIB_TRDR8,
494+ MIB_TRDR9,
495+ MIB_TRDR10,
496+ MIB_TRDR11,
497+ MIB_TRDR12,
498+ MIB_TRDR13,
499+ MIB_TRDR14,
500+ MIB_TRDR15,
501+ MIB_MSR0,
502+ MIB_MSR1,
503+ MIB_MSR2,
504+ MIB_MCTR5,
505+ MIB_MCTR6,
506+ __MT_DBG_OFFS_REV_MAX,
507+};
508+
509+static const u32 mt7996_dbg_offs[] = {
510+ [AGG_AALCR2] = 0x128,
511+ [AGG_AALCR3] = 0x12c,
512+ [AGG_AALCR4] = 0x130,
513+ [AGG_AALCR5] = 0x134,
514+ [AGG_AALCR6] = 0x138,
515+ [AGG_AALCR7] = 0x13c,
516+ [MIB_TDRCR0] = 0x728,
517+ [MIB_TDRCR1] = 0x72c,
518+ [MIB_TDRCR2] = 0x730,
519+ [MIB_TDRCR3] = 0x734,
520+ [MIB_TDRCR4] = 0x738,
521+ [MIB_RSCR26] = 0x950,
522+ [MIB_TSCR18] = 0xa1c,
523+ [MIB_TRDR0] = 0xa24,
524+ [MIB_TRDR2] = 0xa2c,
525+ [MIB_TRDR3] = 0xa30,
526+ [MIB_TRDR4] = 0xa34,
527+ [MIB_TRDR5] = 0xa38,
528+ [MIB_TRDR6] = 0xa3c,
529+ [MIB_TRDR7] = 0xa40,
530+ [MIB_TRDR8] = 0xa44,
531+ [MIB_TRDR9] = 0xa48,
532+ [MIB_TRDR10] = 0xa4c,
533+ [MIB_TRDR11] = 0xa50,
534+ [MIB_TRDR12] = 0xa54,
535+ [MIB_TRDR13] = 0xa58,
536+ [MIB_TRDR14] = 0xa5c,
537+ [MIB_TRDR15] = 0xa60,
538+ [MIB_MSR0] = 0xa64,
539+ [MIB_MSR1] = 0xa68,
540+ [MIB_MSR2] = 0xa6c,
541+ [MIB_MCTR5] = 0xa70,
542+ [MIB_MCTR6] = 0xa74,
543+};
544+
545+static const u32 mt7992_dbg_offs[] = {
546+ [AGG_AALCR2] = 0x12c,
547+ [AGG_AALCR3] = 0x130,
548+ [AGG_AALCR4] = 0x134,
549+ [AGG_AALCR5] = 0x138,
550+ [AGG_AALCR6] = 0x13c,
551+ [AGG_AALCR7] = 0x140,
552+ [MIB_TDRCR0] = 0x768,
553+ [MIB_TDRCR1] = 0x76c,
554+ [MIB_TDRCR2] = 0x770,
555+ [MIB_TDRCR3] = 0x774,
556+ [MIB_TDRCR4] = 0x778,
557+ [MIB_RSCR26] = 0x994,
558+ [MIB_TSCR18] = 0xb18,
559+ [MIB_TRDR0] = 0xb20,
560+ [MIB_TRDR2] = 0xb28,
561+ [MIB_TRDR3] = 0xb2c,
562+ [MIB_TRDR4] = 0xb30,
563+ [MIB_TRDR5] = 0xb34,
564+ [MIB_TRDR6] = 0xb38,
565+ [MIB_TRDR7] = 0xb3c,
566+ [MIB_TRDR8] = 0xb40,
567+ [MIB_TRDR9] = 0xb44,
568+ [MIB_TRDR10] = 0xb48,
569+ [MIB_TRDR11] = 0xb4c,
570+ [MIB_TRDR12] = 0xb50,
571+ [MIB_TRDR13] = 0xb54,
572+ [MIB_TRDR14] = 0xb58,
573+ [MIB_TRDR15] = 0xb5c,
574+ [MIB_MSR0] = 0xb60,
575+ [MIB_MSR1] = 0xb64,
576+ [MIB_MSR2] = 0xb68,
577+ [MIB_MCTR5] = 0xb6c,
578+ [MIB_MCTR6] = 0xb70,
579+};
580+
581+/* used to differentiate between generations */
582+struct mt7996_dbg_reg_desc {
583+ const u32 id;
584+ const u32 *offs_rev;
585+};
586+
587+/* AGG */
588+#define BN0_WF_AGG_TOP_BASE 0x820e2000
589+#define BN1_WF_AGG_TOP_BASE 0x820f2000
590+#define IP1_BN0_WF_AGG_TOP_BASE 0x830e2000
591+
592+#define BN0_WF_AGG_TOP_SCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x0) // 2000
593+#define BN0_WF_AGG_TOP_SCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x4) // 2004
594+#define BN0_WF_AGG_TOP_SCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x8) // 2008
595+#define BN0_WF_AGG_TOP_BCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xc) // 200C
596+#define BN0_WF_AGG_TOP_BWCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x10) // 2010
597+#define BN0_WF_AGG_TOP_ARCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x14) // 2014
598+#define BN0_WF_AGG_TOP_ARUCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x18) // 2018
599+#define BN0_WF_AGG_TOP_ARDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x1c) // 201C
600+#define BN0_WF_AGG_TOP_AALCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x20) // 2020
601+#define BN0_WF_AGG_TOP_AALCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x24) // 2024
602+#define BN0_WF_AGG_TOP_PCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x28) // 2028
603+#define BN0_WF_AGG_TOP_PCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c) // 202C
604+#define BN0_WF_AGG_TOP_TTCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x30) // 2030
605+#define BN0_WF_AGG_TOP_TTCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x34) // 2034
606+#define BN0_WF_AGG_TOP_ACR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x38) // 2038
607+#define BN0_WF_AGG_TOP_ACR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x3c) // 203C
608+#define BN0_WF_AGG_TOP_ACR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x40) // 2040
609+#define BN0_WF_AGG_TOP_ACR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x44) // 2044
610+#define BN0_WF_AGG_TOP_ACR8_ADDR (BN0_WF_AGG_TOP_BASE + 0x4c) // 204C
611+#define BN0_WF_AGG_TOP_MRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x50) // 2050
612+#define BN0_WF_AGG_TOP_MMPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x54) // 2054
613+#define BN0_WF_AGG_TOP_GFPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x58) // 2058
614+#define BN0_WF_AGG_TOP_VHTPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x5c) // 205C
615+#define BN0_WF_AGG_TOP_HEPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x60) // 2060
616+#define BN0_WF_AGG_TOP_CTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x64) // 2064
617+#define BN0_WF_AGG_TOP_ATCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x68) // 2068
618+#define BN0_WF_AGG_TOP_SRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x6c) // 206C
619+#define BN0_WF_AGG_TOP_VBCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x70) // 2070
620+#define BN0_WF_AGG_TOP_TCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x74) // 2074
621+#define BN0_WF_AGG_TOP_SRHS_ADDR (BN0_WF_AGG_TOP_BASE + 0x78) // 2078
622+#define BN0_WF_AGG_TOP_DBRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x7c) // 207C
623+#define BN0_WF_AGG_TOP_DBRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x80) // 2080
624+#define BN0_WF_AGG_TOP_CTETCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x84) // 2084
625+#define BN0_WF_AGG_TOP_WPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x88) // 2088
626+#define BN0_WF_AGG_TOP_PLRPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x8c) // 208C
627+#define BN0_WF_AGG_TOP_CECR_ADDR (BN0_WF_AGG_TOP_BASE + 0x90) // 2090
628+#define BN0_WF_AGG_TOP_OMRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x94) // 2094
629+#define BN0_WF_AGG_TOP_OMRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x98) // 2098
630+#define BN0_WF_AGG_TOP_OMRCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x9c) // 209C
631+#define BN0_WF_AGG_TOP_OMRCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xa0) // 20A0
632+#define BN0_WF_AGG_TOP_TMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa4) // 20A4
633+#define BN0_WF_AGG_TOP_TWTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa8) // 20A8
634+#define BN0_WF_AGG_TOP_TWTSTACR_ADDR (BN0_WF_AGG_TOP_BASE + 0xac) // 20AC
635+#define BN0_WF_AGG_TOP_TWTE0TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb0) // 20B0
636+#define BN0_WF_AGG_TOP_TWTE1TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb4) // 20B4
637+#define BN0_WF_AGG_TOP_TWTE2TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb8) // 20B8
638+#define BN0_WF_AGG_TOP_TWTE3TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xbc) // 20BC
639+#define BN0_WF_AGG_TOP_TWTE4TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc0) // 20C0
640+#define BN0_WF_AGG_TOP_TWTE5TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc4) // 20C4
641+#define BN0_WF_AGG_TOP_TWTE6TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc8) // 20C8
642+#define BN0_WF_AGG_TOP_TWTE7TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xcc) // 20CC
643+#define BN0_WF_AGG_TOP_TWTE8TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd0) // 20D0
644+#define BN0_WF_AGG_TOP_TWTE9TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd4) // 20D4
645+#define BN0_WF_AGG_TOP_TWTEATB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd8) // 20D8
646+#define BN0_WF_AGG_TOP_TWTEBTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xdc) // 20DC
647+#define BN0_WF_AGG_TOP_TWTECTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe0) // 20E0
648+#define BN0_WF_AGG_TOP_TWTEDTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe4) // 20E4
649+#define BN0_WF_AGG_TOP_TWTEETB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe8) // 20E8
650+#define BN0_WF_AGG_TOP_TWTEFTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xec) // 20EC
651+#define BN0_WF_AGG_TOP_ATCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x108) // 2108
652+#define BN0_WF_AGG_TOP_ATCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x10c) // 210C
653+#define BN0_WF_AGG_TOP_TCCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x110) // 2110
654+#define BN0_WF_AGG_TOP_TFCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x114) // 2114
655+#define BN0_WF_AGG_TOP_MUCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x118) // 2118
656+#define BN0_WF_AGG_TOP_MUCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x11c) // 211C
657+#define BN0_WF_AGG_TOP_AALCR2_ADDR (BN0_WF_AGG_TOP_BASE + __DBG_OFFS(AGG_AALCR2))
658+#define BN0_WF_AGG_TOP_AALCR3_ADDR (BN0_WF_AGG_TOP_BASE + __DBG_OFFS(AGG_AALCR3))
659+#define BN0_WF_AGG_TOP_AALCR4_ADDR (BN0_WF_AGG_TOP_BASE + __DBG_OFFS(AGG_AALCR4))
660+#define BN0_WF_AGG_TOP_AALCR5_ADDR (BN0_WF_AGG_TOP_BASE + __DBG_OFFS(AGG_AALCR5))
661+#define BN0_WF_AGG_TOP_AALCR6_ADDR (BN0_WF_AGG_TOP_BASE + __DBG_OFFS(AGG_AALCR6))
662+#define BN0_WF_AGG_TOP_AALCR7_ADDR (BN0_WF_AGG_TOP_BASE + __DBG_OFFS(AGG_AALCR7))
663+#define BN0_WF_AGG_TOP_CSDCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x150) // 2150
664+#define BN0_WF_AGG_TOP_CSDCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x154) // 2154
665+#define BN0_WF_AGG_TOP_CSDCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x158) // 2158
666+#define BN0_WF_AGG_TOP_CSDCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x15c) // 215C
667+#define BN0_WF_AGG_TOP_CSDCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x160) // 2160
668+#define BN0_WF_AGG_TOP_DYNSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x178) // 2178
669+#define BN0_WF_AGG_TOP_DYNSSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x198) // 2198
670+#define BN0_WF_AGG_TOP_TCDCNT0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c8) // 22C8
671+#define BN0_WF_AGG_TOP_TCDCNT1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2cc) // 22CC
672+#define BN0_WF_AGG_TOP_TCSR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d0) // 22D0
673+#define BN0_WF_AGG_TOP_TCSR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d4) // 22D4
674+#define BN0_WF_AGG_TOP_TCSR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d8) // 22D8
675+#define BN0_WF_AGG_TOP_DCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e4) // 22E4
676+#define BN0_WF_AGG_TOP_SMDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e8) // 22E8
677+#define BN0_WF_AGG_TOP_TXCMDSMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2ec) // 22EC
678+#define BN0_WF_AGG_TOP_SMCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f0) // 22F0
679+#define BN0_WF_AGG_TOP_SMCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f4) // 22F4
680+#define BN0_WF_AGG_TOP_SMCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f8) // 22F8
681+#define BN0_WF_AGG_TOP_SMCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x2fc) // 22FC
682+
683+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
684+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK 0x03FF0000 // AC01_AGG_LIMIT[25..16]
685+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT 16
686+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
687+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK 0x000003FF // AC00_AGG_LIMIT[9..0]
688+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT 0
689+
690+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
691+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK 0x03FF0000 // AC03_AGG_LIMIT[25..16]
692+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT 16
693+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
694+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK 0x000003FF // AC02_AGG_LIMIT[9..0]
695+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT 0
696+
697+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
698+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK 0x03FF0000 // AC11_AGG_LIMIT[25..16]
699+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT 16
700+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
701+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK 0x000003FF // AC10_AGG_LIMIT[9..0]
702+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT 0
703+
704+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
705+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK 0x03FF0000 // AC13_AGG_LIMIT[25..16]
706+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT 16
707+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
708+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK 0x000003FF // AC12_AGG_LIMIT[9..0]
709+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT 0
710+
711+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
712+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK 0x03FF0000 // AC21_AGG_LIMIT[25..16]
713+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT 16
714+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
715+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK 0x000003FF // AC20_AGG_LIMIT[9..0]
716+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT 0
717+
718+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
719+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK 0x03FF0000 // AC23_AGG_LIMIT[25..16]
720+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT 16
721+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
722+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK 0x000003FF // AC22_AGG_LIMIT[9..0]
723+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT 0
724+
725+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
726+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK 0x03FF0000 // AC31_AGG_LIMIT[25..16]
727+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT 16
728+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
729+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK 0x000003FF // AC30_AGG_LIMIT[9..0]
730+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT 0
731+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
732+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK 0x03FF0000 // AC33_AGG_LIMIT[25..16]
733+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT 16
734+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
735+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK 0x000003FF // AC32_AGG_LIMIT[9..0]
736+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT 0
737+
738+/* DMA */
739+struct queue_desc {
740+ u32 hw_desc_base;
741+ u16 ring_size;
742+ char *const ring_info;
743+};
744+
745+// HOST DMA
746+#define WF_WFDMA_HOST_DMA0_BASE 0xd4000
747+
748+#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \
749+ (WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */
750+#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \
751+ (WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */
752+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \
753+ (WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */
754+
755+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR \
756+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
757+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK \
758+ 0x00000008 /* RX_DMA_BUSY[3] */
759+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
760+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR \
761+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
762+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK \
763+ 0x00000004 /* RX_DMA_EN[2] */
764+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
765+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR \
766+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
767+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK \
768+ 0x00000002 /* TX_DMA_BUSY[1] */
769+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
770+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR \
771+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
772+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK \
773+ 0x00000001 /* TX_DMA_EN[0] */
774+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
775+
776+
777+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \
778+ (WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */
779+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \
780+ (WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */
781+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \
782+ (WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */
783+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \
784+ (WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */
785+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \
786+ (WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */
787+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \
788+ (WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */
789+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \
790+ (WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */
791+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \
792+ (WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */
793+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \
794+ (WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */
795+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \
796+ (WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */
797+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \
798+ (WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */
799+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \
800+ (WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */
801+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \
802+ (WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */
803+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \
804+ (WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */
805+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \
806+ (WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */
807+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \
808+ (WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */
809+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \
810+ (WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */
811+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \
812+ (WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */
813+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \
814+ (WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */
815+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \
816+ (WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */
817+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \
818+ (WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */
819+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \
820+ (WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */
821+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \
822+ (WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */
823+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \
824+ (WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */
825+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \
826+ (WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */
827+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \
828+ (WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */
829+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \
830+ (WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */
831+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \
832+ (WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */
833+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \
834+ (WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */
835+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \
836+ (WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */
837+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \
838+ (WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */
839+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \
840+ (WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */
841+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \
842+ (WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */
843+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \
844+ (WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */
845+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \
846+ (WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */
847+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \
848+ (WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */
849+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \
850+ (WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */
851+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \
852+ (WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */
853+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \
854+ (WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */
855+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \
856+ (WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */
857+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \
858+ (WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */
859+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \
860+ (WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */
861+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \
862+ (WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */
863+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \
864+ (WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */
865+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \
866+ (WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */
867+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \
868+ (WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */
869+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \
870+ (WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */
871+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \
872+ (WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */
873+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR \
874+ (WF_WFDMA_HOST_DMA0_BASE + 0x450) /* 4450 */
875+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL1_ADDR \
876+ (WF_WFDMA_HOST_DMA0_BASE + 0x454) /* 4454 */
877+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL2_ADDR \
878+ (WF_WFDMA_HOST_DMA0_BASE + 0x458) /* 4458 */
879+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL3_ADDR \
880+ (WF_WFDMA_HOST_DMA0_BASE + 0x45c) /* 445c */
881+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x460) // 4460
882+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x464) // 4464
883+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x468) // 4468
884+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x46c) // 446C
885+
886+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \
887+ (WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */
888+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \
889+ (WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */
890+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \
891+ (WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */
892+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \
893+ (WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */
894+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \
895+ (WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */
896+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \
897+ (WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */
898+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \
899+ (WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */
900+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \
901+ (WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */
902+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \
903+ (WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */
904+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \
905+ (WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */
906+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \
907+ (WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */
908+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \
909+ (WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */
910+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \
911+ (WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */
912+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \
913+ (WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */
914+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \
915+ (WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */
916+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \
917+ (WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */
918+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \
919+ (WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */
920+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \
921+ (WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */
922+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \
923+ (WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */
924+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \
925+ (WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */
926+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \
927+ (WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */
928+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \
929+ (WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */
930+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \
931+ (WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */
932+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \
933+ (WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */
934+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \
935+ (WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */
936+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \
937+ (WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */
938+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \
939+ (WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */
940+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \
941+ (WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */
942+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \
943+ (WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */
944+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \
945+ (WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */
946+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \
947+ (WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */
948+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \
949+ (WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */
950+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \
951+ (WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */
952+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \
953+ (WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */
954+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \
955+ (WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */
956+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \
957+ (WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */
958+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \
959+ (WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */
960+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \
961+ (WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */
962+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \
963+ (WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */
964+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \
965+ (WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */
966+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a0) // 45A0
967+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a4) // 45A4
968+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a8) // 45A8
969+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5ac) // 45AC
970+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b0) // 45B0
971+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b4) // 45B4
972+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b8) // 45B8
973+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5bc) // 45BC
974+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C0) // 45C0
975+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C4) // 45C4
976+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C8) // 45C8
977+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5CC) // 45CC
978+
979+// HOST PCIE1 DMA
980+#define WF_WFDMA_HOST_DMA0_PCIE1_BASE 0xd8000
981+
982+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x200) // 8200
983+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0X204) // 8204
984+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x208) // 8208
985+
986+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_PDMA_BT_SIZE_SHFT 4
987+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008
988+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
989+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004
990+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
991+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002
992+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
993+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001
994+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
995+
996+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x450) // 8450
997+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x454) // 8454
998+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x458) // 8458
999+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x45c) // 845C
1000+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x460) // 8460
1001+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x464) // 8464
1002+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x468) // 8468
1003+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x46c) // 846C
1004+
1005+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x530) // 8530
1006+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x534) // 8534
1007+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x538) // 8538
1008+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x53C) // 853C
1009+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x550) // 8550
1010+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x554) // 8554
1011+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x558) // 8558
1012+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x55c) // 855C
1013+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x560) // 8560
1014+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x564) // 8564
1015+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x568) // 8568
1016+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x56c) // 856C
1017+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x570) // 8570
1018+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x574) // 8574
1019+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x578) // 8578
1020+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x57c) // 857C
1021+//MCU DMA
1022+//#define WF_WFDMA_MCU_DMA0_BASE 0x02000
1023+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1024+
1025+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1026+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1027+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1028+
1029+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
1030+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1031+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1032+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
1033+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1034+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1035+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
1036+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1037+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1038+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
1039+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1040+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1041+
1042+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1043+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x304) // 0304
1044+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x308) // 0308
1045+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x30c) // 030C
1046+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1047+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x314) // 0314
1048+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x318) // 0318
1049+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x31c) // 031C
1050+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1051+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x324) // 0324
1052+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x328) // 0328
1053+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x32c) // 032C
1054+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1055+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x334) // 0334
1056+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x338) // 0338
1057+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x33c) // 033C
1058+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1059+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x344) // 0344
1060+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x348) // 0348
1061+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x34c) // 034C
1062+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1063+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x354) // 0354
1064+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x358) // 0358
1065+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x35c) // 035C
1066+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1067+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x364) // 0364
1068+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x368) // 0368
1069+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x36c) // 036C
1070+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x370) // 0370
1071+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x374) // 0374
1072+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x378) // 0378
1073+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x37c) // 037C
1074+
1075+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1076+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x504) // 0504
1077+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x508) // 0508
1078+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x50c) // 050C
1079+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1080+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x514) // 0514
1081+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x518) // 0518
1082+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x51c) // 051C
1083+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1084+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x524) // 0524
1085+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x528) // 0528
1086+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x52C) // 052C
1087+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1088+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x534) // 0534
1089+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x538) // 0538
1090+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x53C) // 053C
1091+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1092+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x544) // 0544
1093+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x548) // 0548
1094+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x54C) // 054C
1095+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1096+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x554) // 0554
1097+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x558) // 0558
1098+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x55C) // 055C
1099+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1100+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x564) // 0564
1101+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x568) // 0568
1102+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x56c) // 056C
1103+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1104+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x574) // 0574
1105+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x578) // 0578
1106+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x57c) // 057C
1107+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1108+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x584) // 0584
1109+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x588) // 0588
1110+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x58c) // 058C
1111+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1112+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x594) // 0594
1113+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x598) // 0598
1114+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x59c) // 059C
1115+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A0) // 05A0
1116+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A4) // 05A4
1117+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A8) // 05A8
1118+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5Ac) // 05AC
1119+
1120+// MEM DMA
1121+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1122+
1123+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1124+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1125+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1126+
1127+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
1128+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1129+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1130+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
1131+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1132+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1133+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
1134+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1135+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1136+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
1137+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1138+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1139+
1140+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1141+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x304) // 0304
1142+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x308) // 0308
1143+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x30c) // 030C
1144+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1145+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x314) // 0314
1146+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x318) // 0318
1147+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x31c) // 031C
1148+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x320) // 0320
1149+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x324) // 0324
1150+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x328) // 0328
1151+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x32c) // 032C
1152+
1153+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1154+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x504) // 0504
1155+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x508) // 0508
1156+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x50c) // 050C
1157+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1158+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x514) // 0514
1159+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x518) // 0518
1160+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x51c) // 051C
1161+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x520) // 0520
1162+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x524) // 0524
1163+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x528) // 0528
1164+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x52C) // 052C
1165+
1166+/* MIB */
1167+#define WF_UMIB_TOP_BASE 0x820cd000
1168+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1169+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1170+#define IP1_BN0_WF_MIB_TOP_BASE 0x830ed000
1171+
1172+#define WF_UMIB_TOP_B0BROCR_ADDR (WF_UMIB_TOP_BASE + 0x484) // D484
1173+#define WF_UMIB_TOP_B0BRBCR_ADDR (WF_UMIB_TOP_BASE + 0x4D4) // D4D4
1174+#define WF_UMIB_TOP_B0BRDCR_ADDR (WF_UMIB_TOP_BASE + 0x524) // D524
1175+#define WF_UMIB_TOP_B1BROCR_ADDR (WF_UMIB_TOP_BASE + 0x5E8) // D5E8
1176+#define WF_UMIB_TOP_B2BROCR_ADDR (WF_UMIB_TOP_BASE + 0x74C) // D74C
1177+
1178+#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x000) // D000
1179+#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x020) // D020
1180+#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x024) // D024
1181+#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x030) // D030
1182+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1183+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x450) // D450
1184+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x590) // D590
1185+#define BN0_WF_MIB_TOP_BTCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5A0) // D5A0
1186+#define BN0_WF_MIB_TOP_RVSR0_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_RVSR0))
1187+
1188+#define BN0_WF_MIB_TOP_TSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B0) // D6B0
1189+#define BN0_WF_MIB_TOP_TSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6BC) // D6BC
1190+#define BN0_WF_MIB_TOP_TSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C0) // D6C0
1191+#define BN0_WF_MIB_TOP_TSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C4) // D6C4
1192+#define BN0_WF_MIB_TOP_TSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C8) // D6C8
1193+#define BN0_WF_MIB_TOP_TSCR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x6D0) // D6D0
1194+#define BN0_WF_MIB_TOP_TSCR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x6CC) // D6CC
1195+
1196+#define BN0_WF_MIB_TOP_TBCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6EC) // D6EC
1197+#define BN0_WF_MIB_TOP_TBCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F0) // D6F0
1198+#define BN0_WF_MIB_TOP_TBCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F4) // D6F4
1199+#define BN0_WF_MIB_TOP_TBCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F8) // D6F8
1200+#define BN0_WF_MIB_TOP_TBCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6FC) // D6FC
1201+
1202+#define BN0_WF_MIB_TOP_TDRCR0_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TDRCR0))
1203+#define BN0_WF_MIB_TOP_TDRCR1_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TDRCR1))
1204+#define BN0_WF_MIB_TOP_TDRCR2_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TDRCR2))
1205+#define BN0_WF_MIB_TOP_TDRCR3_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TDRCR3))
1206+#define BN0_WF_MIB_TOP_TDRCR4_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TDRCR4))
1207+
1208+#define BN0_WF_MIB_TOP_BTSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1209+#define BN0_WF_MIB_TOP_BTSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x5F0) // D5F0
1210+#define BN0_WF_MIB_TOP_BTSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x600) // D600
1211+#define BN0_WF_MIB_TOP_BTSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x610) // D610
1212+#define BN0_WF_MIB_TOP_BTSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x620) // D620
1213+#define BN0_WF_MIB_TOP_BTSCR5_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_BTSCR5))
1214+#define BN0_WF_MIB_TOP_BTSCR6_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_BTSCR6))
1215+
1216+#define BN0_WF_MIB_TOP_RSCR1_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_RSCR1))
1217+#define BN0_WF_MIB_TOP_BSCR2_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_BSCR2))
1218+#define BN0_WF_MIB_TOP_TSCR18_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TSCR18))
1219+
1220+#define BN0_WF_MIB_TOP_MSR0_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_MSR0))
1221+#define BN0_WF_MIB_TOP_MSR1_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_MSR1))
1222+#define BN0_WF_MIB_TOP_MSR2_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_MSR2))
1223+#define BN0_WF_MIB_TOP_MCTR5_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_MCTR5))
1224+#define BN0_WF_MIB_TOP_MCTR6_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_MCTR6))
1225+
1226+#define BN0_WF_MIB_TOP_RSCR26_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_RSCR26))
1227+#define BN0_WF_MIB_TOP_RSCR27_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_RSCR27))
1228+#define BN0_WF_MIB_TOP_RSCR28_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_RSCR28))
1229+#define BN0_WF_MIB_TOP_RSCR31_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_RSCR31))
1230+#define BN0_WF_MIB_TOP_RSCR33_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_RSCR33))
1231+#define BN0_WF_MIB_TOP_RSCR35_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_RSCR35))
1232+#define BN0_WF_MIB_TOP_RSCR36_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_RSCR36))
1233+
1234+#define BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK 0xFFFFFFFF // AMPDU_MPDU_COUNT[31..0]
1235+#define BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK 0xFFFFFFFF // AMPDU_ACKED_COUNT[31..0]
1236+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1237+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1238+#define BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK 0xFFFFFFFF // RX_MDRDY_COUNT[31..0]
1239+#define BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK 0xFFFFFFFF // CCK_MDRDY_TIME[31..0]
1240+#define BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[31..0]
1241+#define BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_GREEN_MDRDY_TIME[31..0]
1242+#define BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK 0xFFFFFFFF // P_CCA_TIME[31..0]
1243+#define BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK 0xFFFFFFFF // S_CCA_TIME[31..0]
1244+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1245+#define BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK 0xFFFFFFFF // BEACONTXCOUNT[31..0]
1246+#define BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK 0xFFFFFFFF // TX_20MHZ_CNT[31..0]
1247+#define BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK 0xFFFFFFFF // TX_40MHZ_CNT[31..0]
1248+#define BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK 0xFFFFFFFF // TX_80MHZ_CNT[31..0]
1249+#define BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK 0xFFFFFFFF // TX_160MHZ_CNT[31..0]
1250+#define BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK 0xFFFFFFFF // TX_320MHZ_CNT[31..0]
1251+#define BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK 0xFFFFFFFF // MUBF_TX_COUNT[31..0]
1252+#define BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK 0xFFFFFFFF // VEC_MISS_COUNT[31..0]
1253+#define BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK 0xFFFFFFFF // DELIMITER_FAIL_COUNT[31..0]
1254+#define BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK 0xFFFFFFFF // RX_FCS_ERROR_COUNT[31..0]
1255+#define BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK 0xFFFFFFFF // RX_FIFO_FULL_COUNT[31..0]
1256+#define BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK 0xFFFFFFFF // RX_LEN_MISMATCH[31..0]
1257+#define BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1258+#define BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK 0xFFFFFFFF // RTSTXCOUNTn[31..0]
1259+#define BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK 0xFFFFFFFF // RTSRETRYCOUNTn[31..0]
1260+#define BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK 0xFFFFFFFF // BAMISSCOUNTn[31..0]
1261+#define BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK 0xFFFFFFFF // ACKFAILCOUNTn[31..0]
1262+#define BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK 0xFFFFFFFF // FRAMERETRYCOUNTn[31..0]
1263+#define BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK 0xFFFFFFFF // FRAMERETRY2COUNTn[31..0]
1264+#define BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK 0xFFFFFFFF // FRAMERETRY3COUNTn[31..0]
1265+#define BN0_WF_MIB_TOP_TRARC0_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B0) // D0B0
1266+#define BN0_WF_MIB_TOP_TRARC1_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B4) // D0B4
1267+#define BN0_WF_MIB_TOP_TRARC2_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B8) // D0B8
1268+#define BN0_WF_MIB_TOP_TRARC3_ADDR (BN0_WF_MIB_TOP_BASE + 0x0BC) // D0BC
1269+#define BN0_WF_MIB_TOP_TRARC4_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C0) // D0C0
1270+#define BN0_WF_MIB_TOP_TRARC5_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C4) // D0C4
1271+#define BN0_WF_MIB_TOP_TRARC6_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C8) // D0C8
1272+#define BN0_WF_MIB_TOP_TRARC7_ADDR (BN0_WF_MIB_TOP_BASE + 0x0CC) // D0CC
1273+
1274+#define BN0_WF_MIB_TOP_TRDR0_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR0))
1275+#define BN0_WF_MIB_TOP_TRDR1_ADDR (BN0_WF_MIB_TOP_BASE + __OFFS(MIB_TRDR1))
1276+#define BN0_WF_MIB_TOP_TRDR2_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR2))
1277+#define BN0_WF_MIB_TOP_TRDR3_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR3))
1278+#define BN0_WF_MIB_TOP_TRDR4_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR4))
1279+#define BN0_WF_MIB_TOP_TRDR5_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR5))
1280+#define BN0_WF_MIB_TOP_TRDR6_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR6))
1281+#define BN0_WF_MIB_TOP_TRDR7_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR7))
1282+#define BN0_WF_MIB_TOP_TRDR8_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR8))
1283+#define BN0_WF_MIB_TOP_TRDR9_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR9))
1284+#define BN0_WF_MIB_TOP_TRDR10_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR10))
1285+#define BN0_WF_MIB_TOP_TRDR11_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR11))
1286+#define BN0_WF_MIB_TOP_TRDR12_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR12))
1287+#define BN0_WF_MIB_TOP_TRDR13_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR13))
1288+#define BN0_WF_MIB_TOP_TRDR14_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR14))
1289+#define BN0_WF_MIB_TOP_TRDR15_ADDR (BN0_WF_MIB_TOP_BASE + __DBG_OFFS(MIB_TRDR15))
1290+
1291+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
1292+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK 0x03FF0000 // AGG_RANG_SEL_1[25..16]
1293+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT 16
1294+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
1295+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK 0x000003FF // AGG_RANG_SEL_0[9..0]
1296+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT 0
1297+
1298+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
1299+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK 0x03FF0000 // AGG_RANG_SEL_3[25..16]
1300+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT 16
1301+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
1302+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK 0x000003FF // AGG_RANG_SEL_2[9..0]
1303+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT 0
1304+
1305+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
1306+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK 0x03FF0000 // AGG_RANG_SEL_5[25..16]
1307+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT 16
1308+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
1309+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK 0x000003FF // AGG_RANG_SEL_4[9..0]
1310+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT 0
1311+
1312+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
1313+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK 0x03FF0000 // AGG_RANG_SEL_7[25..16]
1314+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT 16
1315+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
1316+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK 0x000003FF // AGG_RANG_SEL_6[9..0]
1317+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT 0
1318+
1319+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
1320+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK 0x03FF0000 // AGG_RANG_SEL_9[25..16]
1321+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT 16
1322+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
1323+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK 0x000003FF // AGG_RANG_SEL_8[9..0]
1324+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT 0
1325+
1326+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
1327+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK 0x03FF0000 // AGG_RANG_SEL_11[25..16]
1328+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT 16
1329+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
1330+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK 0x000003FF // AGG_RANG_SEL_10[9..0]
1331+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT 0
1332+
1333+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
1334+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK 0x03FF0000 // AGG_RANG_SEL_13[25..16]
1335+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT 16
1336+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
1337+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK 0x000003FF // AGG_RANG_SEL_12[9..0]
1338+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT 0
1339+
1340+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_ADDR BN0_WF_MIB_TOP_TRARC7_ADDR
1341+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK 0x000003FF // AGG_RANG_SEL_14[9..0]
1342+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT 0
1343+
1344+/* RRO TOP */
1345+#define WF_RRO_TOP_BASE 0xA000 /*0x820C2000 */
1346+#define WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR (WF_RRO_TOP_BASE + 0x40) // 2040
1347+ //
1348+/* WTBL */
1349+enum mt7996_wtbl_type {
1350+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1351+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1352+ WTBL_TYPE_KEY, /* Key Table */
1353+ MAX_NUM_WTBL_TYPE
1354+};
1355+
1356+struct berse_wtbl_parse {
1357+ u8 *name;
1358+ u32 mask;
1359+ u32 shift;
1360+ u8 new_line;
1361+};
1362+
1363+enum muar_idx {
1364+ MUAR_INDEX_OWN_MAC_ADDR_0 = 0,
1365+ MUAR_INDEX_OWN_MAC_ADDR_1,
1366+ MUAR_INDEX_OWN_MAC_ADDR_2,
1367+ MUAR_INDEX_OWN_MAC_ADDR_3,
1368+ MUAR_INDEX_OWN_MAC_ADDR_4,
1369+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC = 0xE,
1370+ MUAR_INDEX_UNMATCHED = 0xF,
1371+ MUAR_INDEX_OWN_MAC_ADDR_11 = 0x11,
1372+ MUAR_INDEX_OWN_MAC_ADDR_12,
1373+ MUAR_INDEX_OWN_MAC_ADDR_13,
1374+ MUAR_INDEX_OWN_MAC_ADDR_14,
1375+ MUAR_INDEX_OWN_MAC_ADDR_15,
1376+ MUAR_INDEX_OWN_MAC_ADDR_16,
1377+ MUAR_INDEX_OWN_MAC_ADDR_17,
1378+ MUAR_INDEX_OWN_MAC_ADDR_18,
1379+ MUAR_INDEX_OWN_MAC_ADDR_19,
1380+ MUAR_INDEX_OWN_MAC_ADDR_1A,
1381+ MUAR_INDEX_OWN_MAC_ADDR_1B,
1382+ MUAR_INDEX_OWN_MAC_ADDR_1C,
1383+ MUAR_INDEX_OWN_MAC_ADDR_1D,
1384+ MUAR_INDEX_OWN_MAC_ADDR_1E,
1385+ MUAR_INDEX_OWN_MAC_ADDR_1F,
1386+ MUAR_INDEX_OWN_MAC_ADDR_20,
1387+ MUAR_INDEX_OWN_MAC_ADDR_21,
1388+ MUAR_INDEX_OWN_MAC_ADDR_22,
1389+ MUAR_INDEX_OWN_MAC_ADDR_23,
1390+ MUAR_INDEX_OWN_MAC_ADDR_24,
1391+ MUAR_INDEX_OWN_MAC_ADDR_25,
1392+ MUAR_INDEX_OWN_MAC_ADDR_26,
1393+ MUAR_INDEX_OWN_MAC_ADDR_27,
1394+ MUAR_INDEX_OWN_MAC_ADDR_28,
1395+ MUAR_INDEX_OWN_MAC_ADDR_29,
1396+ MUAR_INDEX_OWN_MAC_ADDR_2A,
1397+ MUAR_INDEX_OWN_MAC_ADDR_2B,
1398+ MUAR_INDEX_OWN_MAC_ADDR_2C,
1399+ MUAR_INDEX_OWN_MAC_ADDR_2D,
1400+ MUAR_INDEX_OWN_MAC_ADDR_2E,
1401+ MUAR_INDEX_OWN_MAC_ADDR_2F
1402+};
1403+
1404+enum cipher_suit {
1405+ IGTK_CIPHER_SUIT_NONE = 0,
1406+ IGTK_CIPHER_SUIT_BIP,
1407+ IGTK_CIPHER_SUIT_BIP_256
1408+};
1409+
1410+#define LWTBL_LEN_IN_DW 36
1411+#define UWTBL_LEN_IN_DW 16
1412+
1413+#define MT_DBG_WTBL_BASE 0x820D8000
1414+
1415+#define MT_DBG_WTBLON_TOP_BASE 0x820d4000
1416+#define MT_DBG_WTBLON_TOP_WDUCR_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x0370) // 4370
1417+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
1418+
1419+#define MT_DBG_UWTBL_TOP_BASE 0x820c4000
1420+#define MT_DBG_UWTBL_TOP_WDUCR_ADDR (MT_DBG_UWTBL_TOP_BASE + 0x0104) // 4104
1421+#define MT_DBG_UWTBL_TOP_WDUCR_GROUP GENMASK(5, 0)
1422+#define MT_DBG_UWTBL_TOP_WDUCR_TARGET BIT(31)
1423+
1424+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1425+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1426+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1427+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1428+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1429+
1430+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1431+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1432+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1433+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1434+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1435+
1436+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1437+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1438+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1439+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1440+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1441+
1442+// UMAC WTBL
1443+// DW0
1444+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__DW 0
1445+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__ADDR 0
1446+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__MASK 0x0000ffff // 15- 0
1447+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__SHIFT 0
1448+#define WF_UWTBL_OWN_MLD_ID_DW 0
1449+#define WF_UWTBL_OWN_MLD_ID_ADDR 0
1450+#define WF_UWTBL_OWN_MLD_ID_MASK 0x003f0000 // 21-16
1451+#define WF_UWTBL_OWN_MLD_ID_SHIFT 16
1452+// DW1
1453+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__DW 1
1454+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__ADDR 4
1455+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__MASK 0xffffffff // 31- 0
1456+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__SHIFT 0
1457+// DW2
1458+#define WF_UWTBL_PN_31_0__DW 2
1459+#define WF_UWTBL_PN_31_0__ADDR 8
1460+#define WF_UWTBL_PN_31_0__MASK 0xffffffff // 31- 0
1461+#define WF_UWTBL_PN_31_0__SHIFT 0
1462+// DW3
1463+#define WF_UWTBL_PN_47_32__DW 3
1464+#define WF_UWTBL_PN_47_32__ADDR 12
1465+#define WF_UWTBL_PN_47_32__MASK 0x0000ffff // 15- 0
1466+#define WF_UWTBL_PN_47_32__SHIFT 0
1467+#define WF_UWTBL_COM_SN_DW 3
1468+#define WF_UWTBL_COM_SN_ADDR 12
1469+#define WF_UWTBL_COM_SN_MASK 0x0fff0000 // 27-16
1470+#define WF_UWTBL_COM_SN_SHIFT 16
1471+// DW4
1472+#define WF_UWTBL_TID0_SN_DW 4
1473+#define WF_UWTBL_TID0_SN_ADDR 16
1474+#define WF_UWTBL_TID0_SN_MASK 0x00000fff // 11- 0
1475+#define WF_UWTBL_TID0_SN_SHIFT 0
1476+#define WF_UWTBL_RX_BIPN_31_0__DW 4
1477+#define WF_UWTBL_RX_BIPN_31_0__ADDR 16
1478+#define WF_UWTBL_RX_BIPN_31_0__MASK 0xffffffff // 31- 0
1479+#define WF_UWTBL_RX_BIPN_31_0__SHIFT 0
1480+#define WF_UWTBL_TID1_SN_DW 4
1481+#define WF_UWTBL_TID1_SN_ADDR 16
1482+#define WF_UWTBL_TID1_SN_MASK 0x00fff000 // 23-12
1483+#define WF_UWTBL_TID1_SN_SHIFT 12
1484+#define WF_UWTBL_TID2_SN_7_0__DW 4
1485+#define WF_UWTBL_TID2_SN_7_0__ADDR 16
1486+#define WF_UWTBL_TID2_SN_7_0__MASK 0xff000000 // 31-24
1487+#define WF_UWTBL_TID2_SN_7_0__SHIFT 24
1488+// DW5
1489+#define WF_UWTBL_TID2_SN_11_8__DW 5
1490+#define WF_UWTBL_TID2_SN_11_8__ADDR 20
1491+#define WF_UWTBL_TID2_SN_11_8__MASK 0x0000000f // 3- 0
1492+#define WF_UWTBL_TID2_SN_11_8__SHIFT 0
1493+#define WF_UWTBL_RX_BIPN_47_32__DW 5
1494+#define WF_UWTBL_RX_BIPN_47_32__ADDR 20
1495+#define WF_UWTBL_RX_BIPN_47_32__MASK 0x0000ffff // 15- 0
1496+#define WF_UWTBL_RX_BIPN_47_32__SHIFT 0
1497+#define WF_UWTBL_TID3_SN_DW 5
1498+#define WF_UWTBL_TID3_SN_ADDR 20
1499+#define WF_UWTBL_TID3_SN_MASK 0x0000fff0 // 15- 4
1500+#define WF_UWTBL_TID3_SN_SHIFT 4
1501+#define WF_UWTBL_TID4_SN_DW 5
1502+#define WF_UWTBL_TID4_SN_ADDR 20
1503+#define WF_UWTBL_TID4_SN_MASK 0x0fff0000 // 27-16
1504+#define WF_UWTBL_TID4_SN_SHIFT 16
1505+#define WF_UWTBL_TID5_SN_3_0__DW 5
1506+#define WF_UWTBL_TID5_SN_3_0__ADDR 20
1507+#define WF_UWTBL_TID5_SN_3_0__MASK 0xf0000000 // 31-28
1508+#define WF_UWTBL_TID5_SN_3_0__SHIFT 28
1509+// DW6
1510+#define WF_UWTBL_TID5_SN_11_4__DW 6
1511+#define WF_UWTBL_TID5_SN_11_4__ADDR 24
1512+#define WF_UWTBL_TID5_SN_11_4__MASK 0x000000ff // 7- 0
1513+#define WF_UWTBL_TID5_SN_11_4__SHIFT 0
1514+#define WF_UWTBL_KEY_LOC2_DW 6
1515+#define WF_UWTBL_KEY_LOC2_ADDR 24
1516+#define WF_UWTBL_KEY_LOC2_MASK 0x00001fff // 12- 0
1517+#define WF_UWTBL_KEY_LOC2_SHIFT 0
1518+#define WF_UWTBL_TID6_SN_DW 6
1519+#define WF_UWTBL_TID6_SN_ADDR 24
1520+#define WF_UWTBL_TID6_SN_MASK 0x000fff00 // 19- 8
1521+#define WF_UWTBL_TID6_SN_SHIFT 8
1522+#define WF_UWTBL_TID7_SN_DW 6
1523+#define WF_UWTBL_TID7_SN_ADDR 24
1524+#define WF_UWTBL_TID7_SN_MASK 0xfff00000 // 31-20
1525+#define WF_UWTBL_TID7_SN_SHIFT 20
1526+// DW7
1527+#define WF_UWTBL_KEY_LOC0_DW 7
1528+#define WF_UWTBL_KEY_LOC0_ADDR 28
1529+#define WF_UWTBL_KEY_LOC0_MASK 0x00001fff // 12- 0
1530+#define WF_UWTBL_KEY_LOC0_SHIFT 0
1531+#define WF_UWTBL_KEY_LOC1_DW 7
1532+#define WF_UWTBL_KEY_LOC1_ADDR 28
1533+#define WF_UWTBL_KEY_LOC1_MASK 0x1fff0000 // 28-16
1534+#define WF_UWTBL_KEY_LOC1_SHIFT 16
1535+// DW8
1536+#define WF_UWTBL_AMSDU_CFG_DW 8
1537+#define WF_UWTBL_AMSDU_CFG_ADDR 32
1538+#define WF_UWTBL_AMSDU_CFG_MASK 0x00000fff // 11- 0
1539+#define WF_UWTBL_AMSDU_CFG_SHIFT 0
1540+#define WF_UWTBL_SEC_ADDR_MODE_DW 8
1541+#define WF_UWTBL_SEC_ADDR_MODE_ADDR 32
1542+#define WF_UWTBL_SEC_ADDR_MODE_MASK 0x00300000 // 21-20
1543+#define WF_UWTBL_SEC_ADDR_MODE_SHIFT 20
1544+#define WF_UWTBL_WMM_Q_DW 8
1545+#define WF_UWTBL_WMM_Q_ADDR 32
1546+#define WF_UWTBL_WMM_Q_MASK 0x06000000 // 26-25
1547+#define WF_UWTBL_WMM_Q_SHIFT 25
1548+#define WF_UWTBL_QOS_DW 8
1549+#define WF_UWTBL_QOS_ADDR 32
1550+#define WF_UWTBL_QOS_MASK 0x08000000 // 27-27
1551+#define WF_UWTBL_QOS_SHIFT 27
1552+#define WF_UWTBL_HT_DW 8
1553+#define WF_UWTBL_HT_ADDR 32
1554+#define WF_UWTBL_HT_MASK 0x10000000 // 28-28
1555+#define WF_UWTBL_HT_SHIFT 28
1556+#define WF_UWTBL_HDRT_MODE_DW 8
1557+#define WF_UWTBL_HDRT_MODE_ADDR 32
1558+#define WF_UWTBL_HDRT_MODE_MASK 0x20000000 // 29-29
1559+#define WF_UWTBL_HDRT_MODE_SHIFT 29
1560+// DW9
1561+#define WF_UWTBL_RELATED_IDX0_DW 9
1562+#define WF_UWTBL_RELATED_IDX0_ADDR 36
1563+#define WF_UWTBL_RELATED_IDX0_MASK 0x00000fff // 11- 0
1564+#define WF_UWTBL_RELATED_IDX0_SHIFT 0
1565+#define WF_UWTBL_RELATED_BAND0_DW 9
1566+#define WF_UWTBL_RELATED_BAND0_ADDR 36
1567+#define WF_UWTBL_RELATED_BAND0_MASK 0x00003000 // 13-12
1568+#define WF_UWTBL_RELATED_BAND0_SHIFT 12
1569+#define WF_UWTBL_PRIMARY_MLD_BAND_DW 9
1570+#define WF_UWTBL_PRIMARY_MLD_BAND_ADDR 36
1571+#define WF_UWTBL_PRIMARY_MLD_BAND_MASK 0x0000c000 // 15-14
1572+#define WF_UWTBL_PRIMARY_MLD_BAND_SHIFT 14
1573+#define WF_UWTBL_RELATED_IDX1_DW 9
1574+#define WF_UWTBL_RELATED_IDX1_ADDR 36
1575+#define WF_UWTBL_RELATED_IDX1_MASK 0x0fff0000 // 27-16
1576+#define WF_UWTBL_RELATED_IDX1_SHIFT 16
1577+#define WF_UWTBL_RELATED_BAND1_DW 9
1578+#define WF_UWTBL_RELATED_BAND1_ADDR 36
1579+#define WF_UWTBL_RELATED_BAND1_MASK 0x30000000 // 29-28
1580+#define WF_UWTBL_RELATED_BAND1_SHIFT 28
1581+#define WF_UWTBL_SECONDARY_MLD_BAND_DW 9
1582+#define WF_UWTBL_SECONDARY_MLD_BAND_ADDR 36
1583+#define WF_UWTBL_SECONDARY_MLD_BAND_MASK 0xc0000000 // 31-30
1584+#define WF_UWTBL_SECONDARY_MLD_BAND_SHIFT 30
1585+
1586+/* LMAC WTBL */
1587+// DW0
1588+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__DW 0
1589+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__ADDR 0
1590+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__MASK \
1591+ 0x0000ffff // 15- 0
1592+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__SHIFT 0
1593+#define WF_LWTBL_MUAR_DW 0
1594+#define WF_LWTBL_MUAR_ADDR 0
1595+#define WF_LWTBL_MUAR_MASK \
1596+ 0x003f0000 // 21-16
1597+#define WF_LWTBL_MUAR_SHIFT 16
1598+#define WF_LWTBL_RCA1_DW 0
1599+#define WF_LWTBL_RCA1_ADDR 0
1600+#define WF_LWTBL_RCA1_MASK \
1601+ 0x00400000 // 22-22
1602+#define WF_LWTBL_RCA1_SHIFT 22
1603+#define WF_LWTBL_KID_DW 0
1604+#define WF_LWTBL_KID_ADDR 0
1605+#define WF_LWTBL_KID_MASK \
1606+ 0x01800000 // 24-23
1607+#define WF_LWTBL_KID_SHIFT 23
1608+#define WF_LWTBL_RCID_DW 0
1609+#define WF_LWTBL_RCID_ADDR 0
1610+#define WF_LWTBL_RCID_MASK \
1611+ 0x02000000 // 25-25
1612+#define WF_LWTBL_RCID_SHIFT 25
1613+#define WF_LWTBL_BAND_DW 0
1614+#define WF_LWTBL_BAND_ADDR 0
1615+#define WF_LWTBL_BAND_MASK \
1616+ 0x0c000000 // 27-26
1617+#define WF_LWTBL_BAND_SHIFT 26
1618+#define WF_LWTBL_RV_DW 0
1619+#define WF_LWTBL_RV_ADDR 0
1620+#define WF_LWTBL_RV_MASK \
1621+ 0x10000000 // 28-28
1622+#define WF_LWTBL_RV_SHIFT 28
1623+#define WF_LWTBL_RCA2_DW 0
1624+#define WF_LWTBL_RCA2_ADDR 0
1625+#define WF_LWTBL_RCA2_MASK \
1626+ 0x20000000 // 29-29
1627+#define WF_LWTBL_RCA2_SHIFT 29
1628+#define WF_LWTBL_WPI_FLAG_DW 0
1629+#define WF_LWTBL_WPI_FLAG_ADDR 0
1630+#define WF_LWTBL_WPI_FLAG_MASK \
1631+ 0x40000000 // 30-30
1632+#define WF_LWTBL_WPI_FLAG_SHIFT 30
1633+// DW1
1634+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__DW 1
1635+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__ADDR 4
1636+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__MASK \
1637+ 0xffffffff // 31- 0
1638+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__SHIFT 0
1639+// DW2
1640+#define WF_LWTBL_AID_DW 2
1641+#define WF_LWTBL_AID_ADDR 8
1642+#define WF_LWTBL_AID_MASK \
1643+ 0x00000fff // 11- 0
1644+#define WF_LWTBL_AID_SHIFT 0
1645+#define WF_LWTBL_GID_SU_DW 2
1646+#define WF_LWTBL_GID_SU_ADDR 8
1647+#define WF_LWTBL_GID_SU_MASK \
1648+ 0x00001000 // 12-12
1649+#define WF_LWTBL_GID_SU_SHIFT 12
1650+#define WF_LWTBL_SPP_EN_DW 2
1651+#define WF_LWTBL_SPP_EN_ADDR 8
1652+#define WF_LWTBL_SPP_EN_MASK \
1653+ 0x00002000 // 13-13
1654+#define WF_LWTBL_SPP_EN_SHIFT 13
1655+#define WF_LWTBL_WPI_EVEN_DW 2
1656+#define WF_LWTBL_WPI_EVEN_ADDR 8
1657+#define WF_LWTBL_WPI_EVEN_MASK \
1658+ 0x00004000 // 14-14
1659+#define WF_LWTBL_WPI_EVEN_SHIFT 14
1660+#define WF_LWTBL_AAD_OM_DW 2
1661+#define WF_LWTBL_AAD_OM_ADDR 8
1662+#define WF_LWTBL_AAD_OM_MASK \
1663+ 0x00008000 // 15-15
1664+#define WF_LWTBL_AAD_OM_SHIFT 15
1665+/* kite DW2 field bit 13-14 */
1666+#define WF_LWTBL_DUAL_PTEC_EN_DW 2
1667+#define WF_LWTBL_DUAL_PTEC_EN_ADDR 8
1668+#define WF_LWTBL_DUAL_PTEC_EN_MASK \
1669+ 0x00002000 // 13-13
1670+#define WF_LWTBL_DUAL_PTEC_EN_SHIFT 13
1671+#define WF_LWTBL_DUAL_CTS_CAP_DW 2
1672+#define WF_LWTBL_DUAL_CTS_CAP_ADDR 8
1673+#define WF_LWTBL_DUAL_CTS_CAP_MASK \
1674+ 0x00004000 // 14-14
1675+#define WF_LWTBL_DUAL_CTS_CAP_SHIFT 14
1676+#define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2
1677+#define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8
1678+#define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \
1679+ 0x001f0000 // 20-16
1680+#define WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT 16
1681+#define WF_LWTBL_FD_DW 2
1682+#define WF_LWTBL_FD_ADDR 8
1683+#define WF_LWTBL_FD_MASK \
1684+ 0x00200000 // 21-21
1685+#define WF_LWTBL_FD_SHIFT 21
1686+#define WF_LWTBL_TD_DW 2
1687+#define WF_LWTBL_TD_ADDR 8
1688+#define WF_LWTBL_TD_MASK \
1689+ 0x00400000 // 22-22
1690+#define WF_LWTBL_TD_SHIFT 22
1691+#define WF_LWTBL_SW_DW 2
1692+#define WF_LWTBL_SW_ADDR 8
1693+#define WF_LWTBL_SW_MASK \
1694+ 0x00800000 // 23-23
1695+#define WF_LWTBL_SW_SHIFT 23
1696+#define WF_LWTBL_UL_DW 2
1697+#define WF_LWTBL_UL_ADDR 8
1698+#define WF_LWTBL_UL_MASK \
1699+ 0x01000000 // 24-24
1700+#define WF_LWTBL_UL_SHIFT 24
1701+#define WF_LWTBL_TX_PS_DW 2
1702+#define WF_LWTBL_TX_PS_ADDR 8
1703+#define WF_LWTBL_TX_PS_MASK \
1704+ 0x02000000 // 25-25
1705+#define WF_LWTBL_TX_PS_SHIFT 25
1706+#define WF_LWTBL_QOS_DW 2
1707+#define WF_LWTBL_QOS_ADDR 8
1708+#define WF_LWTBL_QOS_MASK \
1709+ 0x04000000 // 26-26
1710+#define WF_LWTBL_QOS_SHIFT 26
1711+#define WF_LWTBL_HT_DW 2
1712+#define WF_LWTBL_HT_ADDR 8
1713+#define WF_LWTBL_HT_MASK \
1714+ 0x08000000 // 27-27
1715+#define WF_LWTBL_HT_SHIFT 27
1716+#define WF_LWTBL_VHT_DW 2
1717+#define WF_LWTBL_VHT_ADDR 8
1718+#define WF_LWTBL_VHT_MASK \
1719+ 0x10000000 // 28-28
1720+#define WF_LWTBL_VHT_SHIFT 28
1721+#define WF_LWTBL_HE_DW 2
1722+#define WF_LWTBL_HE_ADDR 8
1723+#define WF_LWTBL_HE_MASK \
1724+ 0x20000000 // 29-29
1725+#define WF_LWTBL_HE_SHIFT 29
1726+#define WF_LWTBL_EHT_DW 2
1727+#define WF_LWTBL_EHT_ADDR 8
1728+#define WF_LWTBL_EHT_MASK \
1729+ 0x40000000 // 30-30
1730+#define WF_LWTBL_EHT_SHIFT 30
1731+#define WF_LWTBL_MESH_DW 2
1732+#define WF_LWTBL_MESH_ADDR 8
1733+#define WF_LWTBL_MESH_MASK \
1734+ 0x80000000 // 31-31
1735+#define WF_LWTBL_MESH_SHIFT 31
1736+// DW3
1737+#define WF_LWTBL_WMM_Q_DW 3
1738+#define WF_LWTBL_WMM_Q_ADDR 12
1739+#define WF_LWTBL_WMM_Q_MASK \
1740+ 0x00000003 // 1- 0
1741+#define WF_LWTBL_WMM_Q_SHIFT 0
1742+#define WF_LWTBL_EHT_SIG_MCS_DW 3
1743+#define WF_LWTBL_EHT_SIG_MCS_ADDR 12
1744+#define WF_LWTBL_EHT_SIG_MCS_MASK \
1745+ 0x0000000c // 3- 2
1746+#define WF_LWTBL_EHT_SIG_MCS_SHIFT 2
1747+#define WF_LWTBL_HDRT_MODE_DW 3
1748+#define WF_LWTBL_HDRT_MODE_ADDR 12
1749+#define WF_LWTBL_HDRT_MODE_MASK \
1750+ 0x00000010 // 4- 4
1751+#define WF_LWTBL_HDRT_MODE_SHIFT 4
1752+#define WF_LWTBL_BEAM_CHG_DW 3
1753+#define WF_LWTBL_BEAM_CHG_ADDR 12
1754+#define WF_LWTBL_BEAM_CHG_MASK \
1755+ 0x00000020 // 5- 5
1756+#define WF_LWTBL_BEAM_CHG_SHIFT 5
1757+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_DW 3
1758+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_ADDR 12
1759+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK \
1760+ 0x000000c0 // 7- 6
1761+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT 6
1762+#define WF_LWTBL_PFMU_IDX_DW 3
1763+#define WF_LWTBL_PFMU_IDX_ADDR 12
1764+#define WF_LWTBL_PFMU_IDX_MASK \
1765+ 0x0000ff00 // 15- 8
1766+#define WF_LWTBL_PFMU_IDX_SHIFT 8
1767+#define WF_LWTBL_ULPF_IDX_DW 3
1768+#define WF_LWTBL_ULPF_IDX_ADDR 12
1769+#define WF_LWTBL_ULPF_IDX_MASK \
1770+ 0x00ff0000 // 23-16
1771+#define WF_LWTBL_ULPF_IDX_SHIFT 16
1772+#define WF_LWTBL_RIBF_DW 3
1773+#define WF_LWTBL_RIBF_ADDR 12
1774+#define WF_LWTBL_RIBF_MASK \
1775+ 0x01000000 // 24-24
1776+#define WF_LWTBL_RIBF_SHIFT 24
1777+#define WF_LWTBL_ULPF_DW 3
1778+#define WF_LWTBL_ULPF_ADDR 12
1779+#define WF_LWTBL_ULPF_MASK \
1780+ 0x02000000 // 25-25
1781+#define WF_LWTBL_ULPF_SHIFT 25
1782+#define WF_LWTBL_BYPASS_TXSMM_DW 3
1783+#define WF_LWTBL_BYPASS_TXSMM_ADDR 12
1784+#define WF_LWTBL_BYPASS_TXSMM_MASK \
1785+ 0x04000000 // 26-26
1786+#define WF_LWTBL_BYPASS_TXSMM_SHIFT 26
1787+#define WF_LWTBL_TBF_HT_DW 3
1788+#define WF_LWTBL_TBF_HT_ADDR 12
1789+#define WF_LWTBL_TBF_HT_MASK \
1790+ 0x08000000 // 27-27
1791+#define WF_LWTBL_TBF_HT_SHIFT 27
1792+#define WF_LWTBL_TBF_VHT_DW 3
1793+#define WF_LWTBL_TBF_VHT_ADDR 12
1794+#define WF_LWTBL_TBF_VHT_MASK \
1795+ 0x10000000 // 28-28
1796+#define WF_LWTBL_TBF_VHT_SHIFT 28
1797+#define WF_LWTBL_TBF_HE_DW 3
1798+#define WF_LWTBL_TBF_HE_ADDR 12
1799+#define WF_LWTBL_TBF_HE_MASK \
1800+ 0x20000000 // 29-29
1801+#define WF_LWTBL_TBF_HE_SHIFT 29
1802+#define WF_LWTBL_TBF_EHT_DW 3
1803+#define WF_LWTBL_TBF_EHT_ADDR 12
1804+#define WF_LWTBL_TBF_EHT_MASK \
1805+ 0x40000000 // 30-30
1806+#define WF_LWTBL_TBF_EHT_SHIFT 30
1807+#define WF_LWTBL_IGN_FBK_DW 3
1808+#define WF_LWTBL_IGN_FBK_ADDR 12
1809+#define WF_LWTBL_IGN_FBK_MASK \
1810+ 0x80000000 // 31-31
1811+#define WF_LWTBL_IGN_FBK_SHIFT 31
1812+// DW4
1813+#define WF_LWTBL_NEGOTIATED_WINSIZE0_DW 4
1814+#define WF_LWTBL_NEGOTIATED_WINSIZE0_ADDR 16
1815+#define WF_LWTBL_NEGOTIATED_WINSIZE0_MASK \
1816+ 0x00000007 // 2- 0
1817+#define WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT 0
1818+#define WF_LWTBL_NEGOTIATED_WINSIZE1_DW 4
1819+#define WF_LWTBL_NEGOTIATED_WINSIZE1_ADDR 16
1820+#define WF_LWTBL_NEGOTIATED_WINSIZE1_MASK \
1821+ 0x00000038 // 5- 3
1822+#define WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT 3
1823+#define WF_LWTBL_NEGOTIATED_WINSIZE2_DW 4
1824+#define WF_LWTBL_NEGOTIATED_WINSIZE2_ADDR 16
1825+#define WF_LWTBL_NEGOTIATED_WINSIZE2_MASK \
1826+ 0x000001c0 // 8- 6
1827+#define WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT 6
1828+#define WF_LWTBL_NEGOTIATED_WINSIZE3_DW 4
1829+#define WF_LWTBL_NEGOTIATED_WINSIZE3_ADDR 16
1830+#define WF_LWTBL_NEGOTIATED_WINSIZE3_MASK \
1831+ 0x00000e00 // 11- 9
1832+#define WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT 9
1833+#define WF_LWTBL_NEGOTIATED_WINSIZE4_DW 4
1834+#define WF_LWTBL_NEGOTIATED_WINSIZE4_ADDR 16
1835+#define WF_LWTBL_NEGOTIATED_WINSIZE4_MASK \
1836+ 0x00007000 // 14-12
1837+#define WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT 12
1838+#define WF_LWTBL_NEGOTIATED_WINSIZE5_DW 4
1839+#define WF_LWTBL_NEGOTIATED_WINSIZE5_ADDR 16
1840+#define WF_LWTBL_NEGOTIATED_WINSIZE5_MASK \
1841+ 0x00038000 // 17-15
1842+#define WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT 15
1843+#define WF_LWTBL_NEGOTIATED_WINSIZE6_DW 4
1844+#define WF_LWTBL_NEGOTIATED_WINSIZE6_ADDR 16
1845+#define WF_LWTBL_NEGOTIATED_WINSIZE6_MASK \
1846+ 0x001c0000 // 20-18
1847+#define WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT 18
1848+#define WF_LWTBL_NEGOTIATED_WINSIZE7_DW 4
1849+#define WF_LWTBL_NEGOTIATED_WINSIZE7_ADDR 16
1850+#define WF_LWTBL_NEGOTIATED_WINSIZE7_MASK \
1851+ 0x00e00000 // 23-21
1852+#define WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT 21
1853+#define WF_LWTBL_PE_DW 4
1854+#define WF_LWTBL_PE_ADDR 16
1855+#define WF_LWTBL_PE_MASK \
1856+ 0x03000000 // 25-24
1857+#define WF_LWTBL_PE_SHIFT 24
1858+#define WF_LWTBL_DIS_RHTR_DW 4
1859+#define WF_LWTBL_DIS_RHTR_ADDR 16
1860+#define WF_LWTBL_DIS_RHTR_MASK \
1861+ 0x04000000 // 26-26
1862+#define WF_LWTBL_DIS_RHTR_SHIFT 26
1863+#define WF_LWTBL_LDPC_HT_DW 4
1864+#define WF_LWTBL_LDPC_HT_ADDR 16
1865+#define WF_LWTBL_LDPC_HT_MASK \
1866+ 0x08000000 // 27-27
1867+#define WF_LWTBL_LDPC_HT_SHIFT 27
1868+#define WF_LWTBL_LDPC_VHT_DW 4
1869+#define WF_LWTBL_LDPC_VHT_ADDR 16
1870+#define WF_LWTBL_LDPC_VHT_MASK \
1871+ 0x10000000 // 28-28
1872+#define WF_LWTBL_LDPC_VHT_SHIFT 28
1873+#define WF_LWTBL_LDPC_HE_DW 4
1874+#define WF_LWTBL_LDPC_HE_ADDR 16
1875+#define WF_LWTBL_LDPC_HE_MASK \
1876+ 0x20000000 // 29-29
1877+#define WF_LWTBL_LDPC_HE_SHIFT 29
1878+#define WF_LWTBL_LDPC_EHT_DW 4
1879+#define WF_LWTBL_LDPC_EHT_ADDR 16
1880+#define WF_LWTBL_LDPC_EHT_MASK \
1881+ 0x40000000 // 30-30
1882+#define WF_LWTBL_LDPC_EHT_SHIFT 30
1883+#define WF_LWTBL_BA_MODE_DW 4
1884+#define WF_LWTBL_BA_MODE_ADDR 16
1885+#define WF_LWTBL_BA_MODE_MASK \
1886+ 0x80000000 // 31-31
1887+#define WF_LWTBL_BA_MODE_SHIFT 31
1888+// DW5
1889+#define WF_LWTBL_AF_DW 5
1890+#define WF_LWTBL_AF_ADDR 20
1891+#define WF_LWTBL_AF_MASK \
1892+ 0x00000007 // 2- 0
1893+#define WF_LWTBL_AF_MASK_7992 \
1894+ 0x0000000f // 3- 0
1895+#define WF_LWTBL_AF_SHIFT 0
1896+#define WF_LWTBL_AF_HE_DW 5
1897+#define WF_LWTBL_AF_HE_ADDR 20
1898+#define WF_LWTBL_AF_HE_MASK \
1899+ 0x00000018 // 4- 3
1900+#define WF_LWTBL_AF_HE_SHIFT 3
1901+#define WF_LWTBL_RTS_DW 5
1902+#define WF_LWTBL_RTS_ADDR 20
1903+#define WF_LWTBL_RTS_MASK \
1904+ 0x00000020 // 5- 5
1905+#define WF_LWTBL_RTS_SHIFT 5
1906+#define WF_LWTBL_SMPS_DW 5
1907+#define WF_LWTBL_SMPS_ADDR 20
1908+#define WF_LWTBL_SMPS_MASK \
1909+ 0x00000040 // 6- 6
1910+#define WF_LWTBL_SMPS_SHIFT 6
1911+#define WF_LWTBL_DYN_BW_DW 5
1912+#define WF_LWTBL_DYN_BW_ADDR 20
1913+#define WF_LWTBL_DYN_BW_MASK \
1914+ 0x00000080 // 7- 7
1915+#define WF_LWTBL_DYN_BW_SHIFT 7
1916+#define WF_LWTBL_MMSS_DW 5
1917+#define WF_LWTBL_MMSS_ADDR 20
1918+#define WF_LWTBL_MMSS_MASK \
1919+ 0x00000700 // 10- 8
1920+#define WF_LWTBL_MMSS_SHIFT 8
1921+#define WF_LWTBL_USR_DW 5
1922+#define WF_LWTBL_USR_ADDR 20
1923+#define WF_LWTBL_USR_MASK \
1924+ 0x00000800 // 11-11
1925+#define WF_LWTBL_USR_SHIFT 11
1926+#define WF_LWTBL_SR_R_DW 5
1927+#define WF_LWTBL_SR_R_ADDR 20
1928+#define WF_LWTBL_SR_R_MASK \
1929+ 0x00007000 // 14-12
1930+#define WF_LWTBL_SR_R_SHIFT 12
1931+#define WF_LWTBL_SR_ABORT_DW 5
1932+#define WF_LWTBL_SR_ABORT_ADDR 20
1933+#define WF_LWTBL_SR_ABORT_MASK \
1934+ 0x00008000 // 15-15
1935+#define WF_LWTBL_SR_ABORT_SHIFT 15
1936+#define WF_LWTBL_TX_POWER_OFFSET_DW 5
1937+#define WF_LWTBL_TX_POWER_OFFSET_ADDR 20
1938+#define WF_LWTBL_TX_POWER_OFFSET_MASK \
1939+ 0x003f0000 // 21-16
1940+#define WF_LWTBL_TX_POWER_OFFSET_SHIFT 16
1941+#define WF_LWTBL_LTF_EHT_DW 5
1942+#define WF_LWTBL_LTF_EHT_ADDR 20
1943+#define WF_LWTBL_LTF_EHT_MASK \
1944+ 0x00c00000 // 23-22
1945+#define WF_LWTBL_LTF_EHT_SHIFT 22
1946+#define WF_LWTBL_GI_EHT_DW 5
1947+#define WF_LWTBL_GI_EHT_ADDR 20
1948+#define WF_LWTBL_GI_EHT_MASK \
1949+ 0x03000000 // 25-24
1950+#define WF_LWTBL_GI_EHT_SHIFT 24
1951+#define WF_LWTBL_DOPPL_DW 5
1952+#define WF_LWTBL_DOPPL_ADDR 20
1953+#define WF_LWTBL_DOPPL_MASK \
1954+ 0x04000000 // 26-26
1955+#define WF_LWTBL_DOPPL_SHIFT 26
1956+#define WF_LWTBL_TXOP_PS_CAP_DW 5
1957+#define WF_LWTBL_TXOP_PS_CAP_ADDR 20
1958+#define WF_LWTBL_TXOP_PS_CAP_MASK \
1959+ 0x08000000 // 27-27
1960+#define WF_LWTBL_TXOP_PS_CAP_SHIFT 27
1961+#define WF_LWTBL_DU_I_PSM_DW 5
1962+#define WF_LWTBL_DU_I_PSM_ADDR 20
1963+#define WF_LWTBL_DU_I_PSM_MASK \
1964+ 0x10000000 // 28-28
1965+#define WF_LWTBL_DU_I_PSM_SHIFT 28
1966+#define WF_LWTBL_I_PSM_DW 5
1967+#define WF_LWTBL_I_PSM_ADDR 20
1968+#define WF_LWTBL_I_PSM_MASK \
1969+ 0x20000000 // 29-29
1970+#define WF_LWTBL_I_PSM_SHIFT 29
1971+#define WF_LWTBL_PSM_DW 5
1972+#define WF_LWTBL_PSM_ADDR 20
1973+#define WF_LWTBL_PSM_MASK \
1974+ 0x40000000 // 30-30
1975+#define WF_LWTBL_PSM_SHIFT 30
1976+#define WF_LWTBL_SKIP_TX_DW 5
1977+#define WF_LWTBL_SKIP_TX_ADDR 20
1978+#define WF_LWTBL_SKIP_TX_MASK \
1979+ 0x80000000 // 31-31
1980+#define WF_LWTBL_SKIP_TX_SHIFT 31
1981+// DW6
1982+#define WF_LWTBL_CBRN_DW 6
1983+#define WF_LWTBL_CBRN_ADDR 24
1984+#define WF_LWTBL_CBRN_MASK \
1985+ 0x00000007 // 2- 0
1986+#define WF_LWTBL_CBRN_SHIFT 0
1987+#define WF_LWTBL_DBNSS_EN_DW 6
1988+#define WF_LWTBL_DBNSS_EN_ADDR 24
1989+#define WF_LWTBL_DBNSS_EN_MASK \
1990+ 0x00000008 // 3- 3
1991+#define WF_LWTBL_DBNSS_EN_SHIFT 3
1992+#define WF_LWTBL_BAF_EN_DW 6
1993+#define WF_LWTBL_BAF_EN_ADDR 24
1994+#define WF_LWTBL_BAF_EN_MASK \
1995+ 0x00000010 // 4- 4
1996+#define WF_LWTBL_BAF_EN_SHIFT 4
1997+#define WF_LWTBL_RDGBA_DW 6
1998+#define WF_LWTBL_RDGBA_ADDR 24
1999+#define WF_LWTBL_RDGBA_MASK \
2000+ 0x00000020 // 5- 5
2001+#define WF_LWTBL_RDGBA_SHIFT 5
2002+#define WF_LWTBL_R_DW 6
2003+#define WF_LWTBL_R_ADDR 24
2004+#define WF_LWTBL_R_MASK \
2005+ 0x00000040 // 6- 6
2006+#define WF_LWTBL_R_SHIFT 6
2007+#define WF_LWTBL_SPE_IDX_DW 6
2008+#define WF_LWTBL_SPE_IDX_ADDR 24
2009+#define WF_LWTBL_SPE_IDX_MASK \
2010+ 0x00000f80 // 11- 7
2011+#define WF_LWTBL_SPE_IDX_SHIFT 7
2012+#define WF_LWTBL_G2_DW 6
2013+#define WF_LWTBL_G2_ADDR 24
2014+#define WF_LWTBL_G2_MASK \
2015+ 0x00001000 // 12-12
2016+#define WF_LWTBL_G2_SHIFT 12
2017+#define WF_LWTBL_G4_DW 6
2018+#define WF_LWTBL_G4_ADDR 24
2019+#define WF_LWTBL_G4_MASK \
2020+ 0x00002000 // 13-13
2021+#define WF_LWTBL_G4_SHIFT 13
2022+#define WF_LWTBL_G8_DW 6
2023+#define WF_LWTBL_G8_ADDR 24
2024+#define WF_LWTBL_G8_MASK \
2025+ 0x00004000 // 14-14
2026+#define WF_LWTBL_G8_SHIFT 14
2027+#define WF_LWTBL_G16_DW 6
2028+#define WF_LWTBL_G16_ADDR 24
2029+#define WF_LWTBL_G16_MASK \
2030+ 0x00008000 // 15-15
2031+#define WF_LWTBL_G16_SHIFT 15
2032+#define WF_LWTBL_G2_LTF_DW 6
2033+#define WF_LWTBL_G2_LTF_ADDR 24
2034+#define WF_LWTBL_G2_LTF_MASK \
2035+ 0x00030000 // 17-16
2036+#define WF_LWTBL_G2_LTF_SHIFT 16
2037+#define WF_LWTBL_G4_LTF_DW 6
2038+#define WF_LWTBL_G4_LTF_ADDR 24
2039+#define WF_LWTBL_G4_LTF_MASK \
2040+ 0x000c0000 // 19-18
2041+#define WF_LWTBL_G4_LTF_SHIFT 18
2042+#define WF_LWTBL_G8_LTF_DW 6
2043+#define WF_LWTBL_G8_LTF_ADDR 24
2044+#define WF_LWTBL_G8_LTF_MASK \
2045+ 0x00300000 // 21-20
2046+#define WF_LWTBL_G8_LTF_SHIFT 20
2047+#define WF_LWTBL_G16_LTF_DW 6
2048+#define WF_LWTBL_G16_LTF_ADDR 24
2049+#define WF_LWTBL_G16_LTF_MASK \
2050+ 0x00c00000 // 23-22
2051+#define WF_LWTBL_G16_LTF_SHIFT 22
2052+#define WF_LWTBL_G2_HE_DW 6
2053+#define WF_LWTBL_G2_HE_ADDR 24
2054+#define WF_LWTBL_G2_HE_MASK \
2055+ 0x03000000 // 25-24
2056+#define WF_LWTBL_G2_HE_SHIFT 24
2057+#define WF_LWTBL_G4_HE_DW 6
2058+#define WF_LWTBL_G4_HE_ADDR 24
2059+#define WF_LWTBL_G4_HE_MASK \
2060+ 0x0c000000 // 27-26
2061+#define WF_LWTBL_G4_HE_SHIFT 26
2062+#define WF_LWTBL_G8_HE_DW 6
2063+#define WF_LWTBL_G8_HE_ADDR 24
2064+#define WF_LWTBL_G8_HE_MASK \
2065+ 0x30000000 // 29-28
2066+#define WF_LWTBL_G8_HE_SHIFT 28
2067+#define WF_LWTBL_G16_HE_DW 6
2068+#define WF_LWTBL_G16_HE_ADDR 24
2069+#define WF_LWTBL_G16_HE_MASK \
2070+ 0xc0000000 // 31-30
2071+#define WF_LWTBL_G16_HE_SHIFT 30
2072+// DW7
2073+#define WF_LWTBL_BA_WIN_SIZE0_DW 7
2074+#define WF_LWTBL_BA_WIN_SIZE0_ADDR 28
2075+#define WF_LWTBL_BA_WIN_SIZE0_MASK \
2076+ 0x0000000f // 3- 0
2077+#define WF_LWTBL_BA_WIN_SIZE0_SHIFT 0
2078+#define WF_LWTBL_BA_WIN_SIZE1_DW 7
2079+#define WF_LWTBL_BA_WIN_SIZE1_ADDR 28
2080+#define WF_LWTBL_BA_WIN_SIZE1_MASK \
2081+ 0x000000f0 // 7- 4
2082+#define WF_LWTBL_BA_WIN_SIZE1_SHIFT 4
2083+#define WF_LWTBL_BA_WIN_SIZE2_DW 7
2084+#define WF_LWTBL_BA_WIN_SIZE2_ADDR 28
2085+#define WF_LWTBL_BA_WIN_SIZE2_MASK \
2086+ 0x00000f00 // 11- 8
2087+#define WF_LWTBL_BA_WIN_SIZE2_SHIFT 8
2088+#define WF_LWTBL_BA_WIN_SIZE3_DW 7
2089+#define WF_LWTBL_BA_WIN_SIZE3_ADDR 28
2090+#define WF_LWTBL_BA_WIN_SIZE3_MASK \
2091+ 0x0000f000 // 15-12
2092+#define WF_LWTBL_BA_WIN_SIZE3_SHIFT 12
2093+#define WF_LWTBL_BA_WIN_SIZE4_DW 7
2094+#define WF_LWTBL_BA_WIN_SIZE4_ADDR 28
2095+#define WF_LWTBL_BA_WIN_SIZE4_MASK \
2096+ 0x000f0000 // 19-16
2097+#define WF_LWTBL_BA_WIN_SIZE4_SHIFT 16
2098+#define WF_LWTBL_BA_WIN_SIZE5_DW 7
2099+#define WF_LWTBL_BA_WIN_SIZE5_ADDR 28
2100+#define WF_LWTBL_BA_WIN_SIZE5_MASK \
2101+ 0x00f00000 // 23-20
2102+#define WF_LWTBL_BA_WIN_SIZE5_SHIFT 20
2103+#define WF_LWTBL_BA_WIN_SIZE6_DW 7
2104+#define WF_LWTBL_BA_WIN_SIZE6_ADDR 28
2105+#define WF_LWTBL_BA_WIN_SIZE6_MASK \
2106+ 0x0f000000 // 27-24
2107+#define WF_LWTBL_BA_WIN_SIZE6_SHIFT 24
2108+#define WF_LWTBL_BA_WIN_SIZE7_DW 7
2109+#define WF_LWTBL_BA_WIN_SIZE7_ADDR 28
2110+#define WF_LWTBL_BA_WIN_SIZE7_MASK \
2111+ 0xf0000000 // 31-28
2112+#define WF_LWTBL_BA_WIN_SIZE7_SHIFT 28
2113+// DW8
2114+#define WF_LWTBL_AC0_RTS_FAIL_CNT_DW 8
2115+#define WF_LWTBL_AC0_RTS_FAIL_CNT_ADDR 32
2116+#define WF_LWTBL_AC0_RTS_FAIL_CNT_MASK \
2117+ 0x0000001f // 4- 0
2118+#define WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT 0
2119+#define WF_LWTBL_AC1_RTS_FAIL_CNT_DW 8
2120+#define WF_LWTBL_AC1_RTS_FAIL_CNT_ADDR 32
2121+#define WF_LWTBL_AC1_RTS_FAIL_CNT_MASK \
2122+ 0x000003e0 // 9- 5
2123+#define WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT 5
2124+#define WF_LWTBL_AC2_RTS_FAIL_CNT_DW 8
2125+#define WF_LWTBL_AC2_RTS_FAIL_CNT_ADDR 32
2126+#define WF_LWTBL_AC2_RTS_FAIL_CNT_MASK \
2127+ 0x00007c00 // 14-10
2128+#define WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT 10
2129+#define WF_LWTBL_AC3_RTS_FAIL_CNT_DW 8
2130+#define WF_LWTBL_AC3_RTS_FAIL_CNT_ADDR 32
2131+#define WF_LWTBL_AC3_RTS_FAIL_CNT_MASK \
2132+ 0x000f8000 // 19-15
2133+#define WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT 15
2134+#define WF_LWTBL_PARTIAL_AID_DW 8
2135+#define WF_LWTBL_PARTIAL_AID_ADDR 32
2136+#define WF_LWTBL_PARTIAL_AID_MASK \
2137+ 0x1ff00000 // 28-20
2138+#define WF_LWTBL_PARTIAL_AID_SHIFT 20
2139+#define WF_LWTBL_CHK_PER_DW 8
2140+#define WF_LWTBL_CHK_PER_ADDR 32
2141+#define WF_LWTBL_CHK_PER_MASK \
2142+ 0x80000000 // 31-31
2143+#define WF_LWTBL_CHK_PER_SHIFT 31
2144+// DW9
2145+#define WF_LWTBL_RX_AVG_MPDU_SIZE_DW 9
2146+#define WF_LWTBL_RX_AVG_MPDU_SIZE_ADDR 36
2147+#define WF_LWTBL_RX_AVG_MPDU_SIZE_MASK \
2148+ 0x00003fff // 13- 0
2149+#define WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT 0
2150+#define WF_LWTBL_PRITX_SW_MODE_DW 9
2151+#define WF_LWTBL_PRITX_SW_MODE_ADDR 36
2152+#define WF_LWTBL_PRITX_SW_MODE_MASK \
2153+ 0x00008000 // 15-15
2154+#define WF_LWTBL_PRITX_SW_MODE_SHIFT 15
2155+#define WF_LWTBL_PRITX_SW_MODE_MASK_7992 \
2156+ 0x00004000 // 14-14
2157+#define WF_LWTBL_PRITX_SW_MODE_SHIFT_7992 14
2158+#define WF_LWTBL_PRITX_ERSU_DW 9
2159+#define WF_LWTBL_PRITX_ERSU_ADDR 36
2160+#define WF_LWTBL_PRITX_ERSU_MASK \
2161+ 0x00010000 // 16-16
2162+#define WF_LWTBL_PRITX_ERSU_SHIFT 16
2163+#define WF_LWTBL_PRITX_ERSU_MASK_7992 \
2164+ 0x00008000 // 15-15
2165+#define WF_LWTBL_PRITX_ERSU_SHIFT_7992 15
2166+#define WF_LWTBL_PRITX_PLR_DW 9
2167+#define WF_LWTBL_PRITX_PLR_ADDR 36
2168+#define WF_LWTBL_PRITX_PLR_MASK \
2169+ 0x00020000 // 17-17
2170+#define WF_LWTBL_PRITX_PLR_SHIFT 17
2171+#define WF_LWTBL_PRITX_PLR_MASK_7992 \
2172+ 0x00030000 // 17-16
2173+#define WF_LWTBL_PRITX_PLR_SHIFT_7992 16
2174+#define WF_LWTBL_PRITX_DCM_DW 9
2175+#define WF_LWTBL_PRITX_DCM_ADDR 36
2176+#define WF_LWTBL_PRITX_DCM_MASK \
2177+ 0x00040000 // 18-18
2178+#define WF_LWTBL_PRITX_DCM_SHIFT 18
2179+#define WF_LWTBL_PRITX_ER106T_DW 9
2180+#define WF_LWTBL_PRITX_ER106T_ADDR 36
2181+#define WF_LWTBL_PRITX_ER106T_MASK \
2182+ 0x00080000 // 19-19
2183+#define WF_LWTBL_PRITX_ER106T_SHIFT 19
2184+#define WF_LWTBL_FCAP_DW 9
2185+#define WF_LWTBL_FCAP_ADDR 36
2186+#define WF_LWTBL_FCAP_MASK \
2187+ 0x00700000 // 22-20
2188+#define WF_LWTBL_FCAP_SHIFT 20
2189+#define WF_LWTBL_MPDU_FAIL_CNT_DW 9
2190+#define WF_LWTBL_MPDU_FAIL_CNT_ADDR 36
2191+#define WF_LWTBL_MPDU_FAIL_CNT_MASK \
2192+ 0x03800000 // 25-23
2193+#define WF_LWTBL_MPDU_FAIL_CNT_SHIFT 23
2194+#define WF_LWTBL_MPDU_OK_CNT_DW 9
2195+#define WF_LWTBL_MPDU_OK_CNT_ADDR 36
2196+#define WF_LWTBL_MPDU_OK_CNT_MASK \
2197+ 0x1c000000 // 28-26
2198+#define WF_LWTBL_MPDU_OK_CNT_SHIFT 26
2199+#define WF_LWTBL_RATE_IDX_DW 9
2200+#define WF_LWTBL_RATE_IDX_ADDR 36
2201+#define WF_LWTBL_RATE_IDX_MASK \
2202+ 0xe0000000 // 31-29
2203+#define WF_LWTBL_RATE_IDX_SHIFT 29
2204+// DW10
2205+#define WF_LWTBL_RATE1_DW 10
2206+#define WF_LWTBL_RATE1_ADDR 40
2207+#define WF_LWTBL_RATE1_MASK \
2208+ 0x00007fff // 14- 0
2209+#define WF_LWTBL_RATE1_SHIFT 0
2210+#define WF_LWTBL_RATE2_DW 10
2211+#define WF_LWTBL_RATE2_ADDR 40
2212+#define WF_LWTBL_RATE2_MASK \
2213+ 0x7fff0000 // 30-16
2214+#define WF_LWTBL_RATE2_SHIFT 16
2215+// DW11
2216+#define WF_LWTBL_RATE3_DW 11
2217+#define WF_LWTBL_RATE3_ADDR 44
2218+#define WF_LWTBL_RATE3_MASK \
2219+ 0x00007fff // 14- 0
2220+#define WF_LWTBL_RATE3_SHIFT 0
2221+#define WF_LWTBL_RATE4_DW 11
2222+#define WF_LWTBL_RATE4_ADDR 44
2223+#define WF_LWTBL_RATE4_MASK \
2224+ 0x7fff0000 // 30-16
2225+#define WF_LWTBL_RATE4_SHIFT 16
2226+// DW12
2227+#define WF_LWTBL_RATE5_DW 12
2228+#define WF_LWTBL_RATE5_ADDR 48
2229+#define WF_LWTBL_RATE5_MASK \
2230+ 0x00007fff // 14- 0
2231+#define WF_LWTBL_RATE5_SHIFT 0
2232+#define WF_LWTBL_RATE6_DW 12
2233+#define WF_LWTBL_RATE6_ADDR 48
2234+#define WF_LWTBL_RATE6_MASK \
2235+ 0x7fff0000 // 30-16
2236+#define WF_LWTBL_RATE6_SHIFT 16
2237+// DW13
2238+#define WF_LWTBL_RATE7_DW 13
2239+#define WF_LWTBL_RATE7_ADDR 52
2240+#define WF_LWTBL_RATE7_MASK \
2241+ 0x00007fff // 14- 0
2242+#define WF_LWTBL_RATE7_SHIFT 0
2243+#define WF_LWTBL_RATE8_DW 13
2244+#define WF_LWTBL_RATE8_ADDR 52
2245+#define WF_LWTBL_RATE8_MASK \
2246+ 0x7fff0000 // 30-16
2247+#define WF_LWTBL_RATE8_SHIFT 16
2248+// DW14
2249+#define WF_LWTBL_RATE1_TX_CNT_DW 14
2250+#define WF_LWTBL_RATE1_TX_CNT_ADDR 56
2251+#define WF_LWTBL_RATE1_TX_CNT_MASK \
2252+ 0x0000ffff // 15- 0
2253+#define WF_LWTBL_RATE1_TX_CNT_SHIFT 0
2254+#define WF_LWTBL_CIPHER_SUIT_IGTK_DW 14
2255+#define WF_LWTBL_CIPHER_SUIT_IGTK_ADDR 56
2256+#define WF_LWTBL_CIPHER_SUIT_IGTK_MASK \
2257+ 0x00003000 // 13-12
2258+#define WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT 12
2259+#define WF_LWTBL_CIPHER_SUIT_BIGTK_DW 14
2260+#define WF_LWTBL_CIPHER_SUIT_BIGTK_ADDR 56
2261+#define WF_LWTBL_CIPHER_SUIT_BIGTK_MASK \
2262+ 0x0000c000 // 15-14
2263+#define WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT 14
2264+#define WF_LWTBL_RATE1_FAIL_CNT_DW 14
2265+#define WF_LWTBL_RATE1_FAIL_CNT_ADDR 56
2266+#define WF_LWTBL_RATE1_FAIL_CNT_MASK \
2267+ 0xffff0000 // 31-16
2268+#define WF_LWTBL_RATE1_FAIL_CNT_SHIFT 16
2269+// DW15
2270+#define WF_LWTBL_RATE2_OK_CNT_DW 15
2271+#define WF_LWTBL_RATE2_OK_CNT_ADDR 60
2272+#define WF_LWTBL_RATE2_OK_CNT_MASK \
2273+ 0x0000ffff // 15- 0
2274+#define WF_LWTBL_RATE2_OK_CNT_SHIFT 0
2275+#define WF_LWTBL_RATE3_OK_CNT_DW 15
2276+#define WF_LWTBL_RATE3_OK_CNT_ADDR 60
2277+#define WF_LWTBL_RATE3_OK_CNT_MASK \
2278+ 0xffff0000 // 31-16
2279+#define WF_LWTBL_RATE3_OK_CNT_SHIFT 16
2280+// DW16
2281+#define WF_LWTBL_CURRENT_BW_TX_CNT_DW 16
2282+#define WF_LWTBL_CURRENT_BW_TX_CNT_ADDR 64
2283+#define WF_LWTBL_CURRENT_BW_TX_CNT_MASK \
2284+ 0x0000ffff // 15- 0
2285+#define WF_LWTBL_CURRENT_BW_TX_CNT_SHIFT 0
2286+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_DW 16
2287+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_ADDR 64
2288+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_MASK \
2289+ 0xffff0000 // 31-16
2290+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_SHIFT 16
2291+// DW17
2292+#define WF_LWTBL_OTHER_BW_TX_CNT_DW 17
2293+#define WF_LWTBL_OTHER_BW_TX_CNT_ADDR 68
2294+#define WF_LWTBL_OTHER_BW_TX_CNT_MASK \
2295+ 0x0000ffff // 15- 0
2296+#define WF_LWTBL_OTHER_BW_TX_CNT_SHIFT 0
2297+#define WF_LWTBL_OTHER_BW_FAIL_CNT_DW 17
2298+#define WF_LWTBL_OTHER_BW_FAIL_CNT_ADDR 68
2299+#define WF_LWTBL_OTHER_BW_FAIL_CNT_MASK \
2300+ 0xffff0000 // 31-16
2301+#define WF_LWTBL_OTHER_BW_FAIL_CNT_SHIFT 16
2302+// DW18
2303+#define WF_LWTBL_RTS_OK_CNT_DW 18
2304+#define WF_LWTBL_RTS_OK_CNT_ADDR 72
2305+#define WF_LWTBL_RTS_OK_CNT_MASK \
2306+ 0x0000ffff // 15- 0
2307+#define WF_LWTBL_RTS_OK_CNT_SHIFT 0
2308+#define WF_LWTBL_RTS_FAIL_CNT_DW 18
2309+#define WF_LWTBL_RTS_FAIL_CNT_ADDR 72
2310+#define WF_LWTBL_RTS_FAIL_CNT_MASK \
2311+ 0xffff0000 // 31-16
2312+#define WF_LWTBL_RTS_FAIL_CNT_SHIFT 16
2313+// DW19
2314+#define WF_LWTBL_DATA_RETRY_CNT_DW 19
2315+#define WF_LWTBL_DATA_RETRY_CNT_ADDR 76
2316+#define WF_LWTBL_DATA_RETRY_CNT_MASK \
2317+ 0x0000ffff // 15- 0
2318+#define WF_LWTBL_DATA_RETRY_CNT_SHIFT 0
2319+#define WF_LWTBL_MGNT_RETRY_CNT_DW 19
2320+#define WF_LWTBL_MGNT_RETRY_CNT_ADDR 76
2321+#define WF_LWTBL_MGNT_RETRY_CNT_MASK \
2322+ 0xffff0000 // 31-16
2323+#define WF_LWTBL_MGNT_RETRY_CNT_SHIFT 16
2324+// DW20
2325+#define WF_LWTBL_AC0_CTT_CDT_CRB_DW 20
2326+#define WF_LWTBL_AC0_CTT_CDT_CRB_ADDR 80
2327+#define WF_LWTBL_AC0_CTT_CDT_CRB_MASK \
2328+ 0xffffffff // 31- 0
2329+#define WF_LWTBL_AC0_CTT_CDT_CRB_SHIFT 0
2330+// DW21
2331+// DO NOT process repeat field(adm[0])
2332+// DW22
2333+#define WF_LWTBL_AC1_CTT_CDT_CRB_DW 22
2334+#define WF_LWTBL_AC1_CTT_CDT_CRB_ADDR 88
2335+#define WF_LWTBL_AC1_CTT_CDT_CRB_MASK \
2336+ 0xffffffff // 31- 0
2337+#define WF_LWTBL_AC1_CTT_CDT_CRB_SHIFT 0
2338+// DW23
2339+// DO NOT process repeat field(adm[1])
2340+// DW24
2341+#define WF_LWTBL_AC2_CTT_CDT_CRB_DW 24
2342+#define WF_LWTBL_AC2_CTT_CDT_CRB_ADDR 96
2343+#define WF_LWTBL_AC2_CTT_CDT_CRB_MASK \
2344+ 0xffffffff // 31- 0
2345+#define WF_LWTBL_AC2_CTT_CDT_CRB_SHIFT 0
2346+// DW25
2347+// DO NOT process repeat field(adm[2])
2348+// DW26
2349+#define WF_LWTBL_AC3_CTT_CDT_CRB_DW 26
2350+#define WF_LWTBL_AC3_CTT_CDT_CRB_ADDR 104
2351+#define WF_LWTBL_AC3_CTT_CDT_CRB_MASK \
2352+ 0xffffffff // 31- 0
2353+#define WF_LWTBL_AC3_CTT_CDT_CRB_SHIFT 0
2354+// DW27
2355+// DO NOT process repeat field(adm[3])
2356+// DW28
2357+#define WF_LWTBL_RELATED_IDX0_DW 28
2358+#define WF_LWTBL_RELATED_IDX0_ADDR 112
2359+#define WF_LWTBL_RELATED_IDX0_MASK \
2360+ 0x00000fff // 11- 0
2361+#define WF_LWTBL_RELATED_IDX0_SHIFT 0
2362+#define WF_LWTBL_RELATED_BAND0_DW 28
2363+#define WF_LWTBL_RELATED_BAND0_ADDR 112
2364+#define WF_LWTBL_RELATED_BAND0_MASK \
2365+ 0x00003000 // 13-12
2366+#define WF_LWTBL_RELATED_BAND0_SHIFT 12
2367+#define WF_LWTBL_PRIMARY_MLD_BAND_DW 28
2368+#define WF_LWTBL_PRIMARY_MLD_BAND_ADDR 112
2369+#define WF_LWTBL_PRIMARY_MLD_BAND_MASK \
2370+ 0x0000c000 // 15-14
2371+#define WF_LWTBL_PRIMARY_MLD_BAND_SHIFT 14
2372+#define WF_LWTBL_RELATED_IDX1_DW 28
2373+#define WF_LWTBL_RELATED_IDX1_ADDR 112
2374+#define WF_LWTBL_RELATED_IDX1_MASK \
2375+ 0x0fff0000 // 27-16
2376+#define WF_LWTBL_RELATED_IDX1_SHIFT 16
2377+#define WF_LWTBL_RELATED_BAND1_DW 28
2378+#define WF_LWTBL_RELATED_BAND1_ADDR 112
2379+#define WF_LWTBL_RELATED_BAND1_MASK \
2380+ 0x30000000 // 29-28
2381+#define WF_LWTBL_RELATED_BAND1_SHIFT 28
2382+#define WF_LWTBL_SECONDARY_MLD_BAND_DW 28
2383+#define WF_LWTBL_SECONDARY_MLD_BAND_ADDR 112
2384+#define WF_LWTBL_SECONDARY_MLD_BAND_MASK \
2385+ 0xc0000000 // 31-30
2386+#define WF_LWTBL_SECONDARY_MLD_BAND_SHIFT 30
2387+// DW29
2388+#define WF_LWTBL_DISPATCH_POLICY0_DW 29
2389+#define WF_LWTBL_DISPATCH_POLICY0_ADDR 116
2390+#define WF_LWTBL_DISPATCH_POLICY0_MASK \
2391+ 0x00000003 // 1- 0
2392+#define WF_LWTBL_DISPATCH_POLICY0_SHIFT 0
2393+#define WF_LWTBL_DISPATCH_POLICY1_DW 29
2394+#define WF_LWTBL_DISPATCH_POLICY1_ADDR 116
2395+#define WF_LWTBL_DISPATCH_POLICY1_MASK \
2396+ 0x0000000c // 3- 2
2397+#define WF_LWTBL_DISPATCH_POLICY1_SHIFT 2
2398+#define WF_LWTBL_DISPATCH_POLICY2_DW 29
2399+#define WF_LWTBL_DISPATCH_POLICY2_ADDR 116
2400+#define WF_LWTBL_DISPATCH_POLICY2_MASK \
2401+ 0x00000030 // 5- 4
2402+#define WF_LWTBL_DISPATCH_POLICY2_SHIFT 4
2403+#define WF_LWTBL_DISPATCH_POLICY3_DW 29
2404+#define WF_LWTBL_DISPATCH_POLICY3_ADDR 116
2405+#define WF_LWTBL_DISPATCH_POLICY3_MASK \
2406+ 0x000000c0 // 7- 6
2407+#define WF_LWTBL_DISPATCH_POLICY3_SHIFT 6
2408+#define WF_LWTBL_DISPATCH_POLICY4_DW 29
2409+#define WF_LWTBL_DISPATCH_POLICY4_ADDR 116
2410+#define WF_LWTBL_DISPATCH_POLICY4_MASK \
2411+ 0x00000300 // 9- 8
2412+#define WF_LWTBL_DISPATCH_POLICY4_SHIFT 8
2413+#define WF_LWTBL_DISPATCH_POLICY5_DW 29
2414+#define WF_LWTBL_DISPATCH_POLICY5_ADDR 116
2415+#define WF_LWTBL_DISPATCH_POLICY5_MASK \
2416+ 0x00000c00 // 11-10
2417+#define WF_LWTBL_DISPATCH_POLICY5_SHIFT 10
2418+#define WF_LWTBL_DISPATCH_POLICY6_DW 29
2419+#define WF_LWTBL_DISPATCH_POLICY6_ADDR 116
2420+#define WF_LWTBL_DISPATCH_POLICY6_MASK \
2421+ 0x00003000 // 13-12
2422+#define WF_LWTBL_DISPATCH_POLICY6_SHIFT 12
2423+#define WF_LWTBL_DISPATCH_POLICY7_DW 29
2424+#define WF_LWTBL_DISPATCH_POLICY7_ADDR 116
2425+#define WF_LWTBL_DISPATCH_POLICY7_MASK \
2426+ 0x0000c000 // 15-14
2427+#define WF_LWTBL_DISPATCH_POLICY7_SHIFT 14
2428+#define WF_LWTBL_OWN_MLD_ID_DW 29
2429+#define WF_LWTBL_OWN_MLD_ID_ADDR 116
2430+#define WF_LWTBL_OWN_MLD_ID_MASK \
2431+ 0x003f0000 // 21-16
2432+#define WF_LWTBL_OWN_MLD_ID_SHIFT 16
2433+#define WF_LWTBL_EMLSR0_DW 29
2434+#define WF_LWTBL_EMLSR0_ADDR 116
2435+#define WF_LWTBL_EMLSR0_MASK \
2436+ 0x00400000 // 22-22
2437+#define WF_LWTBL_EMLSR0_SHIFT 22
2438+#define WF_LWTBL_EMLMR0_DW 29
2439+#define WF_LWTBL_EMLMR0_ADDR 116
2440+#define WF_LWTBL_EMLMR0_MASK \
2441+ 0x00800000 // 23-23
2442+#define WF_LWTBL_EMLMR0_SHIFT 23
2443+#define WF_LWTBL_EMLSR1_DW 29
2444+#define WF_LWTBL_EMLSR1_ADDR 116
2445+#define WF_LWTBL_EMLSR1_MASK \
2446+ 0x01000000 // 24-24
2447+#define WF_LWTBL_EMLSR1_SHIFT 24
2448+#define WF_LWTBL_EMLMR1_DW 29
2449+#define WF_LWTBL_EMLMR1_ADDR 116
2450+#define WF_LWTBL_EMLMR1_MASK \
2451+ 0x02000000 // 25-25
2452+#define WF_LWTBL_EMLMR1_SHIFT 25
2453+#define WF_LWTBL_EMLSR2_DW 29
2454+#define WF_LWTBL_EMLSR2_ADDR 116
2455+#define WF_LWTBL_EMLSR2_MASK \
2456+ 0x04000000 // 26-26
2457+#define WF_LWTBL_EMLSR2_SHIFT 26
2458+#define WF_LWTBL_EMLMR2_DW 29
2459+#define WF_LWTBL_EMLMR2_ADDR 116
2460+#define WF_LWTBL_EMLMR2_MASK \
2461+ 0x08000000 // 27-27
2462+#define WF_LWTBL_EMLMR2_SHIFT 27
2463+#define WF_LWTBL_STR_BITMAP_DW 29
2464+#define WF_LWTBL_STR_BITMAP_ADDR 116
2465+#define WF_LWTBL_STR_BITMAP_MASK \
2466+ 0xe0000000 // 31-29
2467+#define WF_LWTBL_STR_BITMAP_SHIFT 29
2468+// DW30
2469+#define WF_LWTBL_DISPATCH_ORDER_DW 30
2470+#define WF_LWTBL_DISPATCH_ORDER_ADDR 120
2471+#define WF_LWTBL_DISPATCH_ORDER_MASK \
2472+ 0x0000007f // 6- 0
2473+#define WF_LWTBL_DISPATCH_ORDER_SHIFT 0
2474+#define WF_LWTBL_DISPATCH_RATIO_DW 30
2475+#define WF_LWTBL_DISPATCH_RATIO_ADDR 120
2476+#define WF_LWTBL_DISPATCH_RATIO_MASK \
2477+ 0x00003f80 // 13- 7
2478+#define WF_LWTBL_DISPATCH_RATIO_SHIFT 7
2479+#define WF_LWTBL_LINK_MGF_DW 30
2480+#define WF_LWTBL_LINK_MGF_ADDR 120
2481+#define WF_LWTBL_LINK_MGF_MASK \
2482+ 0xffff0000 // 31-16
2483+#define WF_LWTBL_LINK_MGF_SHIFT 16
2484+// DW31
2485+#define WF_LWTBL_BFTX_TB_DW 31
2486+#define WF_LWTBL_BFTX_TB_ADDR 124
2487+#define WF_LWTBL_BFTX_TB_MASK \
2488+ 0x00800000 // 23-23
2489+#define WF_LWTBL_DROP_DW 31
2490+#define WF_LWTBL_DROP_ADDR 124
2491+#define WF_LWTBL_DROP_MASK \
2492+ 0x01000000 // 24-24
2493+#define WF_LWTBL_DROP_SHIFT 24
2494+#define WF_LWTBL_CASCAD_DW 31
2495+#define WF_LWTBL_CASCAD_ADDR 124
2496+#define WF_LWTBL_CASCAD_MASK \
2497+ 0x02000000 // 25-25
2498+#define WF_LWTBL_CASCAD_SHIFT 25
2499+#define WF_LWTBL_ALL_ACK_DW 31
2500+#define WF_LWTBL_ALL_ACK_ADDR 124
2501+#define WF_LWTBL_ALL_ACK_MASK \
2502+ 0x04000000 // 26-26
2503+#define WF_LWTBL_ALL_ACK_SHIFT 26
2504+#define WF_LWTBL_MPDU_SIZE_DW 31
2505+#define WF_LWTBL_MPDU_SIZE_ADDR 124
2506+#define WF_LWTBL_MPDU_SIZE_MASK \
2507+ 0x18000000 // 28-27
2508+#define WF_LWTBL_MPDU_SIZE_SHIFT 27
2509+#define WF_LWTBL_RXD_DUP_MODE_DW 31
2510+#define WF_LWTBL_RXD_DUP_MODE_ADDR 124
2511+#define WF_LWTBL_RXD_DUP_MODE_MASK \
2512+ 0x60000000 // 30-29
2513+#define WF_LWTBL_RXD_DUP_MODE_SHIFT 29
2514+#define WF_LWTBL_ACK_EN_DW 31
2515+#define WF_LWTBL_ACK_EN_ADDR 128
2516+#define WF_LWTBL_ACK_EN_MASK \
2517+ 0x80000000 // 31-31
2518+#define WF_LWTBL_ACK_EN_SHIFT 31
2519+// DW32
2520+#define WF_LWTBL_OM_INFO_DW 32
2521+#define WF_LWTBL_OM_INFO_ADDR 128
2522+#define WF_LWTBL_OM_INFO_MASK \
2523+ 0x00000fff // 11- 0
2524+#define WF_LWTBL_OM_INFO_SHIFT 0
2525+#define WF_LWTBL_OM_INFO_EHT_DW 32
2526+#define WF_LWTBL_OM_INFO_EHT_ADDR 128
2527+#define WF_LWTBL_OM_INFO_EHT_MASK \
2528+ 0x0000f000 // 15-12
2529+#define WF_LWTBL_OM_INFO_EHT_SHIFT 12
2530+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_DW 32
2531+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_ADDR 128
2532+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK \
2533+ 0x00010000 // 16-16
2534+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_SHIFT 16
2535+#define WF_LWTBL_RXD_DUP_WHITE_LIST_DW 32
2536+#define WF_LWTBL_RXD_DUP_WHITE_LIST_ADDR 128
2537+#define WF_LWTBL_RXD_DUP_WHITE_LIST_MASK \
2538+ 0x1ffe0000 // 28-17
2539+#define WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT 17
2540+// DW33
2541+#define WF_LWTBL_USER_RSSI_DW 33
2542+#define WF_LWTBL_USER_RSSI_ADDR 132
2543+#define WF_LWTBL_USER_RSSI_MASK \
2544+ 0x000001ff // 8- 0
2545+#define WF_LWTBL_USER_RSSI_SHIFT 0
2546+#define WF_LWTBL_USER_SNR_DW 33
2547+#define WF_LWTBL_USER_SNR_ADDR 132
2548+#define WF_LWTBL_USER_SNR_MASK \
2549+ 0x00007e00 // 14- 9
2550+#define WF_LWTBL_USER_SNR_SHIFT 9
2551+#define WF_LWTBL_RAPID_REACTION_RATE_DW 33
2552+#define WF_LWTBL_RAPID_REACTION_RATE_ADDR 132
2553+#define WF_LWTBL_RAPID_REACTION_RATE_MASK \
2554+ 0x0fff0000 // 27-16
2555+#define WF_LWTBL_RAPID_REACTION_RATE_SHIFT 16
2556+#define WF_LWTBL_HT_AMSDU_DW 33
2557+#define WF_LWTBL_HT_AMSDU_ADDR 132
2558+#define WF_LWTBL_HT_AMSDU_MASK \
2559+ 0x40000000 // 30-30
2560+#define WF_LWTBL_HT_AMSDU_SHIFT 30
2561+#define WF_LWTBL_AMSDU_CROSS_LG_DW 33
2562+#define WF_LWTBL_AMSDU_CROSS_LG_ADDR 132
2563+#define WF_LWTBL_AMSDU_CROSS_LG_MASK \
2564+ 0x80000000 // 31-31
2565+#define WF_LWTBL_AMSDU_CROSS_LG_SHIFT 31
2566+// DW34
2567+#define WF_LWTBL_RESP_RCPI0_DW 34
2568+#define WF_LWTBL_RESP_RCPI0_ADDR 136
2569+#define WF_LWTBL_RESP_RCPI0_MASK \
2570+ 0x000000ff // 7- 0
2571+#define WF_LWTBL_RESP_RCPI0_SHIFT 0
2572+#define WF_LWTBL_RESP_RCPI1_DW 34
2573+#define WF_LWTBL_RESP_RCPI1_ADDR 136
2574+#define WF_LWTBL_RESP_RCPI1_MASK \
2575+ 0x0000ff00 // 15- 8
2576+#define WF_LWTBL_RESP_RCPI1_SHIFT 8
2577+#define WF_LWTBL_RESP_RCPI2_DW 34
2578+#define WF_LWTBL_RESP_RCPI2_ADDR 136
2579+#define WF_LWTBL_RESP_RCPI2_MASK \
2580+ 0x00ff0000 // 23-16
2581+#define WF_LWTBL_RESP_RCPI2_SHIFT 16
2582+#define WF_LWTBL_RESP_RCPI3_DW 34
2583+#define WF_LWTBL_RESP_RCPI3_ADDR 136
2584+#define WF_LWTBL_RESP_RCPI3_MASK \
2585+ 0xff000000 // 31-24
2586+#define WF_LWTBL_RESP_RCPI3_SHIFT 24
2587+// DW35
2588+#define WF_LWTBL_SNR_RX0_DW 35
2589+#define WF_LWTBL_SNR_RX0_ADDR 140
2590+#define WF_LWTBL_SNR_RX0_MASK \
2591+ 0x0000003f // 5- 0
2592+#define WF_LWTBL_SNR_RX0_SHIFT 0
2593+#define WF_LWTBL_SNR_RX1_DW 35
2594+#define WF_LWTBL_SNR_RX1_ADDR 140
2595+#define WF_LWTBL_SNR_RX1_MASK \
2596+ 0x00000fc0 // 11- 6
2597+#define WF_LWTBL_SNR_RX1_SHIFT 6
2598+#define WF_LWTBL_SNR_RX2_DW 35
2599+#define WF_LWTBL_SNR_RX2_ADDR 140
2600+#define WF_LWTBL_SNR_RX2_MASK \
2601+ 0x0003f000 // 17-12
2602+#define WF_LWTBL_SNR_RX2_SHIFT 12
2603+#define WF_LWTBL_SNR_RX3_DW 35
2604+#define WF_LWTBL_SNR_RX3_ADDR 140
2605+#define WF_LWTBL_SNR_RX3_MASK \
2606+ 0x00fc0000 // 23-18
2607+#define WF_LWTBL_SNR_RX3_SHIFT 18
2608+
2609+/* WTBL Group - Packet Number */
2610+/* DW 2 */
2611+#define WTBL_PN0_MASK BITS(0, 7)
2612+#define WTBL_PN0_OFFSET 0
2613+#define WTBL_PN1_MASK BITS(8, 15)
2614+#define WTBL_PN1_OFFSET 8
2615+#define WTBL_PN2_MASK BITS(16, 23)
2616+#define WTBL_PN2_OFFSET 16
2617+#define WTBL_PN3_MASK BITS(24, 31)
2618+#define WTBL_PN3_OFFSET 24
2619+
2620+/* DW 3 */
2621+#define WTBL_PN4_MASK BITS(0, 7)
2622+#define WTBL_PN4_OFFSET 0
2623+#define WTBL_PN5_MASK BITS(8, 15)
2624+#define WTBL_PN5_OFFSET 8
2625+
2626+/* DW 4 */
2627+#define WTBL_BIPN0_MASK BITS(0, 7)
2628+#define WTBL_BIPN0_OFFSET 0
2629+#define WTBL_BIPN1_MASK BITS(8, 15)
2630+#define WTBL_BIPN1_OFFSET 8
2631+#define WTBL_BIPN2_MASK BITS(16, 23)
2632+#define WTBL_BIPN2_OFFSET 16
2633+#define WTBL_BIPN3_MASK BITS(24, 31)
2634+#define WTBL_BIPN3_OFFSET 24
2635+
2636+/* DW 5 */
2637+#define WTBL_BIPN4_MASK BITS(0, 7)
2638+#define WTBL_BIPN4_OFFSET 0
2639+#define WTBL_BIPN5_MASK BITS(8, 15)
2640+#define WTBL_BIPN5_OFFSET 8
2641+
2642+/* UWTBL DW 6 */
2643+#define WTBL_AMSDU_LEN_MASK BITS(0, 5)
2644+#define WTBL_AMSDU_LEN_OFFSET 0
2645+#define WTBL_AMSDU_NUM_MASK BITS(6, 10)
2646+#define WTBL_AMSDU_NUM_OFFSET 6
2647+#define WTBL_AMSDU_EN_MASK BIT(11)
2648+#define WTBL_AMSDU_EN_OFFSET 11
2649+
2650+/* UWTBL DW 8 */
2651+#define WTBL_SEC_ADDR_MODE_MASK BITS(20, 21)
2652+#define WTBL_SEC_ADDR_MODE_OFFSET 20
2653+
2654+/* LWTBL Rate field */
2655+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
2656+#define WTBL_RATE_TX_RATE_OFFSET 0
2657+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
2658+#define WTBL_RATE_TX_MODE_OFFSET 6
2659+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
2660+#define WTBL_RATE_NSTS_OFFSET 10
2661+#define WTBL_RATE_STBC_MASK BIT(14)
2662+#define WTBL_RATE_STBC_OFFSET 14
2663+
2664+/***** WTBL(LMAC) DW Offset *****/
2665+/* LMAC WTBL Group - Peer Unique Information */
2666+#define WTBL_GROUP_PEER_INFO_DW_0 0
2667+#define WTBL_GROUP_PEER_INFO_DW_1 1
2668+
2669+/* WTBL Group - TxRx Capability/Information */
2670+#define WTBL_GROUP_TRX_CAP_DW_2 2
2671+#define WTBL_GROUP_TRX_CAP_DW_3 3
2672+#define WTBL_GROUP_TRX_CAP_DW_4 4
2673+#define WTBL_GROUP_TRX_CAP_DW_5 5
2674+#define WTBL_GROUP_TRX_CAP_DW_6 6
2675+#define WTBL_GROUP_TRX_CAP_DW_7 7
2676+#define WTBL_GROUP_TRX_CAP_DW_8 8
2677+#define WTBL_GROUP_TRX_CAP_DW_9 9
2678+
2679+/* WTBL Group - Auto Rate Table*/
2680+#define WTBL_GROUP_AUTO_RATE_1_2 10
2681+#define WTBL_GROUP_AUTO_RATE_3_4 11
2682+#define WTBL_GROUP_AUTO_RATE_5_6 12
2683+#define WTBL_GROUP_AUTO_RATE_7_8 13
2684+
2685+/* WTBL Group - Tx Counter */
2686+#define WTBL_GROUP_TX_CNT_LINE_1 14
2687+#define WTBL_GROUP_TX_CNT_LINE_2 15
2688+#define WTBL_GROUP_TX_CNT_LINE_3 16
2689+#define WTBL_GROUP_TX_CNT_LINE_4 17
2690+#define WTBL_GROUP_TX_CNT_LINE_5 18
2691+#define WTBL_GROUP_TX_CNT_LINE_6 19
2692+
2693+/* WTBL Group - Admission Control Counter */
2694+#define WTBL_GROUP_ADM_CNT_LINE_1 20
2695+#define WTBL_GROUP_ADM_CNT_LINE_2 21
2696+#define WTBL_GROUP_ADM_CNT_LINE_3 22
2697+#define WTBL_GROUP_ADM_CNT_LINE_4 23
2698+#define WTBL_GROUP_ADM_CNT_LINE_5 24
2699+#define WTBL_GROUP_ADM_CNT_LINE_6 25
2700+#define WTBL_GROUP_ADM_CNT_LINE_7 26
2701+#define WTBL_GROUP_ADM_CNT_LINE_8 27
2702+
2703+/* WTBL Group -MLO Info */
2704+#define WTBL_GROUP_MLO_INFO_LINE_1 28
2705+#define WTBL_GROUP_MLO_INFO_LINE_2 29
2706+#define WTBL_GROUP_MLO_INFO_LINE_3 30
2707+
2708+/* WTBL Group -RESP Info */
2709+#define WTBL_GROUP_RESP_INFO_DW_31 31
2710+
2711+/* WTBL Group -RX DUP Info */
2712+#define WTBL_GROUP_RX_DUP_INFO_DW_32 32
2713+
2714+/* WTBL Group - Rx Statistics Counter */
2715+#define WTBL_GROUP_RX_STAT_CNT_LINE_1 33
2716+#define WTBL_GROUP_RX_STAT_CNT_LINE_2 34
2717+#define WTBL_GROUP_RX_STAT_CNT_LINE_3 35
2718+
2719+/* UWTBL Group - HW AMSDU */
2720+#define UWTBL_HW_AMSDU_DW WF_UWTBL_AMSDU_CFG_DW
2721+
2722+/* LWTBL DW 4 */
2723+#define WTBL_DIS_RHTR WF_LWTBL_DIS_RHTR_MASK
2724+
2725+/* UWTBL DW 5 */
2726+#define WTBL_KEY_LINK_DW_KEY_LOC0_MASK BITS(0, 10)
2727+#define WTBL_PSM WF_LWTBL_PSM_MASK
2728+
2729+/* Need to sync with FW define */
2730+#define INVALID_KEY_ENTRY WTBL_KEY_LINK_DW_KEY_LOC0_MASK
2731+
2732+// RATE
2733+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
2734+#define WTBL_RATE_TX_RATE_OFFSET 0
2735+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
2736+#define WTBL_RATE_TX_MODE_OFFSET 6
2737+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
2738+#define WTBL_RATE_NSTS_OFFSET 10
2739+#define WTBL_RATE_STBC_MASK BIT(14)
2740+#define WTBL_RATE_STBC_OFFSET 14
2741+#endif
2742+
2743+#endif
2744diff --git a/mt7996/mtk_debugfs.c b/mt7996/mtk_debugfs.c
2745new file mode 100644
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]2746index 0000000..d79e00c
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]2747--- /dev/null
2748+++ b/mt7996/mtk_debugfs.c
2749@@ -0,0 +1,2507 @@
2750+// SPDX-License-Identifier: ISC
2751+/*
2752+ * Copyright (C) 2023 MediaTek Inc.
2753+ */
2754+#include "mt7996.h"
2755+#include "../mt76.h"
2756+#include "mcu.h"
2757+#include "mac.h"
2758+#include "eeprom.h"
2759+#include "mtk_debug.h"
2760+#include "mtk_mcu.h"
2761+#include "coredump.h"
2762+
2763+#ifdef CONFIG_MTK_DEBUG
2764+
2765+/* AGG INFO */
2766+static int
2767+mt7996_agginfo_read_per_band(struct seq_file *s, int band_idx)
2768+{
2769+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2770+ u64 total_burst, total_ampdu, ampdu_cnt[16];
2771+ u32 value, idx, row_idx, col_idx, start_range, agg_rang_sel[16], burst_cnt[16], band_offset = 0;
2772+ u8 partial_str[16] = {}, full_str[64] = {};
2773+
2774+ switch (band_idx) {
2775+ case 0:
2776+ band_offset = 0;
2777+ break;
2778+ case 1:
2779+ band_offset = BN1_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
2780+ break;
2781+ case 2:
2782+ band_offset = IP1_BN0_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
2783+ break;
2784+ default:
2785+ return 0;
2786+ }
2787+
2788+ seq_printf(s, "Band %d AGG Status\n", band_idx);
2789+ seq_printf(s, "===============================\n");
2790+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR0_ADDR + band_offset);
2791+ seq_printf(s, "AC00 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT);
2792+ seq_printf(s, "AC01 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT);
2793+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR1_ADDR + band_offset);
2794+ seq_printf(s, "AC02 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT);
2795+ seq_printf(s, "AC03 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT);
2796+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR2_ADDR + band_offset);
2797+ seq_printf(s, "AC10 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT);
2798+ seq_printf(s, "AC11 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT);
2799+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR3_ADDR + band_offset);
2800+ seq_printf(s, "AC12 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT);
2801+ seq_printf(s, "AC13 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT);
2802+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR4_ADDR + band_offset);
2803+ seq_printf(s, "AC20 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT);
2804+ seq_printf(s, "AC21 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT);
2805+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR5_ADDR + band_offset);
2806+ seq_printf(s, "AC22 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT);
2807+ seq_printf(s, "AC23 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT);
2808+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR6_ADDR + band_offset);
2809+ seq_printf(s, "AC30 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT);
2810+ seq_printf(s, "AC31 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT);
2811+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR7_ADDR + band_offset);
2812+ seq_printf(s, "AC32 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT);
2813+ seq_printf(s, "AC33 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT);
2814+
2815+ switch (band_idx) {
2816+ case 0:
2817+ band_offset = 0;
2818+ break;
2819+ case 1:
2820+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
2821+ break;
2822+ case 2:
2823+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
2824+ break;
2825+ default:
2826+ return 0;
2827+ }
2828+
2829+ seq_printf(s, "===AMPDU Related Counters===\n");
2830+
2831+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC0_ADDR + band_offset);
2832+ agg_rang_sel[0] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT;
2833+ agg_rang_sel[1] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT;
2834+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC1_ADDR + band_offset);
2835+ agg_rang_sel[2] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT;
2836+ agg_rang_sel[3] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT;
2837+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC2_ADDR + band_offset);
2838+ agg_rang_sel[4] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT;
2839+ agg_rang_sel[5] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT;
2840+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC3_ADDR + band_offset);
2841+ agg_rang_sel[6] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT;
2842+ agg_rang_sel[7] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT;
2843+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC4_ADDR + band_offset);
2844+ agg_rang_sel[8] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT;
2845+ agg_rang_sel[9] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT;
2846+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC5_ADDR + band_offset);
2847+ agg_rang_sel[10] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT;
2848+ agg_rang_sel[11] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT;
2849+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC6_ADDR + band_offset);
2850+ agg_rang_sel[12] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT;
2851+ agg_rang_sel[13] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT;
2852+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC7_ADDR + band_offset);
2853+ agg_rang_sel[14] = (value & BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK) >> BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT;
2854+
2855+ burst_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR0_ADDR + band_offset);
2856+ burst_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR1_ADDR + band_offset);
2857+ burst_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR2_ADDR + band_offset);
2858+ burst_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR3_ADDR + band_offset);
2859+ burst_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR4_ADDR + band_offset);
2860+ burst_cnt[5] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR5_ADDR + band_offset);
2861+ burst_cnt[6] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR6_ADDR + band_offset);
2862+ burst_cnt[7] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR7_ADDR + band_offset);
2863+ burst_cnt[8] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR8_ADDR + band_offset);
2864+ burst_cnt[9] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR9_ADDR + band_offset);
2865+ burst_cnt[10] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR10_ADDR + band_offset);
2866+ burst_cnt[11] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR11_ADDR + band_offset);
2867+ burst_cnt[12] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR12_ADDR + band_offset);
2868+ burst_cnt[13] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR13_ADDR + band_offset);
2869+ burst_cnt[14] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR14_ADDR + band_offset);
2870+ burst_cnt[15] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR15_ADDR + band_offset);
2871+
2872+ start_range = 1;
2873+ total_burst = 0;
2874+ total_ampdu = 0;
2875+ agg_rang_sel[15] = 1023;
2876+
2877+ /* Need to add 1 after read from AGG_RANG_SEL CR */
2878+ for (idx = 0; idx < 16; idx++) {
2879+ agg_rang_sel[idx]++;
2880+ total_burst += burst_cnt[idx];
2881+
2882+ if (start_range == agg_rang_sel[idx])
2883+ ampdu_cnt[idx] = (u64) start_range * burst_cnt[idx];
2884+ else
2885+ ampdu_cnt[idx] = (u64) ((start_range + agg_rang_sel[idx]) >> 1) * burst_cnt[idx];
2886+
2887+ start_range = agg_rang_sel[idx] + 1;
2888+ total_ampdu += ampdu_cnt[idx];
2889+ }
2890+
2891+ start_range = 1;
2892+ sprintf(full_str, "%13s ", "Tx Agg Range:");
2893+
2894+ for (row_idx = 0; row_idx < 4; row_idx++) {
2895+ for (col_idx = 0; col_idx < 4; col_idx++, idx++) {
2896+ idx = 4 * row_idx + col_idx;
2897+
2898+ if (start_range == agg_rang_sel[idx])
2899+ sprintf(partial_str, "%d", agg_rang_sel[idx]);
2900+ else
2901+ sprintf(partial_str, "%d~%d", start_range, agg_rang_sel[idx]);
2902+
2903+ start_range = agg_rang_sel[idx] + 1;
2904+ sprintf(full_str + strlen(full_str), "%-11s ", partial_str);
2905+ }
2906+
2907+ idx = 4 * row_idx;
2908+
2909+ seq_printf(s, "%s\n", full_str);
2910+ seq_printf(s, "%13s 0x%-9x 0x%-9x 0x%-9x 0x%-9x\n",
2911+ row_idx ? "" : "Burst count:",
2912+ burst_cnt[idx], burst_cnt[idx + 1],
2913+ burst_cnt[idx + 2], burst_cnt[idx + 3]);
2914+
2915+ if (total_burst != 0) {
2916+ if (row_idx == 0)
2917+ sprintf(full_str, "%13s ",
2918+ "Burst ratio:");
2919+ else
2920+ sprintf(full_str, "%13s ", "");
2921+
2922+ for (col_idx = 0; col_idx < 4; col_idx++) {
2923+ u64 count = (u64) burst_cnt[idx + col_idx] * 100;
2924+
2925+ sprintf(partial_str, "(%llu%%)",
2926+ div64_u64(count, total_burst));
2927+ sprintf(full_str + strlen(full_str),
2928+ "%-11s ", partial_str);
2929+ }
2930+
2931+ seq_printf(s, "%s\n", full_str);
2932+
2933+ if (row_idx == 0)
2934+ sprintf(full_str, "%13s ",
2935+ "MDPU ratio:");
2936+ else
2937+ sprintf(full_str, "%13s ", "");
2938+
2939+ for (col_idx = 0; col_idx < 4; col_idx++) {
2940+ u64 count = ampdu_cnt[idx + col_idx] * 100;
2941+
2942+ sprintf(partial_str, "(%llu%%)",
2943+ div64_u64(count, total_ampdu));
2944+ sprintf(full_str + strlen(full_str),
2945+ "%-11s ", partial_str);
2946+ }
2947+
2948+ seq_printf(s, "%s\n", full_str);
2949+ }
2950+
2951+ sprintf(full_str, "%13s ", "");
2952+ }
2953+
2954+ return 0;
2955+}
2956+
2957+static int mt7996_agginfo_read_band0(struct seq_file *s, void *data)
2958+{
2959+ mt7996_agginfo_read_per_band(s, MT_BAND0);
2960+ return 0;
2961+}
2962+
2963+static int mt7996_agginfo_read_band1(struct seq_file *s, void *data)
2964+{
2965+ mt7996_agginfo_read_per_band(s, MT_BAND1);
2966+ return 0;
2967+}
2968+
2969+static int mt7996_agginfo_read_band2(struct seq_file *s, void *data)
2970+{
2971+ mt7996_agginfo_read_per_band(s, MT_BAND2);
2972+ return 0;
2973+}
2974+
2975+/* AMSDU INFO */
2976+static int mt7996_amsdu_result_read(struct seq_file *s, void *data)
2977+{
2978+#define HW_MSDU_CNT_ADDR 0xf400
2979+#define HW_MSDU_NUM_MAX 33
2980+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2981+ u32 ple_stat[HW_MSDU_NUM_MAX] = {0}, total_amsdu = 0;
2982+ u8 i;
2983+
2984+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
2985+ ple_stat[i] = mt76_rr(dev, HW_MSDU_CNT_ADDR + i * 0x04);
2986+
2987+ seq_printf(s, "TXD counter status of MSDU:\n");
2988+
2989+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
2990+ total_amsdu += ple_stat[i];
2991+
2992+ for (i = 0; i < HW_MSDU_NUM_MAX; i++) {
2993+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i, ple_stat[i]);
2994+ if (total_amsdu != 0)
2995+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
2996+ else
2997+ seq_printf(s, "\n");
2998+ }
2999+
3000+ return 0;
3001+}
3002+
3003+/* DBG MODLE */
3004+static int
3005+mt7996_fw_debug_module_set(void *data, u64 module)
3006+{
3007+ struct mt7996_dev *dev = data;
3008+
3009+ dev->dbg.fw_dbg_module = module;
3010+ return 0;
3011+}
3012+
3013+static int
3014+mt7996_fw_debug_module_get(void *data, u64 *module)
3015+{
3016+ struct mt7996_dev *dev = data;
3017+
3018+ *module = dev->dbg.fw_dbg_module;
3019+ return 0;
3020+}
3021+
3022+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7996_fw_debug_module_get,
3023+ mt7996_fw_debug_module_set, "%lld\n");
3024+
3025+static int
3026+mt7996_fw_debug_level_set(void *data, u64 level)
3027+{
3028+ struct mt7996_dev *dev = data;
3029+
3030+ dev->dbg.fw_dbg_lv = level;
3031+ mt7996_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
3032+ return 0;
3033+}
3034+
3035+static int
3036+mt7996_fw_debug_level_get(void *data, u64 *level)
3037+{
3038+ struct mt7996_dev *dev = data;
3039+
3040+ *level = dev->dbg.fw_dbg_lv;
3041+ return 0;
3042+}
3043+
3044+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7996_fw_debug_level_get,
3045+ mt7996_fw_debug_level_set, "%lld\n");
3046+
3047+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
3048+static int
3049+mt7996_wa_set(void *data, u64 val)
3050+{
3051+ struct mt7996_dev *dev = data;
3052+ u32 arg1, arg2, arg3;
3053+
3054+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
3055+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
3056+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
3057+
3058+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
3059+ arg1, arg2, arg3);
3060+}
3061+
3062+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7996_wa_set,
3063+ "0x%llx\n");
3064+
3065+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
3066+static int
3067+mt7996_wa_query(void *data, u64 val)
3068+{
3069+ struct mt7996_dev *dev = data;
3070+ u32 arg1, arg2, arg3;
3071+
3072+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
3073+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
3074+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
3075+
3076+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
3077+ arg1, arg2, arg3);
3078+ return 0;
3079+}
3080+
3081+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7996_wa_query,
3082+ "0x%llx\n");
3083+
3084+static int mt7996_dump_version(struct seq_file *s, void *data)
3085+{
3086+#define MAX_ADIE_NUM 3
3087+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3088+ u32 regval;
3089+ u16 adie_chip_id, adie_chip_ver;
3090+ int adie_idx;
3091+ static const char * const fem_type[] = {
3092+ [MT7996_FEM_UNSET] = "N/A",
3093+ [MT7996_FEM_EXT] = "eFEM",
3094+ [MT7996_FEM_INT] = "iFEM",
3095+ [MT7996_FEM_MIX] = "mixed FEM",
3096+ };
3097+
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]3098+ seq_printf(s, "Version: 4.3.24.5\n");
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]3099+
3100+ if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
3101+ return 0;
3102+
3103+ seq_printf(s, "Rom Patch Build Time: %.16s\n", dev->patch_build_date);
3104+ seq_printf(s, "WM Patch Build Time: %.15s, Mode: %s\n",
3105+ dev->ram_build_date[MT7996_RAM_TYPE_WM],
3106+ dev->testmode_enable ? "Testmode" : "Normal mode");
3107+ seq_printf(s, "WA Patch Build Time: %.15s\n",
3108+ dev->ram_build_date[MT7996_RAM_TYPE_WA]);
3109+ seq_printf(s, "DSP Patch Build Time: %.15s\n",
3110+ dev->ram_build_date[MT7996_RAM_TYPE_DSP]);
3111+ for (adie_idx = 0; adie_idx < MAX_ADIE_NUM; adie_idx++) {
3112+ mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), &regval, false);
3113+ adie_chip_id = FIELD_GET(MT_ADIE_CHIP_ID_MASK, regval);
3114+ adie_chip_ver = FIELD_GET(MT_ADIE_VERSION_MASK, regval);
3115+ if (adie_chip_id)
3116+ seq_printf(s, "Adie %d: ID = 0x%04x, Ver = 0x%04x\n",
3117+ adie_idx, adie_chip_id, adie_chip_ver);
3118+ else
3119+ seq_printf(s, "Adie %d: ID = N/A, Ver = N/A\n", adie_idx);
3120+ }
3121+ seq_printf(s, "FEM type: %s\n", fem_type[dev->fem_type]);
3122+
3123+ return 0;
3124+}
3125+
3126+/* fw wm call trace info dump */
3127+void mt7996_show_lp_history(struct seq_file *s, u32 type)
3128+{
3129+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3130+ struct mt7996_crash_data *crash_data;
3131+ struct mt7996_coredump *dump;
3132+ u64 now = 0;
3133+ int i = 0;
3134+ u8 fw_type = !!type;
3135+
3136+ mutex_lock(&dev->dump_mutex);
3137+
3138+ crash_data = mt7996_coredump_new(dev, fw_type);
3139+ if (!crash_data) {
3140+ mutex_unlock(&dev->dump_mutex);
3141+ seq_printf(s, "the coredump is disable!\n");
3142+ return;
3143+ }
3144+ mutex_unlock(&dev->dump_mutex);
3145+
3146+ dump = mt7996_coredump_build(dev, fw_type, false);
3147+ if (!dump) {
3148+ seq_printf(s, "no call stack data found!\n");
3149+ return;
3150+ }
3151+
3152+ seq_printf(s, "\x1b[32m%s log output\x1b[0m\n", dump->fw_type);
3153+ seq_printf(s, "\x1b[32mfw status: %s\n", dump->fw_state);
3154+ mt7996_dump_version(s, NULL);
3155+ /* PC log */
3156+ now = jiffies;
3157+ for (i = 0; i < 10; i++)
3158+ seq_printf(s, "\tCurrent PC=%x\n", dump->pc_cur[i]);
3159+
3160+ seq_printf(s, "PC log contorl=0x%x(T=%llu)(latest PC index = 0x%x)\n",
3161+ dump->pc_dbg_ctrl, now, dump->pc_cur_idx);
3162+ for (i = 0; i < 32; i++)
3163+ seq_printf(s, "\tPC log(%d)=0x%08x\n", i, dump->pc_stack[i]);
3164+
3165+ /* LR log */
3166+ now = jiffies;
3167+ seq_printf(s, "\nLR log contorl=0x%x(T=%llu)(latest LR index = 0x%x)\n",
3168+ dump->lr_dbg_ctrl, now, dump->lr_cur_idx);
3169+ for (i = 0; i < 32; i++)
3170+ seq_printf(s, "\tLR log(%d)=0x%08x\n", i, dump->lr_stack[i]);
3171+
3172+ vfree(dump);
3173+}
3174+
3175+static int mt7996_fw_wa_info_read(struct seq_file *s, void *data)
3176+{
3177+ seq_printf(s, "======[ShowPcLpHistory]======\n");
3178+ mt7996_show_lp_history(s, MT7996_RAM_TYPE_WA);
3179+ seq_printf(s, "======[End ShowPcLpHistory]==\n");
3180+
3181+ return 0;
3182+}
3183+
3184+static int mt7996_fw_wm_info_read(struct seq_file *s, void *data)
3185+{
3186+ seq_printf(s, "======[ShowPcLpHistory]======\n");
3187+ mt7996_show_lp_history(s, MT7996_RAM_TYPE_WM);
3188+ seq_printf(s, "======[End ShowPcLpHistory]==\n");
3189+
3190+ return 0;
3191+}
3192+
3193+/* dma info dump */
3194+static void
3195+dump_dma_tx_ring_info(struct seq_file *s, struct mt7996_dev *dev, char *str1, char *str2, u32 ring_base)
3196+{
3197+ u32 base, cnt, cidx, didx, queue_cnt;
3198+
3199+ base= mt76_rr(dev, ring_base);
3200+ cnt = mt76_rr(dev, ring_base + 4);
3201+ cidx = mt76_rr(dev, ring_base + 8);
3202+ didx = mt76_rr(dev, ring_base + 12);
3203+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
3204+
3205+ seq_printf(s, "%20s %6s %10x %15x %10x %10x %10x\n", str1, str2, base, cnt, cidx, didx, queue_cnt);
3206+}
3207+
3208+static void
3209+dump_dma_rx_ring_info(struct seq_file *s, struct mt7996_dev *dev, char *str1, char *str2, u32 ring_base)
3210+{
3211+ u32 base, ctrl1, cnt, cidx, didx, queue_cnt;
3212+
3213+ base= mt76_rr(dev, ring_base);
3214+ ctrl1 = mt76_rr(dev, ring_base + 4);
3215+ cidx = mt76_rr(dev, ring_base + 8) & 0xfff;
3216+ didx = mt76_rr(dev, ring_base + 12) & 0xfff;
3217+ cnt = ctrl1 & 0xfff;
3218+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
3219+
3220+ seq_printf(s, "%20s %6s %10x %10x(%3x) %10x %10x %10x\n",
3221+ str1, str2, base, ctrl1, cnt, cidx, didx, queue_cnt);
3222+}
3223+
3224+static void
3225+mt7996_show_dma_info(struct seq_file *s, struct mt7996_dev *dev)
3226+{
3227+ u32 sys_ctrl[10];
3228+
3229+ /* HOST DMA0 information */
3230+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR);
3231+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR);
3232+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR);
3233+
3234+ seq_printf(s, "HOST_DMA Configuration\n");
3235+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
3236+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
3237+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
3238+ "DMA0", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2],
3239+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
3240+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
3241+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
3242+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
3243+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
3244+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
3245+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
3246+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
3247+
3248+ if (dev->hif2) {
3249+ /* HOST DMA1 information */
3250+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR);
3251+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR);
3252+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR);
3253+
3254+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
3255+ "DMA0P1", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2],
3256+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
3257+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
3258+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
3259+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
3260+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
3261+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
3262+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
3263+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
3264+ }
3265+
3266+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
3267+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
3268+ "Name", "Used", "Base", "Ctrl1(Cnt)", "CIDX", "DIDX", "QCnt");
3269+ dump_dma_tx_ring_info(s, dev, "T0:TXD0(H2MAC)", "STA",
3270+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
3271+ dump_dma_tx_ring_info(s, dev, "T1:TXD1(H2MAC)", "STA",
3272+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
3273+ dump_dma_tx_ring_info(s, dev, "T2:TXD2(H2MAC)", "STA",
3274+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
3275+ dump_dma_tx_ring_info(s, dev, "T3:", "STA",
3276+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
3277+ dump_dma_tx_ring_info(s, dev, "T4:", "STA",
3278+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
3279+ dump_dma_tx_ring_info(s, dev, "T5:", "STA",
3280+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
3281+ dump_dma_tx_ring_info(s, dev, "T6:", "STA",
3282+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
3283+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", "Both",
3284+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR);
3285+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", "Both",
3286+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR);
3287+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", "AP",
3288+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR);
3289+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", "AP",
3290+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR);
3291+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", "AP",
3292+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR);
3293+ dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP",
3294+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR);
3295+ dump_dma_tx_ring_info(s, dev, "T22:TXD3(H2WA)", "AP",
3296+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR);
3297+
3298+
3299+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", "Both",
3300+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
3301+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", "AP",
3302+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
3303+ dump_dma_rx_ring_info(s, dev, "R2:TxDone0(WA2H)", "AP",
3304+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
3305+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP",
3306+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
3307+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", "Both",
3308+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
3309+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both",
3310+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
3311+ dump_dma_rx_ring_info(s, dev, "R6:BUF1(MAC2H)", "Both",
3312+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
3313+ dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "Both",
3314+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
3315+ dump_dma_rx_ring_info(s, dev, "R8:BUF0(MAC2H)", "Both",
3316+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
3317+ dump_dma_rx_ring_info(s, dev, "R9:TxDone0(MAC2H)", "Both",
3318+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
3319+ dump_dma_rx_ring_info(s, dev, "R10:MSDU_PG0(MAC2H)", "Both",
3320+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR);
3321+ dump_dma_rx_ring_info(s, dev, "R11:MSDU_PG1(MAC2H)", "Both",
3322+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR);
3323+ dump_dma_rx_ring_info(s, dev, "R12:MSDU_PG2(MAC2H)", "Both",
3324+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR);
3325+ dump_dma_rx_ring_info(s, dev, "IND:IND_CMD(MAC2H)", "Both",
3326+ WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR);
3327+
3328+ if (dev->hif2) {
3329+ seq_printf(s, "HOST_DMA0 PCIe1 Ring Configuration\n");
3330+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
3331+ "Name", "Used", "Base", "Ctrl1(Cnt)", "CIDX", "DIDX", "QCnt");
3332+ dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP",
3333+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR);
3334+ dump_dma_tx_ring_info(s, dev, "T22:TXD?(H2WA)", "AP",
3335+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR);
3336+
3337+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP",
3338+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
3339+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both",
3340+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR);
3341+ dump_dma_rx_ring_info(s, dev, "R6:BUF1(MAC2H)", "Both",
3342+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR);
3343+ dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "Both",
3344+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR);
3345+ }
3346+
3347+ /* MCU DMA information */
3348+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
3349+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
3350+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
3351+
3352+ seq_printf(s, "MCU_DMA Configuration\n");
3353+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
3354+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
3355+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
3356+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
3357+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
3358+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
3359+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
3360+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
3361+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
3362+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
3363+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
3364+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
3365+
3366+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
3367+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
3368+ "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
3369+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", "Both",
3370+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
3371+ dump_dma_tx_ring_info(s, dev, "T1:Event(WA2H)", "AP",
3372+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
3373+ dump_dma_tx_ring_info(s, dev, "T2:TxDone0(WA2H)", "AP",
3374+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
3375+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1(WA2H)", "AP",
3376+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
3377+ dump_dma_tx_ring_info(s, dev, "T4:TXD(WM2MAC)", "Both",
3378+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
3379+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD(WM2MAC)", "Both",
3380+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
3381+ dump_dma_tx_ring_info(s, dev, "T6:TXD(WA2MAC)", "AP",
3382+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
3383+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", "Both",
3384+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
3385+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", "Both",
3386+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
3387+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", "AP",
3388+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
3389+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", "AP",
3390+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
3391+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", "AP",
3392+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
3393+ dump_dma_rx_ring_info(s, dev, "R5:Data0(MAC2WM)", "Both",
3394+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
3395+ dump_dma_rx_ring_info(s, dev, "R6:TxDone(MAC2WM)", "Both",
3396+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
3397+ dump_dma_rx_ring_info(s, dev, "R7:SPL/RPT(MAC2WM)", "Both",
3398+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
3399+ dump_dma_rx_ring_info(s, dev, "R8:TxDone(MAC2WA)", "AP",
3400+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
3401+ dump_dma_rx_ring_info(s, dev, "R9:Data1(MAC2WM)", "Both",
3402+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
3403+ dump_dma_rx_ring_info(s, dev, "R10:TXD2(H2WA)", "AP",
3404+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR);
3405+
3406+ /* MEM DMA information */
3407+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
3408+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
3409+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
3410+
3411+ seq_printf(s, "MEM_DMA Configuration\n");
3412+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
3413+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
3414+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
3415+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
3416+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
3417+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
3418+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
3419+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
3420+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
3421+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
3422+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
3423+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
3424+
3425+ seq_printf(s, "MEM_DMA Ring Configuration\n");
3426+ seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n",
3427+ "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
3428+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", "AP",
3429+ WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
3430+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", "AP",
3431+ WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
3432+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", "AP",
3433+ WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
3434+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", "AP",
3435+ WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
3436+}
3437+
3438+static int mt7996_trinfo_read(struct seq_file *s, void *data)
3439+{
3440+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3441+ mt7996_show_dma_info(s, dev);
3442+ return 0;
3443+}
3444+
3445+/* MIB INFO */
3446+static int mt7996_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3447+{
3448+#define BSS_NUM 4
3449+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3450+ u8 bss_nums = BSS_NUM;
3451+ u32 idx;
3452+ u32 mac_val, band_offset = 0, band_offset_umib = 0;
3453+ u32 msdr6, msdr9, msdr18;
3454+ u32 rvsr0, rscr26, rscr35, mctr5, mctr6, msr0, msr1, msr2;
3455+ u32 tbcr0, tbcr1, tbcr2, tbcr3, tbcr4;
3456+ u32 btscr[7];
3457+ u32 tdrcr[5];
3458+ u32 mbtocr[16], mbtbcr[16], mbrocr[16], mbrbcr[16];
3459+ u32 btcr, btbcr, brocr, brbcr, btdcr, brdcr;
3460+ u32 mu_cnt[5];
3461+ u32 ampdu_cnt[3];
3462+ u64 per;
3463+
3464+ switch (band_idx) {
3465+ case 0:
3466+ band_offset = 0;
3467+ band_offset_umib = 0;
3468+ break;
3469+ case 1:
3470+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
3471+ band_offset_umib = WF_UMIB_TOP_B1BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR;
3472+ break;
3473+ case 2:
3474+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
3475+ band_offset_umib = WF_UMIB_TOP_B2BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR;
3476+ break;
3477+ default:
3478+ return true;
3479+ }
3480+
3481+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3482+ seq_printf(s, "===============================\n");
3483+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_M0SCR0_ADDR + band_offset);
3484+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3485+
3486+ msdr6 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR6_ADDR + band_offset);
3487+ rvsr0 = mt76_rr(dev, BN0_WF_MIB_TOP_RVSR0_ADDR + band_offset);
3488+ rscr35 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR35_ADDR + band_offset);
3489+ msdr9 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR9_ADDR + band_offset);
3490+ rscr26 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR26_ADDR + band_offset);
3491+ mctr5 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR5_ADDR + band_offset);
3492+ mctr6 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR6_ADDR + band_offset);
3493+ msdr18 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR18_ADDR + band_offset);
3494+ msr0 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR0_ADDR + band_offset);
3495+ msr1 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR1_ADDR + band_offset);
3496+ msr2 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR2_ADDR + band_offset);
3497+ ampdu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR0_ADDR + band_offset);
3498+ ampdu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR3_ADDR + band_offset);
3499+ ampdu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR4_ADDR + band_offset);
3500+ ampdu_cnt[1] &= BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK;
3501+ ampdu_cnt[2] &= BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK;
3502+
3503+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3504+ seq_printf(s, "\tChannelIdleCnt=0x%x\n",
3505+ msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3506+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n",
3507+ msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3508+ seq_printf(s, "\tRx_MDRDY_CNT=0x%x\n",
3509+ rscr26 & BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK);
3510+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x",
3511+ msr0 & BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK,
3512+ msr1 & BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK);
3513+ seq_printf(s, ", OFDM_GREEN_MDRDY_TIME=0x%x\n",
3514+ msr2 & BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK);
3515+ seq_printf(s, "\tPrim CCA Time=0x%x\n",
3516+ mctr5 & BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK);
3517+ seq_printf(s, "\tSec CCA Time=0x%x\n",
3518+ mctr6 & BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK);
3519+ seq_printf(s, "\tPrim ED Time=0x%x\n",
3520+ msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3521+
3522+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3523+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR18_ADDR + band_offset);
3524+ dev->dbg.bcn_total_cnt[band_idx] +=
3525+ (mac_val & BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK);
3526+ seq_printf(s, "\tBeaconTxCnt=0x%x\n", dev->dbg.bcn_total_cnt[band_idx]);
3527+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3528+
3529+ tbcr0 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR0_ADDR + band_offset);
3530+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n",
3531+ tbcr0 & BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK);
3532+ tbcr1 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR1_ADDR + band_offset);
3533+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n",
3534+ tbcr1 & BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK);
3535+ tbcr2 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR2_ADDR + band_offset);
3536+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n",
3537+ tbcr2 & BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK);
3538+ tbcr3 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR3_ADDR + band_offset);
3539+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n",
3540+ tbcr3 & BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK);
3541+ tbcr4 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR4_ADDR + band_offset);
3542+ seq_printf(s, "\tTx 320MHz Cnt=0x%x\n",
3543+ tbcr4 & BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK);
3544+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3545+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3546+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3547+ per = (ampdu_cnt[2] == 0 ?
3548+ 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3549+ seq_printf(s, "\tAMPDU MPDU PER=%llu.%1llu%%\n", per / 10, per % 10);
3550+
3551+ seq_printf(s, "===MU Related Counters===\n");
3552+ mu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSCR2_ADDR + band_offset);
3553+ mu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR5_ADDR + band_offset);
3554+ mu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR6_ADDR + band_offset);
3555+ mu_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR8_ADDR + band_offset);
3556+ mu_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR7_ADDR + band_offset);
3557+
3558+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n",
3559+ mu_cnt[0] & BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK);
3560+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3561+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3562+ seq_printf(s, "\tMU_TO_MU_FAIL_PPDU_COUNT=0x%x\n", mu_cnt[3]);
3563+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3564+
3565+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3566+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n",
3567+ rvsr0 & BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK);
3568+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n",
3569+ rscr35 & BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK);
3570+
3571+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR1_ADDR + band_offset);
3572+ seq_printf(s, "\tRxFCSErrCnt=0x%x\n",
3573+ (mac_val & BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK));
3574+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR33_ADDR + band_offset);
3575+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n",
3576+ (mac_val & BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK));
3577+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR36_ADDR + band_offset);
3578+ seq_printf(s, "\tRxLenMismatch=0x%x\n",
3579+ (mac_val & BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK));
3580+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR31_ADDR + band_offset);
3581+ seq_printf(s, "\tRxMPDUCnt=0x%x\n",
3582+ (mac_val & BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK));
3583+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR27_ADDR + band_offset);
3584+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3585+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR28_ADDR + band_offset);
3586+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3587+
3588+
3589+ /* Per-BSS T/RX Counters */
3590+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3591+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxOkCnt/DataCnt RxByteCnt\n");
3592+ for (idx = 0; idx < bss_nums; idx++) {
3593+ btcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTCR_ADDR + band_offset + idx * 4);
3594+ btdcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + idx * 4);
3595+ btbcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + idx * 4);
3596+
3597+ brocr = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + idx * 4);
3598+ brdcr = mt76_rr(dev, WF_UMIB_TOP_B0BRDCR_ADDR + band_offset_umib + idx * 4);
3599+ brbcr = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + idx * 4);
3600+
3601+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3602+ idx, btcr, btdcr, btbcr, brocr, brdcr, brbcr);
3603+ }
3604+
3605+ seq_printf(s, "===Per-BSS Related MIB Counters===\n");
3606+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3607+
3608+ /* Per-BSS TX Status */
3609+ for (idx = 0; idx < bss_nums; idx++) {
3610+ btscr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR5_ADDR + band_offset + idx * 4);
3611+ btscr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR6_ADDR + band_offset + idx * 4);
3612+ btscr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR0_ADDR + band_offset + idx * 4);
3613+ btscr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR1_ADDR + band_offset + idx * 4);
3614+ btscr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR2_ADDR + band_offset + idx * 4);
3615+ btscr[5] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR3_ADDR + band_offset + idx * 4);
3616+ btscr[6] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR4_ADDR + band_offset + idx * 4);
3617+
3618+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3619+ idx, (btscr[0] & BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK),
3620+ (btscr[1] & BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK),
3621+ (btscr[2] & BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK),
3622+ (btscr[3] & BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK),
3623+ (btscr[4] & BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK),
3624+ (btscr[5] & BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK),
3625+ (btscr[6] & BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK));
3626+ }
3627+
3628+ /* Dummy delimiter insertion result */
3629+ seq_printf(s, "===Dummy delimiter insertion result===\n");
3630+ tdrcr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR0_ADDR + band_offset);
3631+ tdrcr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR1_ADDR + band_offset);
3632+ tdrcr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR2_ADDR + band_offset);
3633+ tdrcr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR3_ADDR + band_offset);
3634+ tdrcr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR4_ADDR + band_offset);
3635+
3636+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3637+ tdrcr[0],
3638+ tdrcr[1],
3639+ tdrcr[2],
3640+ tdrcr[3],
3641+ tdrcr[4]);
3642+
3643+ /* Per-MBSS T/RX Counters */
3644+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3645+ seq_printf(s, "MBSSIdx TxOkCnt TxByteCnt RxOkCnt RxByteCnt\n");
3646+
3647+ for (idx = 0; idx < 16; idx++) {
3648+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (bss_nums + idx) * 4);
3649+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (bss_nums + idx) * 4);
3650+
3651+ mbrocr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + (bss_nums + idx) * 4);
3652+ mbrbcr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + (bss_nums + idx) * 4);
3653+ }
3654+
3655+ for (idx = 0; idx < 16; idx++) {
3656+ seq_printf(s, "%d\t 0x%x\t 0x%x \t 0x%x \t 0x%x\n",
3657+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3658+ }
3659+
3660+ return 0;
3661+}
3662+
3663+static int mt7996_mibinfo_band0(struct seq_file *s, void *data)
3664+{
3665+ mt7996_mibinfo_read_per_band(s, MT_BAND0);
3666+ return 0;
3667+}
3668+
3669+static int mt7996_mibinfo_band1(struct seq_file *s, void *data)
3670+{
3671+ mt7996_mibinfo_read_per_band(s, MT_BAND1);
3672+ return 0;
3673+}
3674+
3675+static int mt7996_mibinfo_band2(struct seq_file *s, void *data)
3676+{
3677+ mt7996_mibinfo_read_per_band(s, MT_BAND2);
3678+ return 0;
3679+}
3680+
3681+/* WTBL INFO */
3682+static int
3683+mt7996_wtbl_read_raw(struct mt7996_dev *dev, u16 idx,
3684+ enum mt7996_wtbl_type type, u16 start_dw,
3685+ u16 len, void *buf)
3686+{
3687+ u32 *dest_cpy = (u32 *)buf;
3688+ u32 size_dw = len;
3689+ u32 src = 0;
3690+
3691+ if (!buf)
3692+ return 0xFF;
3693+
3694+ if (type == WTBL_TYPE_LMAC) {
3695+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR,
3696+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
3697+ src = LWTBL_IDX2BASE(idx, start_dw);
3698+ } else if (type == WTBL_TYPE_UMAC) {
3699+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3700+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3701+ src = UWTBL_IDX2BASE(idx, start_dw);
3702+ } else if (type == WTBL_TYPE_KEY) {
3703+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3704+ MT_DBG_UWTBL_TOP_WDUCR_TARGET |
3705+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3706+ src = KEYTBL_IDX2BASE(idx, start_dw);
3707+ }
3708+
3709+ while (size_dw--) {
3710+ *dest_cpy++ = mt76_rr(dev, src);
3711+ src += 4;
3712+ };
3713+
3714+ return 0;
3715+}
3716+
3717+#if 0
3718+static int
3719+mt7996_wtbl_write_raw(struct mt7996_dev *dev, u16 idx,
3720+ enum mt7996_wtbl_type type, u16 start_dw,
3721+ u32 val)
3722+{
3723+ u32 addr = 0;
3724+
3725+ if (type == WTBL_TYPE_LMAC) {
3726+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR,
3727+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
3728+ addr = LWTBL_IDX2BASE(idx, start_dw);
3729+ } else if (type == WTBL_TYPE_UMAC) {
3730+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3731+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3732+ addr = UWTBL_IDX2BASE(idx, start_dw);
3733+ } else if (type == WTBL_TYPE_KEY) {
3734+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3735+ MT_DBG_UWTBL_TOP_WDUCR_TARGET |
3736+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3737+ addr = KEYTBL_IDX2BASE(idx, start_dw);
3738+ }
3739+
3740+ mt76_wr(dev, addr, val);
3741+
3742+ return 0;
3743+}
3744+#endif
3745+
3746+static const struct berse_wtbl_parse WTBL_LMAC_DW0[] = {
3747+ {"MUAR_IDX", WF_LWTBL_MUAR_MASK, WF_LWTBL_MUAR_SHIFT,false},
3748+ {"RCA1", WF_LWTBL_RCA1_MASK, NO_SHIFT_DEFINE, false},
3749+ {"KID", WF_LWTBL_KID_MASK, WF_LWTBL_KID_SHIFT, false},
3750+ {"RCID", WF_LWTBL_RCID_MASK, NO_SHIFT_DEFINE, false},
3751+ {"BAND", WF_LWTBL_BAND_MASK, WF_LWTBL_BAND_SHIFT,false},
3752+ {"RV", WF_LWTBL_RV_MASK, NO_SHIFT_DEFINE, false},
3753+ {"RCA2", WF_LWTBL_RCA2_MASK, NO_SHIFT_DEFINE, false},
3754+ {"WPI_FLAG", WF_LWTBL_WPI_FLAG_MASK, NO_SHIFT_DEFINE,true},
3755+ {NULL,}
3756+};
3757+
3758+static void parse_fmac_lwtbl_dw0_1(struct seq_file *s, u8 *lwtbl)
3759+{
3760+ u32 *addr = 0;
3761+ u32 dw_value = 0;
3762+ u16 i = 0;
3763+
3764+ seq_printf(s, "\t\n");
3765+ seq_printf(s, "LinkAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
3766+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
3767+
3768+ /* LMAC WTBL DW 0 */
3769+ seq_printf(s, "\t\n");
3770+ seq_printf(s, "LWTBL DW 0/1\n");
3771+ addr = (u32 *)&(lwtbl[WTBL_GROUP_PEER_INFO_DW_0*4]);
3772+ dw_value = *addr;
3773+
3774+ while (WTBL_LMAC_DW0[i].name) {
3775+
3776+ if (WTBL_LMAC_DW0[i].shift == NO_SHIFT_DEFINE)
3777+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW0[i].name,
3778+ (dw_value & WTBL_LMAC_DW0[i].mask) ? 1 : 0);
3779+ else
3780+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW0[i].name,
3781+ (dw_value & WTBL_LMAC_DW0[i].mask) >> WTBL_LMAC_DW0[i].shift);
3782+ i++;
3783+ }
3784+}
3785+
3786+static const struct berse_wtbl_parse *WTBL_LMAC_DW2;
3787+static const struct berse_wtbl_parse WTBL_LMAC_DW2_7996[] = {
3788+ {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false},
3789+ {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false},
3790+ {"SPP_EN", WF_LWTBL_SPP_EN_MASK, NO_SHIFT_DEFINE, false},
3791+ {"WPI_EVEN", WF_LWTBL_WPI_EVEN_MASK, NO_SHIFT_DEFINE, false},
3792+ {"AAD_OM", WF_LWTBL_AAD_OM_MASK, NO_SHIFT_DEFINE, false},
3793+ {"CIPHER_PGTK",WF_LWTBL_CIPHER_SUIT_PGTK_MASK, WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT, true},
3794+ {"FROM_DS", WF_LWTBL_FD_MASK, NO_SHIFT_DEFINE, false},
3795+ {"TO_DS", WF_LWTBL_TD_MASK, NO_SHIFT_DEFINE, false},
3796+ {"SW", WF_LWTBL_SW_MASK, NO_SHIFT_DEFINE, false},
3797+ {"UL", WF_LWTBL_UL_MASK, NO_SHIFT_DEFINE, false},
3798+ {"TX_POWER_SAVE", WF_LWTBL_TX_PS_MASK, NO_SHIFT_DEFINE, true},
3799+ {"QOS", WF_LWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
3800+ {"HT", WF_LWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
3801+ {"VHT", WF_LWTBL_VHT_MASK, NO_SHIFT_DEFINE, false},
3802+ {"HE", WF_LWTBL_HE_MASK, NO_SHIFT_DEFINE, false},
3803+ {"EHT", WF_LWTBL_EHT_MASK, NO_SHIFT_DEFINE, false},
3804+ {"MESH", WF_LWTBL_MESH_MASK, NO_SHIFT_DEFINE, true},
3805+ {NULL,}
3806+};
3807+
3808+static const struct berse_wtbl_parse WTBL_LMAC_DW2_7992[] = {
3809+ {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false},
3810+ {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false},
3811+ {"DUAL_PTEC_EN", WF_LWTBL_DUAL_PTEC_EN_MASK, NO_SHIFT_DEFINE, false},
3812+ {"DUAL_CTS_CAP", WF_LWTBL_DUAL_CTS_CAP_MASK, NO_SHIFT_DEFINE, false},
3813+ {"CIPHER_PGTK",WF_LWTBL_CIPHER_SUIT_PGTK_MASK, WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT, true},
3814+ {"FROM_DS", WF_LWTBL_FD_MASK, NO_SHIFT_DEFINE, false},
3815+ {"TO_DS", WF_LWTBL_TD_MASK, NO_SHIFT_DEFINE, false},
3816+ {"SW", WF_LWTBL_SW_MASK, NO_SHIFT_DEFINE, false},
3817+ {"UL", WF_LWTBL_UL_MASK, NO_SHIFT_DEFINE, false},
3818+ {"TX_POWER_SAVE", WF_LWTBL_TX_PS_MASK, NO_SHIFT_DEFINE, true},
3819+ {"QOS", WF_LWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
3820+ {"HT", WF_LWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
3821+ {"VHT", WF_LWTBL_VHT_MASK, NO_SHIFT_DEFINE, false},
3822+ {"HE", WF_LWTBL_HE_MASK, NO_SHIFT_DEFINE, false},
3823+ {"EHT", WF_LWTBL_EHT_MASK, NO_SHIFT_DEFINE, false},
3824+ {"MESH", WF_LWTBL_MESH_MASK, NO_SHIFT_DEFINE, true},
3825+ {NULL,}
3826+};
3827+
3828+static void parse_fmac_lwtbl_dw2(struct seq_file *s, u8 *lwtbl)
3829+{
3830+ u32 *addr = 0;
3831+ u32 dw_value = 0;
3832+ u16 i = 0;
3833+
3834+ /* LMAC WTBL DW 2 */
3835+ seq_printf(s, "\t\n");
3836+ seq_printf(s, "LWTBL DW 2\n");
3837+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]);
3838+ dw_value = *addr;
3839+
3840+ while (WTBL_LMAC_DW2[i].name) {
3841+
3842+ if (WTBL_LMAC_DW2[i].shift == NO_SHIFT_DEFINE)
3843+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW2[i].name,
3844+ (dw_value & WTBL_LMAC_DW2[i].mask) ? 1 : 0);
3845+ else
3846+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[i].name,
3847+ (dw_value & WTBL_LMAC_DW2[i].mask) >> WTBL_LMAC_DW2[i].shift);
3848+ i++;
3849+ }
3850+}
3851+
3852+static const struct berse_wtbl_parse WTBL_LMAC_DW3[] = {
3853+ {"WMM_Q", WF_LWTBL_WMM_Q_MASK, WF_LWTBL_WMM_Q_SHIFT, false},
3854+ {"EHT_SIG_MCS", WF_LWTBL_EHT_SIG_MCS_MASK, WF_LWTBL_EHT_SIG_MCS_SHIFT, false},
3855+ {"HDRT_MODE", WF_LWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, false},
3856+ {"BEAM_CHG", WF_LWTBL_BEAM_CHG_MASK, NO_SHIFT_DEFINE, false},
3857+ {"EHT_LTF_SYM_NUM", WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK, WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT, true},
3858+ {"PFMU_IDX", WF_LWTBL_PFMU_IDX_MASK, WF_LWTBL_PFMU_IDX_SHIFT, false},
3859+ {"ULPF_IDX", WF_LWTBL_ULPF_IDX_MASK, WF_LWTBL_ULPF_IDX_SHIFT, false},
3860+ {"RIBF", WF_LWTBL_RIBF_MASK, NO_SHIFT_DEFINE, false},
3861+ {"ULPF", WF_LWTBL_ULPF_MASK, NO_SHIFT_DEFINE, false},
3862+ {"BYPASS_TXSMM", WF_LWTBL_BYPASS_TXSMM_MASK, NO_SHIFT_DEFINE, true},
3863+ {"TBF_HT", WF_LWTBL_TBF_HT_MASK, NO_SHIFT_DEFINE, false},
3864+ {"TBF_VHT", WF_LWTBL_TBF_VHT_MASK, NO_SHIFT_DEFINE, false},
3865+ {"TBF_HE", WF_LWTBL_TBF_HE_MASK, NO_SHIFT_DEFINE, false},
3866+ {"TBF_EHT", WF_LWTBL_TBF_EHT_MASK, NO_SHIFT_DEFINE, false},
3867+ {"IGN_FBK", WF_LWTBL_IGN_FBK_MASK, NO_SHIFT_DEFINE, true},
3868+ {NULL,}
3869+};
3870+
3871+static void parse_fmac_lwtbl_dw3(struct seq_file *s, u8 *lwtbl)
3872+{
3873+ u32 *addr = 0;
3874+ u32 dw_value = 0;
3875+ u16 i = 0;
3876+
3877+ /* LMAC WTBL DW 3 */
3878+ seq_printf(s, "\t\n");
3879+ seq_printf(s, "LWTBL DW 3\n");
3880+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_3*4]);
3881+ dw_value = *addr;
3882+
3883+ while (WTBL_LMAC_DW3[i].name) {
3884+
3885+ if (WTBL_LMAC_DW3[i].shift == NO_SHIFT_DEFINE)
3886+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW3[i].name,
3887+ (dw_value & WTBL_LMAC_DW3[i].mask) ? 1 : 0);
3888+ else
3889+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW3[i].name,
3890+ (dw_value & WTBL_LMAC_DW3[i].mask) >> WTBL_LMAC_DW3[i].shift);
3891+ i++;
3892+ }
3893+}
3894+
3895+static const struct berse_wtbl_parse WTBL_LMAC_DW4[] = {
3896+ {"NEGOTIATED_WINSIZE0", WF_LWTBL_NEGOTIATED_WINSIZE0_MASK, WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT, false},
3897+ {"WINSIZE1", WF_LWTBL_NEGOTIATED_WINSIZE1_MASK, WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT, false},
3898+ {"WINSIZE2", WF_LWTBL_NEGOTIATED_WINSIZE2_MASK, WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT, false},
3899+ {"WINSIZE3", WF_LWTBL_NEGOTIATED_WINSIZE3_MASK, WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT, true},
3900+ {"WINSIZE4", WF_LWTBL_NEGOTIATED_WINSIZE4_MASK, WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT, false},
3901+ {"WINSIZE5", WF_LWTBL_NEGOTIATED_WINSIZE5_MASK, WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT, false},
3902+ {"WINSIZE6", WF_LWTBL_NEGOTIATED_WINSIZE6_MASK, WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT, false},
3903+ {"WINSIZE7", WF_LWTBL_NEGOTIATED_WINSIZE7_MASK, WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT, true},
3904+ {"PE", WF_LWTBL_PE_MASK, WF_LWTBL_PE_SHIFT, false},
3905+ {"DIS_RHTR", WF_LWTBL_DIS_RHTR_MASK, NO_SHIFT_DEFINE, false},
3906+ {"LDPC_HT", WF_LWTBL_LDPC_HT_MASK, NO_SHIFT_DEFINE, false},
3907+ {"LDPC_VHT", WF_LWTBL_LDPC_VHT_MASK, NO_SHIFT_DEFINE, false},
3908+ {"LDPC_HE", WF_LWTBL_LDPC_HE_MASK, NO_SHIFT_DEFINE, false},
3909+ {"LDPC_EHT", WF_LWTBL_LDPC_EHT_MASK, NO_SHIFT_DEFINE, true},
3910+ {"BA_MODE", WF_LWTBL_BA_MODE_MASK, NO_SHIFT_DEFINE, true},
3911+ {NULL,}
3912+};
3913+
3914+static void parse_fmac_lwtbl_dw4(struct seq_file *s, u8 *lwtbl)
3915+{
3916+ u32 *addr = 0;
3917+ u32 dw_value = 0;
3918+ u16 i = 0;
3919+
3920+ /* LMAC WTBL DW 4 */
3921+ seq_printf(s, "\t\n");
3922+ seq_printf(s, "LWTBL DW 4\n");
3923+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_4*4]);
3924+ dw_value = *addr;
3925+
3926+ while (WTBL_LMAC_DW4[i].name) {
3927+ if (WTBL_LMAC_DW4[i].shift == NO_SHIFT_DEFINE)
3928+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW4[i].name,
3929+ (dw_value & WTBL_LMAC_DW4[i].mask) ? 1 : 0);
3930+ else
3931+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW4[i].name,
3932+ (dw_value & WTBL_LMAC_DW4[i].mask) >> WTBL_LMAC_DW4[i].shift);
3933+ i++;
3934+ }
3935+}
3936+
3937+static const struct berse_wtbl_parse *WTBL_LMAC_DW5;
3938+static const struct berse_wtbl_parse WTBL_LMAC_DW5_7996[] = {
3939+ {"AF", WF_LWTBL_AF_MASK, WF_LWTBL_AF_SHIFT, false},
3940+ {"AF_HE", WF_LWTBL_AF_HE_MASK, WF_LWTBL_AF_HE_SHIFT,false},
3941+ {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false},
3942+ {"SMPS", WF_LWTBL_SMPS_MASK, NO_SHIFT_DEFINE, false},
3943+ {"DYN_BW", WF_LWTBL_DYN_BW_MASK, NO_SHIFT_DEFINE, true},
3944+ {"MMSS", WF_LWTBL_MMSS_MASK, WF_LWTBL_MMSS_SHIFT,false},
3945+ {"USR", WF_LWTBL_USR_MASK, NO_SHIFT_DEFINE, false},
3946+ {"SR_RATE", WF_LWTBL_SR_R_MASK, WF_LWTBL_SR_R_SHIFT,false},
3947+ {"SR_ABORT", WF_LWTBL_SR_ABORT_MASK, NO_SHIFT_DEFINE, true},
3948+ {"TX_POWER_OFFSET", WF_LWTBL_TX_POWER_OFFSET_MASK, WF_LWTBL_TX_POWER_OFFSET_SHIFT, false},
3949+ {"LTF_EHT", WF_LWTBL_LTF_EHT_MASK, WF_LWTBL_LTF_EHT_SHIFT, false},
3950+ {"GI_EHT", WF_LWTBL_GI_EHT_MASK, WF_LWTBL_GI_EHT_SHIFT, false},
3951+ {"DOPPL", WF_LWTBL_DOPPL_MASK, NO_SHIFT_DEFINE, false},
3952+ {"TXOP_PS_CAP", WF_LWTBL_TXOP_PS_CAP_MASK, NO_SHIFT_DEFINE, false},
3953+ {"DONOT_UPDATE_I_PSM", WF_LWTBL_DU_I_PSM_MASK, NO_SHIFT_DEFINE, true},
3954+ {"I_PSM", WF_LWTBL_I_PSM_MASK, NO_SHIFT_DEFINE, false},
3955+ {"PSM", WF_LWTBL_PSM_MASK, NO_SHIFT_DEFINE, false},
3956+ {"SKIP_TX", WF_LWTBL_SKIP_TX_MASK, NO_SHIFT_DEFINE, true},
3957+ {NULL,}
3958+};
3959+
3960+static const struct berse_wtbl_parse WTBL_LMAC_DW5_7992[] = {
3961+ {"AF", WF_LWTBL_AF_MASK_7992, WF_LWTBL_AF_SHIFT, false},
3962+ {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false},
3963+ {"SMPS", WF_LWTBL_SMPS_MASK, NO_SHIFT_DEFINE, false},
3964+ {"DYN_BW", WF_LWTBL_DYN_BW_MASK, NO_SHIFT_DEFINE, true},
3965+ {"MMSS", WF_LWTBL_MMSS_MASK, WF_LWTBL_MMSS_SHIFT,false},
3966+ {"USR", WF_LWTBL_USR_MASK, NO_SHIFT_DEFINE, false},
3967+ {"SR_RATE", WF_LWTBL_SR_R_MASK, WF_LWTBL_SR_R_SHIFT,false},
3968+ {"SR_ABORT", WF_LWTBL_SR_ABORT_MASK, NO_SHIFT_DEFINE, true},
3969+ {"TX_POWER_OFFSET", WF_LWTBL_TX_POWER_OFFSET_MASK, WF_LWTBL_TX_POWER_OFFSET_SHIFT, false},
3970+ {"LTF_EHT", WF_LWTBL_LTF_EHT_MASK, WF_LWTBL_LTF_EHT_SHIFT, false},
3971+ {"GI_EHT", WF_LWTBL_GI_EHT_MASK, WF_LWTBL_GI_EHT_SHIFT, false},
3972+ {"DOPPL", WF_LWTBL_DOPPL_MASK, NO_SHIFT_DEFINE, false},
3973+ {"TXOP_PS_CAP", WF_LWTBL_TXOP_PS_CAP_MASK, NO_SHIFT_DEFINE, false},
3974+ {"DONOT_UPDATE_I_PSM", WF_LWTBL_DU_I_PSM_MASK, NO_SHIFT_DEFINE, true},
3975+ {"I_PSM", WF_LWTBL_I_PSM_MASK, NO_SHIFT_DEFINE, false},
3976+ {"PSM", WF_LWTBL_PSM_MASK, NO_SHIFT_DEFINE, false},
3977+ {"SKIP_TX", WF_LWTBL_SKIP_TX_MASK, NO_SHIFT_DEFINE, true},
3978+ {NULL,}
3979+};
3980+
3981+static void parse_fmac_lwtbl_dw5(struct seq_file *s, u8 *lwtbl)
3982+{
3983+ u32 *addr = 0;
3984+ u32 dw_value = 0;
3985+ u16 i = 0;
3986+
3987+ /* LMAC WTBL DW 5 */
3988+ seq_printf(s, "\t\n");
3989+ seq_printf(s, "LWTBL DW 5\n");
3990+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_5*4]);
3991+ dw_value = *addr;
3992+
3993+ while (WTBL_LMAC_DW5[i].name) {
3994+ if (WTBL_LMAC_DW5[i].shift == NO_SHIFT_DEFINE)
3995+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW5[i].name,
3996+ (dw_value & WTBL_LMAC_DW5[i].mask) ? 1 : 0);
3997+ else
3998+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW5[i].name,
3999+ (dw_value & WTBL_LMAC_DW5[i].mask) >> WTBL_LMAC_DW5[i].shift);
4000+ i++;
4001+ }
4002+}
4003+
4004+static const struct berse_wtbl_parse WTBL_LMAC_DW6[] = {
4005+ {"CBRN", WF_LWTBL_CBRN_MASK, WF_LWTBL_CBRN_SHIFT, false},
4006+ {"DBNSS_EN", WF_LWTBL_DBNSS_EN_MASK, NO_SHIFT_DEFINE, false},
4007+ {"BAF_EN", WF_LWTBL_BAF_EN_MASK, NO_SHIFT_DEFINE, false},
4008+ {"RDGBA", WF_LWTBL_RDGBA_MASK, NO_SHIFT_DEFINE, false},
4009+ {"RDG", WF_LWTBL_R_MASK, NO_SHIFT_DEFINE, false},
4010+ {"SPE_IDX", WF_LWTBL_SPE_IDX_MASK, WF_LWTBL_SPE_IDX_SHIFT, true},
4011+ {"G2", WF_LWTBL_G2_MASK, NO_SHIFT_DEFINE, false},
4012+ {"G4", WF_LWTBL_G4_MASK, NO_SHIFT_DEFINE, false},
4013+ {"G8", WF_LWTBL_G8_MASK, NO_SHIFT_DEFINE, false},
4014+ {"G16", WF_LWTBL_G16_MASK, NO_SHIFT_DEFINE, true},
4015+ {"G2_LTF", WF_LWTBL_G2_LTF_MASK, WF_LWTBL_G2_LTF_SHIFT, false},
4016+ {"G4_LTF", WF_LWTBL_G4_LTF_MASK, WF_LWTBL_G4_LTF_SHIFT, false},
4017+ {"G8_LTF", WF_LWTBL_G8_LTF_MASK, WF_LWTBL_G8_LTF_SHIFT, false},
4018+ {"G16_LTF", WF_LWTBL_G16_LTF_MASK, WF_LWTBL_G16_LTF_SHIFT, true},
4019+ {"G2_HE", WF_LWTBL_G2_HE_MASK, WF_LWTBL_G2_HE_SHIFT, false},
4020+ {"G4_HE", WF_LWTBL_G4_HE_MASK, WF_LWTBL_G4_HE_SHIFT, false},
4021+ {"G8_HE", WF_LWTBL_G8_HE_MASK, WF_LWTBL_G8_HE_SHIFT, false},
4022+ {"G16_HE", WF_LWTBL_G16_HE_MASK, WF_LWTBL_G16_HE_SHIFT, true},
4023+ {NULL,}
4024+};
4025+
4026+static void parse_fmac_lwtbl_dw6(struct seq_file *s, u8 *lwtbl)
4027+{
4028+ u32 *addr = 0;
4029+ u32 dw_value = 0;
4030+ u16 i = 0;
4031+
4032+ /* LMAC WTBL DW 6 */
4033+ seq_printf(s, "\t\n");
4034+ seq_printf(s, "LWTBL DW 6\n");
4035+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_6*4]);
4036+ dw_value = *addr;
4037+
4038+ while (WTBL_LMAC_DW6[i].name) {
4039+ if (WTBL_LMAC_DW6[i].shift == NO_SHIFT_DEFINE)
4040+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW6[i].name,
4041+ (dw_value & WTBL_LMAC_DW6[i].mask) ? 1 : 0);
4042+ else
4043+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW6[i].name,
4044+ (dw_value & WTBL_LMAC_DW6[i].mask) >> WTBL_LMAC_DW6[i].shift);
4045+ i++;
4046+ }
4047+}
4048+
4049+static void parse_fmac_lwtbl_dw7(struct seq_file *s, u8 *lwtbl)
4050+{
4051+ u32 *addr = 0;
4052+ u32 dw_value = 0;
4053+ int i = 0;
4054+
4055+ /* LMAC WTBL DW 7 */
4056+ seq_printf(s, "\t\n");
4057+ seq_printf(s, "LWTBL DW 7\n");
4058+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_7*4]);
4059+ dw_value = *addr;
4060+
4061+ for (i = 0; i < 8; i++) {
4062+ seq_printf(s, "\tBA_WIN_SIZE%u:%lu\n", i, ((dw_value & BITS(i*4, i*4+3)) >> i*4));
4063+ }
4064+}
4065+
4066+static const struct berse_wtbl_parse WTBL_LMAC_DW8[] = {
4067+ {"RTS_FAIL_CNT_AC0", WF_LWTBL_AC0_RTS_FAIL_CNT_MASK, WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT, false},
4068+ {"AC1", WF_LWTBL_AC1_RTS_FAIL_CNT_MASK, WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT, false},
4069+ {"AC2", WF_LWTBL_AC2_RTS_FAIL_CNT_MASK, WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT, false},
4070+ {"AC3", WF_LWTBL_AC3_RTS_FAIL_CNT_MASK, WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT, true},
4071+ {"PARTIAL_AID", WF_LWTBL_PARTIAL_AID_MASK, WF_LWTBL_PARTIAL_AID_SHIFT, false},
4072+ {"CHK_PER", WF_LWTBL_CHK_PER_MASK, NO_SHIFT_DEFINE, true},
4073+ {NULL,}
4074+};
4075+
4076+static void parse_fmac_lwtbl_dw8(struct seq_file *s, u8 *lwtbl)
4077+{
4078+ u32 *addr = 0;
4079+ u32 dw_value = 0;
4080+ u16 i = 0;
4081+
4082+ /* LMAC WTBL DW 8 */
4083+ seq_printf(s, "\t\n");
4084+ seq_printf(s, "LWTBL DW 8\n");
4085+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_8*4]);
4086+ dw_value = *addr;
4087+
4088+ while (WTBL_LMAC_DW8[i].name) {
4089+ if (WTBL_LMAC_DW8[i].shift == NO_SHIFT_DEFINE)
4090+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW8[i].name,
4091+ (dw_value & WTBL_LMAC_DW8[i].mask) ? 1 : 0);
4092+ else
4093+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW8[i].name,
4094+ (dw_value & WTBL_LMAC_DW8[i].mask) >> WTBL_LMAC_DW8[i].shift);
4095+ i++;
4096+ }
4097+}
4098+
4099+static const struct berse_wtbl_parse *WTBL_LMAC_DW9;
4100+static const struct berse_wtbl_parse WTBL_LMAC_DW9_7996[] = {
4101+ {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false},
4102+ {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK, NO_SHIFT_DEFINE, false},
4103+ {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK, NO_SHIFT_DEFINE, false},
4104+ {"PRITX_PLR", WF_LWTBL_PRITX_PLR_MASK, NO_SHIFT_DEFINE, true},
4105+ {"PRITX_DCM", WF_LWTBL_PRITX_DCM_MASK, NO_SHIFT_DEFINE, false},
4106+ {"PRITX_ER106T", WF_LWTBL_PRITX_ER106T_MASK, NO_SHIFT_DEFINE, true},
4107+ /* {"FCAP(0:20 1:~40)", WTBL_FCAP_20_TO_160_MHZ, WTBL_FCAP_20_TO_160_MHZ_OFFSET}, */
4108+ {"MPDU_FAIL_CNT", WF_LWTBL_MPDU_FAIL_CNT_MASK, WF_LWTBL_MPDU_FAIL_CNT_SHIFT, false},
4109+ {"MPDU_OK_CNT", WF_LWTBL_MPDU_OK_CNT_MASK, WF_LWTBL_MPDU_OK_CNT_SHIFT, false},
4110+ {"RATE_IDX", WF_LWTBL_RATE_IDX_MASK, WF_LWTBL_RATE_IDX_SHIFT, true},
4111+ {NULL,}
4112+};
4113+
4114+static const struct berse_wtbl_parse WTBL_LMAC_DW9_7992[] = {
4115+ {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false},
4116+ {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK_7992, NO_SHIFT_DEFINE, false},
4117+ {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK_7992, NO_SHIFT_DEFINE, false},
4118+ {"PRITX_PLR", WF_LWTBL_PRITX_PLR_MASK_7992, NO_SHIFT_DEFINE, true},
4119+ {"PRITX_DCM", WF_LWTBL_PRITX_DCM_MASK, NO_SHIFT_DEFINE, false},
4120+ {"PRITX_ER106T", WF_LWTBL_PRITX_ER106T_MASK, NO_SHIFT_DEFINE, true},
4121+ /* {"FCAP(0:20 1:~40)", WTBL_FCAP_20_TO_160_MHZ, WTBL_FCAP_20_TO_160_MHZ_OFFSET}, */
4122+ {"MPDU_FAIL_CNT", WF_LWTBL_MPDU_FAIL_CNT_MASK, WF_LWTBL_MPDU_FAIL_CNT_SHIFT, false},
4123+ {"MPDU_OK_CNT", WF_LWTBL_MPDU_OK_CNT_MASK, WF_LWTBL_MPDU_OK_CNT_SHIFT, false},
4124+ {"RATE_IDX", WF_LWTBL_RATE_IDX_MASK, WF_LWTBL_RATE_IDX_SHIFT, true},
4125+ {NULL,}
4126+};
4127+
4128+char *fcap_name[] = {"20MHz", "20/40MHz", "20/40/80MHz", "20/40/80/160/80+80MHz", "20/40/80/160/80+80/320MHz"};
4129+
4130+static void parse_fmac_lwtbl_dw9(struct seq_file *s, u8 *lwtbl)
4131+{
4132+ u32 *addr = 0;
4133+ u32 dw_value = 0;
4134+ u16 i = 0;
4135+
4136+ /* LMAC WTBL DW 9 */
4137+ seq_printf(s, "\t\n");
4138+ seq_printf(s, "LWTBL DW 9\n");
4139+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_9*4]);
4140+ dw_value = *addr;
4141+
4142+ while (WTBL_LMAC_DW9[i].name) {
4143+ if (WTBL_LMAC_DW9[i].shift == NO_SHIFT_DEFINE)
4144+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW9[i].name,
4145+ (dw_value & WTBL_LMAC_DW9[i].mask) ? 1 : 0);
4146+ else
4147+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW9[i].name,
4148+ (dw_value & WTBL_LMAC_DW9[i].mask) >> WTBL_LMAC_DW9[i].shift);
4149+ i++;
4150+ }
4151+
4152+ /* FCAP parser */
4153+ seq_printf(s, "\t\n");
4154+ seq_printf(s, "FCAP:%s\n", fcap_name[(dw_value & WF_LWTBL_FCAP_MASK) >> WF_LWTBL_FCAP_SHIFT]);
4155+}
4156+
4157+#define HW_TX_RATE_TO_MODE(_x) (((_x) & WTBL_RATE_TX_MODE_MASK) >> WTBL_RATE_TX_MODE_OFFSET)
4158+#define HW_TX_RATE_TO_MCS(_x, _mode) ((_x) & WTBL_RATE_TX_RATE_MASK >> WTBL_RATE_TX_RATE_OFFSET)
4159+#define HW_TX_RATE_TO_NSS(_x) (((_x) & WTBL_RATE_NSTS_MASK) >> WTBL_RATE_NSTS_OFFSET)
4160+#define HW_TX_RATE_TO_STBC(_x) (((_x) & WTBL_RATE_STBC_MASK) >> WTBL_RATE_STBC_OFFSET)
4161+
4162+#define MAX_TX_MODE 16
4163+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
4164+ "N/A", "N/A", "N/A",
4165+ "HE_SU", "HE_EXT_SU", "HE_TRIG", "HE_MU",
4166+ "N/A",
4167+ "EHT_EXT_SU", "EHT_TRIG", "EHT_MU",
4168+ "N/A"};
4169+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong", "N/A", "2Mshort", "5.5Mshort", "11Mshort", "N/A"};
4170+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", "N/A"};
4171+
4172+static char *hw_rate_ofdm_str(uint16_t ofdm_idx)
4173+{
4174+ switch (ofdm_idx) {
4175+ case 11: /* 6M */
4176+ return HW_TX_RATE_OFDM_STR[0];
4177+
4178+ case 15: /* 9M */
4179+ return HW_TX_RATE_OFDM_STR[1];
4180+
4181+ case 10: /* 12M */
4182+ return HW_TX_RATE_OFDM_STR[2];
4183+
4184+ case 14: /* 18M */
4185+ return HW_TX_RATE_OFDM_STR[3];
4186+
4187+ case 9: /* 24M */
4188+ return HW_TX_RATE_OFDM_STR[4];
4189+
4190+ case 13: /* 36M */
4191+ return HW_TX_RATE_OFDM_STR[5];
4192+
4193+ case 8: /* 48M */
4194+ return HW_TX_RATE_OFDM_STR[6];
4195+
4196+ case 12: /* 54M */
4197+ return HW_TX_RATE_OFDM_STR[7];
4198+
4199+ default:
4200+ return HW_TX_RATE_OFDM_STR[8];
4201+ }
4202+}
4203+
4204+static char *hw_rate_str(u8 mode, uint16_t rate_idx)
4205+{
4206+ if (mode == 0)
4207+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
4208+ else if (mode == 1)
4209+ return hw_rate_ofdm_str(rate_idx);
4210+ else
4211+ return "MCS";
4212+}
4213+
4214+static void
4215+parse_rate(struct seq_file *s, uint16_t rate_idx, uint16_t txrate)
4216+{
4217+ uint16_t txmode, mcs, nss, stbc;
4218+
4219+ txmode = HW_TX_RATE_TO_MODE(txrate);
4220+ mcs = HW_TX_RATE_TO_MCS(txrate, txmode);
4221+ nss = HW_TX_RATE_TO_NSS(txrate);
4222+ stbc = HW_TX_RATE_TO_STBC(txrate);
4223+
4224+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
4225+ rate_idx + 1, txrate,
4226+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
4227+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
4228+}
4229+
4230+
4231+static const struct berse_wtbl_parse WTBL_LMAC_DW10[] = {
4232+ {"RATE1", WF_LWTBL_RATE1_MASK, WF_LWTBL_RATE1_SHIFT},
4233+ {"RATE2", WF_LWTBL_RATE2_MASK, WF_LWTBL_RATE2_SHIFT},
4234+ {NULL,}
4235+};
4236+
4237+static void parse_fmac_lwtbl_dw10(struct seq_file *s, u8 *lwtbl)
4238+{
4239+ u32 *addr = 0;
4240+ u32 dw_value = 0;
4241+ u16 i = 0;
4242+
4243+ /* LMAC WTBL DW 10 */
4244+ seq_printf(s, "\t\n");
4245+ seq_printf(s, "LWTBL DW 10\n");
4246+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_1_2*4]);
4247+ dw_value = *addr;
4248+
4249+ while (WTBL_LMAC_DW10[i].name) {
4250+ parse_rate(s, i, (dw_value & WTBL_LMAC_DW10[i].mask) >> WTBL_LMAC_DW10[i].shift);
4251+ i++;
4252+ }
4253+}
4254+
4255+static const struct berse_wtbl_parse WTBL_LMAC_DW11[] = {
4256+ {"RATE3", WF_LWTBL_RATE3_MASK, WF_LWTBL_RATE3_SHIFT},
4257+ {"RATE4", WF_LWTBL_RATE4_MASK, WF_LWTBL_RATE4_SHIFT},
4258+ {NULL,}
4259+};
4260+
4261+static void parse_fmac_lwtbl_dw11(struct seq_file *s, u8 *lwtbl)
4262+{
4263+ u32 *addr = 0;
4264+ u32 dw_value = 0;
4265+ u16 i = 0;
4266+
4267+ /* LMAC WTBL DW 11 */
4268+ seq_printf(s, "\t\n");
4269+ seq_printf(s, "LWTBL DW 11\n");
4270+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_3_4*4]);
4271+ dw_value = *addr;
4272+
4273+ while (WTBL_LMAC_DW11[i].name) {
4274+ parse_rate(s, i+2, (dw_value & WTBL_LMAC_DW11[i].mask) >> WTBL_LMAC_DW11[i].shift);
4275+ i++;
4276+ }
4277+}
4278+
4279+static const struct berse_wtbl_parse WTBL_LMAC_DW12[] = {
4280+ {"RATE5", WF_LWTBL_RATE5_MASK, WF_LWTBL_RATE5_SHIFT},
4281+ {"RATE6", WF_LWTBL_RATE6_MASK, WF_LWTBL_RATE6_SHIFT},
4282+ {NULL,}
4283+};
4284+
4285+static void parse_fmac_lwtbl_dw12(struct seq_file *s, u8 *lwtbl)
4286+{
4287+ u32 *addr = 0;
4288+ u32 dw_value = 0;
4289+ u16 i = 0;
4290+
4291+ /* LMAC WTBL DW 12 */
4292+ seq_printf(s, "\t\n");
4293+ seq_printf(s, "LWTBL DW 12\n");
4294+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_5_6*4]);
4295+ dw_value = *addr;
4296+
4297+ while (WTBL_LMAC_DW12[i].name) {
4298+ parse_rate(s, i+4, (dw_value & WTBL_LMAC_DW12[i].mask) >> WTBL_LMAC_DW12[i].shift);
4299+ i++;
4300+ }
4301+}
4302+
4303+static const struct berse_wtbl_parse WTBL_LMAC_DW13[] = {
4304+ {"RATE7", WF_LWTBL_RATE7_MASK, WF_LWTBL_RATE7_SHIFT},
4305+ {"RATE8", WF_LWTBL_RATE8_MASK, WF_LWTBL_RATE8_SHIFT},
4306+ {NULL,}
4307+};
4308+
4309+static void parse_fmac_lwtbl_dw13(struct seq_file *s, u8 *lwtbl)
4310+{
4311+ u32 *addr = 0;
4312+ u32 dw_value = 0;
4313+ u16 i = 0;
4314+
4315+ /* LMAC WTBL DW 13 */
4316+ seq_printf(s, "\t\n");
4317+ seq_printf(s, "LWTBL DW 13\n");
4318+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_7_8*4]);
4319+ dw_value = *addr;
4320+
4321+ while (WTBL_LMAC_DW13[i].name) {
4322+ parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW13[i].mask) >> WTBL_LMAC_DW13[i].shift);
4323+ i++;
4324+ }
4325+}
4326+
4327+static const struct berse_wtbl_parse WTBL_LMAC_DW14_BMC[] = {
4328+ {"CIPHER_IGTK", WF_LWTBL_CIPHER_SUIT_IGTK_MASK, WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT, false},
4329+ {"CIPHER_BIGTK", WF_LWTBL_CIPHER_SUIT_BIGTK_MASK, WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT, true},
4330+ {NULL,}
4331+};
4332+
4333+static const struct berse_wtbl_parse WTBL_LMAC_DW14[] = {
4334+ {"RATE1_TX_CNT", WF_LWTBL_RATE1_TX_CNT_MASK, WF_LWTBL_RATE1_TX_CNT_SHIFT, false},
4335+ {"RATE1_FAIL_CNT", WF_LWTBL_RATE1_FAIL_CNT_MASK, WF_LWTBL_RATE1_FAIL_CNT_SHIFT, true},
4336+ {NULL,}
4337+};
4338+
4339+static void parse_fmac_lwtbl_dw14(struct seq_file *s, u8 *lwtbl)
4340+{
4341+ u32 *addr, *muar_addr = 0;
4342+ u32 dw_value, muar_dw_value = 0;
4343+ u16 i = 0;
4344+
4345+ /* DUMP DW14 for BMC entry only */
4346+ muar_addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]);
4347+ muar_dw_value = *muar_addr;
4348+ if (((muar_dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT)
4349+ == MUAR_INDEX_OWN_MAC_ADDR_BC_MC) {
4350+ /* LMAC WTBL DW 14 */
4351+ seq_printf(s, "\t\n");
4352+ seq_printf(s, "LWTBL DW 14\n");
4353+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]);
4354+ dw_value = *addr;
4355+
4356+ while (WTBL_LMAC_DW14_BMC[i].name) {
4357+ if (WTBL_LMAC_DW14_BMC[i].shift == NO_SHIFT_DEFINE)
4358+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW14_BMC[i].name,
4359+ (dw_value & WTBL_LMAC_DW14_BMC[i].mask) ? 1 : 0);
4360+ else
4361+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW14_BMC[i].name,
4362+ (dw_value & WTBL_LMAC_DW14_BMC[i].mask) >> WTBL_LMAC_DW14_BMC[i].shift);
4363+ i++;
4364+ }
4365+ } else {
4366+ seq_printf(s, "\t\n");
4367+ seq_printf(s, "LWTBL DW 14\n");
4368+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]);
4369+ dw_value = *addr;
4370+
4371+ while (WTBL_LMAC_DW14[i].name) {
4372+ if (WTBL_LMAC_DW14[i].shift == NO_SHIFT_DEFINE)
4373+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW14[i].name,
4374+ (dw_value & WTBL_LMAC_DW14[i].mask) ? 1 : 0);
4375+ else
4376+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW14[i].name,
4377+ (dw_value & WTBL_LMAC_DW14[i].mask) >> WTBL_LMAC_DW14[i].shift);
4378+ i++;
4379+ }
4380+ }
4381+}
4382+
4383+static const struct berse_wtbl_parse WTBL_LMAC_DW28[] = {
4384+ {"RELATED_IDX0", WF_LWTBL_RELATED_IDX0_MASK, WF_LWTBL_RELATED_IDX0_SHIFT, false},
4385+ {"RELATED_BAND0", WF_LWTBL_RELATED_BAND0_MASK, WF_LWTBL_RELATED_BAND0_SHIFT, false},
4386+ {"PRI_MLD_BAND", WF_LWTBL_PRIMARY_MLD_BAND_MASK, WF_LWTBL_PRIMARY_MLD_BAND_SHIFT, true},
4387+ {"RELATED_IDX1", WF_LWTBL_RELATED_IDX1_MASK, WF_LWTBL_RELATED_IDX1_SHIFT, false},
4388+ {"RELATED_BAND1", WF_LWTBL_RELATED_BAND1_MASK, WF_LWTBL_RELATED_BAND1_SHIFT, false},
4389+ {"SEC_MLD_BAND", WF_LWTBL_SECONDARY_MLD_BAND_MASK, WF_LWTBL_SECONDARY_MLD_BAND_SHIFT, true},
4390+ {NULL,}
4391+};
4392+
4393+static void parse_fmac_lwtbl_dw28(struct seq_file *s, u8 *lwtbl)
4394+{
4395+ u32 *addr = 0;
4396+ u32 dw_value = 0;
4397+ u16 i = 0;
4398+
4399+ /* LMAC WTBL DW 28 */
4400+ seq_printf(s, "\t\n");
4401+ seq_printf(s, "LWTBL DW 28\n");
4402+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_1*4]);
4403+ dw_value = *addr;
4404+
4405+ while (WTBL_LMAC_DW28[i].name) {
4406+ if (WTBL_LMAC_DW28[i].shift == NO_SHIFT_DEFINE)
4407+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW28[i].name,
4408+ (dw_value & WTBL_LMAC_DW28[i].mask) ? 1 : 0);
4409+ else
4410+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW28[i].name,
4411+ (dw_value & WTBL_LMAC_DW28[i].mask) >>
4412+ WTBL_LMAC_DW28[i].shift);
4413+ i++;
4414+ }
4415+}
4416+
4417+static const struct berse_wtbl_parse WTBL_LMAC_DW29[] = {
4418+ {"DISPATCH_POLICY_MLD_TID0", WF_LWTBL_DISPATCH_POLICY0_MASK, WF_LWTBL_DISPATCH_POLICY0_SHIFT, false},
4419+ {"MLD_TID1", WF_LWTBL_DISPATCH_POLICY1_MASK, WF_LWTBL_DISPATCH_POLICY1_SHIFT, false},
4420+ {"MLD_TID2", WF_LWTBL_DISPATCH_POLICY2_MASK, WF_LWTBL_DISPATCH_POLICY2_SHIFT, false},
4421+ {"MLD_TID3", WF_LWTBL_DISPATCH_POLICY3_MASK, WF_LWTBL_DISPATCH_POLICY3_SHIFT, true},
4422+ {"MLD_TID4", WF_LWTBL_DISPATCH_POLICY4_MASK, WF_LWTBL_DISPATCH_POLICY4_SHIFT, false},
4423+ {"MLD_TID5", WF_LWTBL_DISPATCH_POLICY5_MASK, WF_LWTBL_DISPATCH_POLICY5_SHIFT, false},
4424+ {"MLD_TID6", WF_LWTBL_DISPATCH_POLICY6_MASK, WF_LWTBL_DISPATCH_POLICY6_SHIFT, false},
4425+ {"MLD_TID7", WF_LWTBL_DISPATCH_POLICY7_MASK, WF_LWTBL_DISPATCH_POLICY7_SHIFT, true},
4426+ {"OMLD_ID", WF_LWTBL_OWN_MLD_ID_MASK, WF_LWTBL_OWN_MLD_ID_SHIFT, false},
4427+ {"EMLSR0", WF_LWTBL_EMLSR0_MASK, NO_SHIFT_DEFINE, false},
4428+ {"EMLMR0", WF_LWTBL_EMLMR0_MASK, NO_SHIFT_DEFINE, false},
4429+ {"EMLSR1", WF_LWTBL_EMLSR1_MASK, NO_SHIFT_DEFINE, false},
4430+ {"EMLMR1", WF_LWTBL_EMLMR1_MASK, NO_SHIFT_DEFINE, true},
4431+ {"EMLSR2", WF_LWTBL_EMLSR2_MASK, NO_SHIFT_DEFINE, false},
4432+ {"EMLMR2", WF_LWTBL_EMLMR2_MASK, NO_SHIFT_DEFINE, false},
4433+ {"STR_BITMAP", WF_LWTBL_STR_BITMAP_MASK, WF_LWTBL_STR_BITMAP_SHIFT, true},
4434+ {NULL,}
4435+};
4436+
4437+static void parse_fmac_lwtbl_dw29(struct seq_file *s, u8 *lwtbl)
4438+{
4439+ u32 *addr = 0;
4440+ u32 dw_value = 0;
4441+ u16 i = 0;
4442+
4443+ /* LMAC WTBL DW 29 */
4444+ seq_printf(s, "\t\n");
4445+ seq_printf(s, "LWTBL DW 29\n");
4446+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_2*4]);
4447+ dw_value = *addr;
4448+
4449+ while (WTBL_LMAC_DW29[i].name) {
4450+ if (WTBL_LMAC_DW29[i].shift == NO_SHIFT_DEFINE)
4451+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW29[i].name,
4452+ (dw_value & WTBL_LMAC_DW29[i].mask) ? 1 : 0);
4453+ else
4454+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW29[i].name,
4455+ (dw_value & WTBL_LMAC_DW29[i].mask) >>
4456+ WTBL_LMAC_DW29[i].shift);
4457+ i++;
4458+ }
4459+}
4460+
4461+static const struct berse_wtbl_parse WTBL_LMAC_DW30[] = {
4462+ {"DISPATCH_ORDER", WF_LWTBL_DISPATCH_ORDER_MASK, WF_LWTBL_DISPATCH_ORDER_SHIFT, false},
4463+ {"DISPATCH_RATIO", WF_LWTBL_DISPATCH_RATIO_MASK, WF_LWTBL_DISPATCH_RATIO_SHIFT, false},
4464+ {"LINK_MGF", WF_LWTBL_LINK_MGF_MASK, WF_LWTBL_LINK_MGF_SHIFT, true},
4465+ {NULL,}
4466+};
4467+
4468+static void parse_fmac_lwtbl_dw30(struct seq_file *s, u8 *lwtbl)
4469+{
4470+ u32 *addr = 0;
4471+ u32 dw_value = 0;
4472+ u16 i = 0;
4473+
4474+ /* LMAC WTBL DW 30 */
4475+ seq_printf(s, "\t\n");
4476+ seq_printf(s, "LWTBL DW 30\n");
4477+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_3*4]);
4478+ dw_value = *addr;
4479+
4480+
4481+ while (WTBL_LMAC_DW30[i].name) {
4482+ if (WTBL_LMAC_DW30[i].shift == NO_SHIFT_DEFINE)
4483+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW30[i].name,
4484+ (dw_value & WTBL_LMAC_DW30[i].mask) ? 1 : 0);
4485+ else
4486+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW30[i].name,
4487+ (dw_value & WTBL_LMAC_DW30[i].mask) >> WTBL_LMAC_DW30[i].shift);
4488+ i++;
4489+ }
4490+}
4491+
4492+static const struct berse_wtbl_parse WTBL_LMAC_DW31[] = {
4493+ {"BFTX_TB", WF_LWTBL_BFTX_TB_MASK, NO_SHIFT_DEFINE, false},
4494+ {"DROP", WF_LWTBL_DROP_MASK, NO_SHIFT_DEFINE, false},
4495+ {"CASCAD", WF_LWTBL_CASCAD_MASK, NO_SHIFT_DEFINE, false},
4496+ {"ALL_ACK", WF_LWTBL_ALL_ACK_MASK, NO_SHIFT_DEFINE, false},
4497+ {"MPDU_SIZE", WF_LWTBL_MPDU_SIZE_MASK, WF_LWTBL_MPDU_SIZE_SHIFT, false},
4498+ {"RXD_DUP_MODE", WF_LWTBL_RXD_DUP_MODE_MASK, WF_LWTBL_RXD_DUP_MODE_SHIFT, true},
4499+ {"ACK_EN", WF_LWTBL_ACK_EN_MASK, NO_SHIFT_DEFINE, true},
4500+ {NULL,}
4501+};
4502+
4503+static void parse_fmac_lwtbl_dw31(struct seq_file *s, u8 *lwtbl)
4504+{
4505+ u32 *addr = 0;
4506+ u32 dw_value = 0;
4507+ u16 i = 0;
4508+
4509+ /* LMAC WTBL DW 31 */
4510+ seq_printf(s, "\t\n");
4511+ seq_printf(s, "LWTBL DW 31\n");
4512+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RESP_INFO_DW_31*4]);
4513+ dw_value = *addr;
4514+
4515+ while (WTBL_LMAC_DW31[i].name) {
4516+ if (WTBL_LMAC_DW31[i].shift == NO_SHIFT_DEFINE)
4517+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW31[i].name,
4518+ (dw_value & WTBL_LMAC_DW31[i].mask) ? 1 : 0);
4519+ else
4520+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW31[i].name,
4521+ (dw_value & WTBL_LMAC_DW31[i].mask) >>
4522+ WTBL_LMAC_DW31[i].shift);
4523+ i++;
4524+ }
4525+}
4526+
4527+static const struct berse_wtbl_parse WTBL_LMAC_DW32[] = {
4528+ {"OM_INFO", WF_LWTBL_OM_INFO_MASK, WF_LWTBL_OM_INFO_SHIFT, false},
4529+ {"OM_INFO_EHT", WF_LWTBL_OM_INFO_EHT_MASK, WF_LWTBL_OM_INFO_EHT_SHIFT, false},
4530+ {"RXD_DUP_FOR_OM_CHG", WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK, NO_SHIFT_DEFINE, false},
4531+ {"RXD_DUP_WHITE_LIST", WF_LWTBL_RXD_DUP_WHITE_LIST_MASK, WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT, false},
4532+ {NULL,}
4533+};
4534+
4535+static void parse_fmac_lwtbl_dw32(struct seq_file *s, u8 *lwtbl)
4536+{
4537+ u32 *addr = 0;
4538+ u32 dw_value = 0;
4539+ u16 i = 0;
4540+
4541+ /* LMAC WTBL DW 32 */
4542+ seq_printf(s, "\t\n");
4543+ seq_printf(s, "LWTBL DW 32\n");
4544+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_DUP_INFO_DW_32*4]);
4545+ dw_value = *addr;
4546+
4547+ while (WTBL_LMAC_DW32[i].name) {
4548+ if (WTBL_LMAC_DW32[i].shift == NO_SHIFT_DEFINE)
4549+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW32[i].name,
4550+ (dw_value & WTBL_LMAC_DW32[i].mask) ? 1 : 0);
4551+ else
4552+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW32[i].name,
4553+ (dw_value & WTBL_LMAC_DW32[i].mask) >>
4554+ WTBL_LMAC_DW32[i].shift);
4555+ i++;
4556+ }
4557+}
4558+
4559+static const struct berse_wtbl_parse WTBL_LMAC_DW33[] = {
4560+ {"USER_RSSI", WF_LWTBL_USER_RSSI_MASK, WF_LWTBL_USER_RSSI_SHIFT, false},
4561+ {"USER_SNR", WF_LWTBL_USER_SNR_MASK, WF_LWTBL_USER_SNR_SHIFT, false},
4562+ {"RAPID_REACTION_RATE", WF_LWTBL_RAPID_REACTION_RATE_MASK, WF_LWTBL_RAPID_REACTION_RATE_SHIFT, true},
4563+ {"HT_AMSDU(Read Only)", WF_LWTBL_HT_AMSDU_MASK, NO_SHIFT_DEFINE, false},
4564+ {"AMSDU_CROSS_LG(Read Only)", WF_LWTBL_AMSDU_CROSS_LG_MASK, NO_SHIFT_DEFINE, true},
4565+ {NULL,}
4566+};
4567+
4568+static void parse_fmac_lwtbl_dw33(struct seq_file *s, u8 *lwtbl)
4569+{
4570+ u32 *addr = 0;
4571+ u32 dw_value = 0;
4572+ u16 i = 0;
4573+
4574+ /* LMAC WTBL DW 33 */
4575+ seq_printf(s, "\t\n");
4576+ seq_printf(s, "LWTBL DW 33\n");
4577+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_1*4]);
4578+ dw_value = *addr;
4579+
4580+ while (WTBL_LMAC_DW33[i].name) {
4581+ if (WTBL_LMAC_DW33[i].shift == NO_SHIFT_DEFINE)
4582+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW33[i].name,
4583+ (dw_value & WTBL_LMAC_DW33[i].mask) ? 1 : 0);
4584+ else
4585+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW33[i].name,
4586+ (dw_value & WTBL_LMAC_DW33[i].mask) >>
4587+ WTBL_LMAC_DW33[i].shift);
4588+ i++;
4589+ }
4590+}
4591+
4592+static const struct berse_wtbl_parse WTBL_LMAC_DW34[] = {
4593+ {"RESP_RCPI0", WF_LWTBL_RESP_RCPI0_MASK, WF_LWTBL_RESP_RCPI0_SHIFT, false},
4594+ {"RCPI1", WF_LWTBL_RESP_RCPI1_MASK, WF_LWTBL_RESP_RCPI1_SHIFT, false},
4595+ {"RCPI2", WF_LWTBL_RESP_RCPI2_MASK, WF_LWTBL_RESP_RCPI2_SHIFT, false},
4596+ {"RCPI3", WF_LWTBL_RESP_RCPI3_MASK, WF_LWTBL_RESP_RCPI3_SHIFT, true},
4597+ {NULL,}
4598+};
4599+
4600+static void parse_fmac_lwtbl_dw34(struct seq_file *s, u8 *lwtbl)
4601+{
4602+ u32 *addr = 0;
4603+ u32 dw_value = 0;
4604+ u16 i = 0;
4605+
4606+ /* LMAC WTBL DW 34 */
4607+ seq_printf(s, "\t\n");
4608+ seq_printf(s, "LWTBL DW 34\n");
4609+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_2*4]);
4610+ dw_value = *addr;
4611+
4612+
4613+ while (WTBL_LMAC_DW34[i].name) {
4614+ if (WTBL_LMAC_DW34[i].shift == NO_SHIFT_DEFINE)
4615+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW34[i].name,
4616+ (dw_value & WTBL_LMAC_DW34[i].mask) ? 1 : 0);
4617+ else
4618+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW34[i].name,
4619+ (dw_value & WTBL_LMAC_DW34[i].mask) >>
4620+ WTBL_LMAC_DW34[i].shift);
4621+ i++;
4622+ }
4623+}
4624+
4625+static const struct berse_wtbl_parse WTBL_LMAC_DW35[] = {
4626+ {"SNR 0", WF_LWTBL_SNR_RX0_MASK, WF_LWTBL_SNR_RX0_SHIFT, false},
4627+ {"SNR 1", WF_LWTBL_SNR_RX1_MASK, WF_LWTBL_SNR_RX1_SHIFT, false},
4628+ {"SNR 2", WF_LWTBL_SNR_RX2_MASK, WF_LWTBL_SNR_RX2_SHIFT, false},
4629+ {"SNR 3", WF_LWTBL_SNR_RX3_MASK, WF_LWTBL_SNR_RX3_SHIFT, true},
4630+ {NULL,}
4631+};
4632+
4633+static void parse_fmac_lwtbl_dw35(struct seq_file *s, u8 *lwtbl)
4634+{
4635+ u32 *addr = 0;
4636+ u32 dw_value = 0;
4637+ u16 i = 0;
4638+
4639+ /* LMAC WTBL DW 35 */
4640+ seq_printf(s, "\t\n");
4641+ seq_printf(s, "LWTBL DW 35\n");
4642+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_3*4]);
4643+ dw_value = *addr;
4644+
4645+
4646+ while (WTBL_LMAC_DW35[i].name) {
4647+ if (WTBL_LMAC_DW35[i].shift == NO_SHIFT_DEFINE)
4648+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW35[i].name,
4649+ (dw_value & WTBL_LMAC_DW35[i].mask) ? 1 : 0);
4650+ else
4651+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW35[i].name,
4652+ (dw_value & WTBL_LMAC_DW35[i].mask) >>
4653+ WTBL_LMAC_DW35[i].shift);
4654+ i++;
4655+ }
4656+}
4657+
4658+static void parse_fmac_lwtbl_rx_stats(struct seq_file *s, u8 *lwtbl)
4659+{
4660+ parse_fmac_lwtbl_dw33(s, lwtbl);
4661+ parse_fmac_lwtbl_dw34(s, lwtbl);
4662+ parse_fmac_lwtbl_dw35(s, lwtbl);
4663+}
4664+
4665+static void parse_fmac_lwtbl_mlo_info(struct seq_file *s, u8 *lwtbl)
4666+{
4667+ parse_fmac_lwtbl_dw28(s, lwtbl);
4668+ parse_fmac_lwtbl_dw29(s, lwtbl);
4669+ parse_fmac_lwtbl_dw30(s, lwtbl);
4670+}
4671+
4672+static const struct berse_wtbl_parse WTBL_UMAC_DW9[] = {
4673+ {"RELATED_IDX0", WF_UWTBL_RELATED_IDX0_MASK, WF_UWTBL_RELATED_IDX0_SHIFT, false},
4674+ {"RELATED_BAND0", WF_UWTBL_RELATED_BAND0_MASK, WF_UWTBL_RELATED_BAND0_SHIFT, false},
4675+ {"PRI_MLD_BAND", WF_UWTBL_PRIMARY_MLD_BAND_MASK, WF_UWTBL_PRIMARY_MLD_BAND_SHIFT, true},
4676+ {"RELATED_IDX1", WF_UWTBL_RELATED_IDX1_MASK, WF_UWTBL_RELATED_IDX1_SHIFT, false},
4677+ {"RELATED_BAND1", WF_UWTBL_RELATED_BAND1_MASK, WF_UWTBL_RELATED_BAND1_SHIFT, false},
4678+ {"SEC_MLD_BAND", WF_UWTBL_SECONDARY_MLD_BAND_MASK, WF_UWTBL_SECONDARY_MLD_BAND_SHIFT, true},
4679+ {NULL,}
4680+};
4681+
4682+static void parse_fmac_uwtbl_mlo_info(struct seq_file *s, u8 *uwtbl)
4683+{
4684+ u32 *addr = 0;
4685+ u32 dw_value = 0;
4686+ u16 i = 0;
4687+
4688+ seq_printf(s, "\t\n");
4689+ seq_printf(s, "MldAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
4690+ uwtbl[4], uwtbl[5], uwtbl[6], uwtbl[7], uwtbl[0], uwtbl[1]);
4691+
4692+ /* UMAC WTBL DW 0 */
4693+ seq_printf(s, "\t\n");
4694+ seq_printf(s, "UWTBL DW 0\n");
4695+ addr = (u32 *)&(uwtbl[WF_UWTBL_OWN_MLD_ID_DW*4]);
4696+ dw_value = *addr;
4697+
4698+ seq_printf(s, "\t%s:%u\n", "OMLD_ID",
4699+ (dw_value & WF_UWTBL_OWN_MLD_ID_MASK) >> WF_UWTBL_OWN_MLD_ID_SHIFT);
4700+
4701+ /* UMAC WTBL DW 9 */
4702+ seq_printf(s, "\t\n");
4703+ seq_printf(s, "UWTBL DW 9\n");
4704+ addr = (u32 *)&(uwtbl[WF_UWTBL_RELATED_IDX0_DW*4]);
4705+ dw_value = *addr;
4706+
4707+ while (WTBL_UMAC_DW9[i].name) {
4708+
4709+ if (WTBL_UMAC_DW9[i].shift == NO_SHIFT_DEFINE)
4710+ seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW9[i].name,
4711+ (dw_value & WTBL_UMAC_DW9[i].mask) ? 1 : 0);
4712+ else
4713+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW9[i].name,
4714+ (dw_value & WTBL_UMAC_DW9[i].mask) >>
4715+ WTBL_UMAC_DW9[i].shift);
4716+ i++;
4717+ }
4718+}
4719+
4720+static bool
4721+is_wtbl_bigtk_exist(u8 *lwtbl)
4722+{
4723+ u32 *addr = 0;
4724+ u32 dw_value = 0;
4725+
4726+ addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]);
4727+ dw_value = *addr;
4728+ if (((dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT) ==
4729+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC) {
4730+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_BIGTK_DW*4]);
4731+ dw_value = *addr;
4732+ if (((dw_value & WF_LWTBL_CIPHER_SUIT_BIGTK_MASK) >>
4733+ WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT) != IGTK_CIPHER_SUIT_NONE)
4734+ return true;
4735+ }
4736+
4737+ return false;
4738+}
4739+
4740+static const struct berse_wtbl_parse WTBL_UMAC_DW2[] = {
4741+ {"PN0", WTBL_PN0_MASK, WTBL_PN0_OFFSET, false},
4742+ {"PN1", WTBL_PN1_MASK, WTBL_PN1_OFFSET, false},
4743+ {"PN2", WTBL_PN2_MASK, WTBL_PN2_OFFSET, true},
4744+ {"PN3", WTBL_PN3_MASK, WTBL_PN3_OFFSET, false},
4745+ {NULL,}
4746+};
4747+
4748+static const struct berse_wtbl_parse WTBL_UMAC_DW3[] = {
4749+ {"PN4", WTBL_PN4_MASK, WTBL_PN4_OFFSET, false},
4750+ {"PN5", WTBL_PN5_MASK, WTBL_PN5_OFFSET, true},
4751+ {"COM_SN", WF_UWTBL_COM_SN_MASK, WF_UWTBL_COM_SN_SHIFT, true},
4752+ {NULL,}
4753+};
4754+
4755+static const struct berse_wtbl_parse WTBL_UMAC_DW4_BIPN[] = {
4756+ {"BIPN0", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false},
4757+ {"BIPN1", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, false},
4758+ {"BIPN2", WTBL_BIPN2_MASK, WTBL_BIPN2_OFFSET, true},
4759+ {"BIPN3", WTBL_BIPN3_MASK, WTBL_BIPN3_OFFSET, false},
4760+ {NULL,}
4761+};
4762+
4763+static const struct berse_wtbl_parse WTBL_UMAC_DW5_BIPN[] = {
4764+ {"BIPN4", WTBL_BIPN4_MASK, WTBL_BIPN4_OFFSET, false},
4765+ {"BIPN5", WTBL_BIPN5_MASK, WTBL_BIPN5_OFFSET, true},
4766+ {NULL,}
4767+};
4768+
4769+static void parse_fmac_uwtbl_pn(struct seq_file *s, u8 *uwtbl, u8 *lwtbl)
4770+{
4771+ u32 *addr = 0;
4772+ u32 dw_value = 0;
4773+ u16 i = 0;
4774+
4775+ seq_printf(s, "\t\n");
4776+ seq_printf(s, "UWTBL PN\n");
4777+
4778+ /* UMAC WTBL DW 2/3 */
4779+ addr = (u32 *)&(uwtbl[WF_UWTBL_PN_31_0__DW*4]);
4780+ dw_value = *addr;
4781+
4782+ while (WTBL_UMAC_DW2[i].name) {
4783+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW2[i].name,
4784+ (dw_value & WTBL_UMAC_DW2[i].mask) >>
4785+ WTBL_UMAC_DW2[i].shift);
4786+ i++;
4787+ }
4788+
4789+ i = 0;
4790+ addr = (u32 *)&(uwtbl[WF_UWTBL_PN_47_32__DW*4]);
4791+ dw_value = *addr;
4792+
4793+ while (WTBL_UMAC_DW3[i].name) {
4794+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW3[i].name,
4795+ (dw_value & WTBL_UMAC_DW3[i].mask) >>
4796+ WTBL_UMAC_DW3[i].shift);
4797+ i++;
4798+ }
4799+
4800+
4801+ /* UMAC WTBL DW 4/5 for BIGTK */
4802+ if (is_wtbl_bigtk_exist(lwtbl) == true) {
4803+ i = 0;
4804+ addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_31_0__DW*4]);
4805+ dw_value = *addr;
4806+
4807+ while (WTBL_UMAC_DW4_BIPN[i].name) {
4808+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW4_BIPN[i].name,
4809+ (dw_value & WTBL_UMAC_DW4_BIPN[i].mask) >>
4810+ WTBL_UMAC_DW4_BIPN[i].shift);
4811+ i++;
4812+ }
4813+
4814+ i = 0;
4815+ addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_47_32__DW*4]);
4816+ dw_value = *addr;
4817+
4818+ while (WTBL_UMAC_DW5_BIPN[i].name) {
4819+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW5_BIPN[i].name,
4820+ (dw_value & WTBL_UMAC_DW5_BIPN[i].mask) >>
4821+ WTBL_UMAC_DW5_BIPN[i].shift);
4822+ i++;
4823+ }
4824+ }
4825+}
4826+
4827+static void parse_fmac_uwtbl_sn(struct seq_file *s, u8 *uwtbl)
4828+{
4829+ u32 *addr = 0;
4830+ u32 u2SN = 0;
4831+
4832+ /* UMAC WTBL DW SN part */
4833+ seq_printf(s, "\t\n");
4834+ seq_printf(s, "UWTBL SN\n");
4835+
4836+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID0_SN_DW*4]);
4837+ u2SN = ((*addr) & WF_UWTBL_TID0_SN_MASK) >> WF_UWTBL_TID0_SN_SHIFT;
4838+ seq_printf(s, "\t%s:%u\n", "TID0_AC0_SN", u2SN);
4839+
4840+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID1_SN_DW*4]);
4841+ u2SN = ((*addr) & WF_UWTBL_TID1_SN_MASK) >> WF_UWTBL_TID1_SN_SHIFT;
4842+ seq_printf(s, "\t%s:%u\n", "TID1_AC1_SN", u2SN);
4843+
4844+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_7_0__DW*4]);
4845+ u2SN = ((*addr) & WF_UWTBL_TID2_SN_7_0__MASK) >>
4846+ WF_UWTBL_TID2_SN_7_0__SHIFT;
4847+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_11_8__DW*4]);
4848+ u2SN |= (((*addr) & WF_UWTBL_TID2_SN_11_8__MASK) >>
4849+ WF_UWTBL_TID2_SN_11_8__SHIFT) << 8;
4850+ seq_printf(s, "\t%s:%u\n", "TID2_AC2_SN", u2SN);
4851+
4852+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID3_SN_DW*4]);
4853+ u2SN = ((*addr) & WF_UWTBL_TID3_SN_MASK) >> WF_UWTBL_TID3_SN_SHIFT;
4854+ seq_printf(s, "\t%s:%u\n", "TID3_AC3_SN", u2SN);
4855+
4856+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID4_SN_DW*4]);
4857+ u2SN = ((*addr) & WF_UWTBL_TID4_SN_MASK) >> WF_UWTBL_TID4_SN_SHIFT;
4858+ seq_printf(s, "\t%s:%u\n", "TID4_SN", u2SN);
4859+
4860+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_3_0__DW*4]);
4861+ u2SN = ((*addr) & WF_UWTBL_TID5_SN_3_0__MASK) >>
4862+ WF_UWTBL_TID5_SN_3_0__SHIFT;
4863+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_11_4__DW*4]);
4864+ u2SN |= (((*addr) & WF_UWTBL_TID5_SN_11_4__MASK) >>
4865+ WF_UWTBL_TID5_SN_11_4__SHIFT) << 4;
4866+ seq_printf(s, "\t%s:%u\n", "TID5_SN", u2SN);
4867+
4868+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID6_SN_DW*4]);
4869+ u2SN = ((*addr) & WF_UWTBL_TID6_SN_MASK) >> WF_UWTBL_TID6_SN_SHIFT;
4870+ seq_printf(s, "\t%s:%u\n", "TID6_SN", u2SN);
4871+
4872+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID7_SN_DW*4]);
4873+ u2SN = ((*addr) & WF_UWTBL_TID7_SN_MASK) >> WF_UWTBL_TID7_SN_SHIFT;
4874+ seq_printf(s, "\t%s:%u\n", "TID7_SN", u2SN);
4875+
4876+ addr = (u32 *)&(uwtbl[WF_UWTBL_COM_SN_DW*4]);
4877+ u2SN = ((*addr) & WF_UWTBL_COM_SN_MASK) >> WF_UWTBL_COM_SN_SHIFT;
4878+ seq_printf(s, "\t%s:%u\n", "COM_SN", u2SN);
4879+}
4880+
4881+static void dump_key_table(
4882+ struct seq_file *s,
4883+ uint16_t keyloc0,
4884+ uint16_t keyloc1,
4885+ uint16_t keyloc2
4886+)
4887+{
4888+#define ONE_KEY_ENTRY_LEN_IN_DW 8
4889+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4890+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
4891+ uint16_t x;
4892+
4893+ seq_printf(s, "\t\n");
4894+ seq_printf(s, "\t%s:%d\n", "keyloc0", keyloc0);
4895+ if (keyloc0 != INVALID_KEY_ENTRY) {
4896+
4897+ /* Don't swap below two lines, halWtblReadRaw will
4898+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4899+ */
4900+ mt7996_wtbl_read_raw(dev, keyloc0,
4901+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4902+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4903+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4904+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4905+ KEYTBL_IDX2BASE(keyloc0, 0));
4906+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4907+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4908+ x,
4909+ keytbl[x * 4 + 3],
4910+ keytbl[x * 4 + 2],
4911+ keytbl[x * 4 + 1],
4912+ keytbl[x * 4]);
4913+ }
4914+ }
4915+
4916+ seq_printf(s, "\t%s:%d\n", "keyloc1", keyloc1);
4917+ if (keyloc1 != INVALID_KEY_ENTRY) {
4918+ /* Don't swap below two lines, halWtblReadRaw will
4919+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4920+ */
4921+ mt7996_wtbl_read_raw(dev, keyloc1,
4922+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4923+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4924+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4925+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4926+ KEYTBL_IDX2BASE(keyloc1, 0));
4927+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4928+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4929+ x,
4930+ keytbl[x * 4 + 3],
4931+ keytbl[x * 4 + 2],
4932+ keytbl[x * 4 + 1],
4933+ keytbl[x * 4]);
4934+ }
4935+ }
4936+
4937+ seq_printf(s, "\t%s:%d\n", "keyloc2", keyloc2);
4938+ if (keyloc2 != INVALID_KEY_ENTRY) {
4939+ /* Don't swap below two lines, halWtblReadRaw will
4940+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4941+ */
4942+ mt7996_wtbl_read_raw(dev, keyloc2,
4943+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4944+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4945+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4946+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4947+ KEYTBL_IDX2BASE(keyloc2, 0));
4948+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4949+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4950+ x,
4951+ keytbl[x * 4 + 3],
4952+ keytbl[x * 4 + 2],
4953+ keytbl[x * 4 + 1],
4954+ keytbl[x * 4]);
4955+ }
4956+ }
4957+}
4958+
4959+static void parse_fmac_uwtbl_key_info(struct seq_file *s, u8 *uwtbl, u8 *lwtbl)
4960+{
4961+ u32 *addr = 0;
4962+ u32 dw_value = 0;
4963+ uint16_t keyloc0 = INVALID_KEY_ENTRY;
4964+ uint16_t keyloc1 = INVALID_KEY_ENTRY;
4965+ uint16_t keyloc2 = INVALID_KEY_ENTRY;
4966+
4967+ /* UMAC WTBL DW 7 */
4968+ seq_printf(s, "\t\n");
4969+ seq_printf(s, "UWTBL key info\n");
4970+
4971+ addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC0_DW*4]);
4972+ dw_value = *addr;
4973+ keyloc0 = (dw_value & WF_UWTBL_KEY_LOC0_MASK) >> WF_UWTBL_KEY_LOC0_SHIFT;
4974+ keyloc1 = (dw_value & WF_UWTBL_KEY_LOC1_MASK) >> WF_UWTBL_KEY_LOC1_SHIFT;
4975+
4976+ seq_printf(s, "\t%s:%u/%u\n", "Key Loc 0/1", keyloc0, keyloc1);
4977+
4978+ /* UMAC WTBL DW 6 for BIGTK */
4979+ if (is_wtbl_bigtk_exist(lwtbl) == true) {
4980+ addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC2_DW*4]);
4981+ dw_value = *addr;
4982+ keyloc2 = (dw_value & WF_UWTBL_KEY_LOC2_MASK) >>
4983+ WF_UWTBL_KEY_LOC2_SHIFT;
4984+ seq_printf(s, "\t%s:%u\n", "Key Loc 2", keyloc2);
4985+ }
4986+
4987+ /* Parse KEY link */
4988+ dump_key_table(s, keyloc0, keyloc1, keyloc2);
4989+}
4990+
4991+static const struct berse_wtbl_parse WTBL_UMAC_DW8[] = {
4992+ {"UWTBL_WMM_Q", WF_UWTBL_WMM_Q_MASK, WF_UWTBL_WMM_Q_SHIFT, false},
4993+ {"UWTBL_QOS", WF_UWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
4994+ {"UWTBL_HT_VHT_HE", WF_UWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
4995+ {"UWTBL_HDRT_MODE", WF_UWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, true},
4996+ {NULL,}
4997+};
4998+
4999+static void parse_fmac_uwtbl_msdu_info(struct seq_file *s, u8 *uwtbl)
5000+{
5001+ u32 *addr = 0;
5002+ u32 dw_value = 0;
5003+ u32 amsdu_len = 0;
5004+ u16 i = 0;
5005+
5006+ /* UMAC WTBL DW 8 */
5007+ seq_printf(s, "\t\n");
5008+ seq_printf(s, "UWTBL DW8\n");
5009+
5010+ addr = (u32 *)&(uwtbl[WF_UWTBL_AMSDU_CFG_DW*4]);
5011+ dw_value = *addr;
5012+
5013+ while (WTBL_UMAC_DW8[i].name) {
5014+
5015+ if (WTBL_UMAC_DW8[i].shift == NO_SHIFT_DEFINE)
5016+ seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW8[i].name,
5017+ (dw_value & WTBL_UMAC_DW8[i].mask) ? 1 : 0);
5018+ else
5019+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW8[i].name,
5020+ (dw_value & WTBL_UMAC_DW8[i].mask) >>
5021+ WTBL_UMAC_DW8[i].shift);
5022+ i++;
5023+ }
5024+
5025+ /* UMAC WTBL DW 8 - SEC_ADDR_MODE */
5026+ addr = (u32 *)&(uwtbl[WF_UWTBL_SEC_ADDR_MODE_DW*4]);
5027+ dw_value = *addr;
5028+ seq_printf(s, "\t%s:%lu\n", "SEC_ADDR_MODE",
5029+ (dw_value & WTBL_SEC_ADDR_MODE_MASK) >> WTBL_SEC_ADDR_MODE_OFFSET);
5030+
5031+ /* UMAC WTBL DW 8 - AMSDU_CFG */
5032+ seq_printf(s, "\t%s:%d\n", "HW AMSDU Enable",
5033+ (dw_value & WTBL_AMSDU_EN_MASK) ? 1 : 0);
5034+
5035+ amsdu_len = (dw_value & WTBL_AMSDU_LEN_MASK) >> WTBL_AMSDU_LEN_OFFSET;
5036+ if (amsdu_len == 0)
5037+ seq_printf(s, "\t%s:invalid (WTBL value=0x%x)\n", "HW AMSDU Len",
5038+ amsdu_len);
5039+ else if (amsdu_len == 1)
5040+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
5041+ 1,
5042+ 255,
5043+ amsdu_len);
5044+ else if (amsdu_len == 2)
5045+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
5046+ 256,
5047+ 511,
5048+ amsdu_len);
5049+ else if (amsdu_len == 3)
5050+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
5051+ 512,
5052+ 767,
5053+ amsdu_len);
5054+ else
5055+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
5056+ 256 * (amsdu_len - 1),
5057+ 256 * (amsdu_len - 1) + 255,
5058+ amsdu_len);
5059+
5060+ seq_printf(s, "\t%s:%lu (WTBL value=0x%lx)\n", "HW AMSDU Num",
5061+ ((dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET) + 1,
5062+ (dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET);
5063+}
5064+
5065+static int mt7996_wtbl_read(struct seq_file *s, void *data)
5066+{
5067+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
5068+ u8 lwtbl[LWTBL_LEN_IN_DW * 4] = {0};
5069+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
5070+ int x;
5071+
5072+ mt7996_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
5073+ LWTBL_LEN_IN_DW, lwtbl);
5074+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
5075+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
5076+ MT_DBG_WTBLON_TOP_WDUCR_ADDR,
5077+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR),
5078+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
5079+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
5080+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
5081+ x,
5082+ lwtbl[x * 4 + 3],
5083+ lwtbl[x * 4 + 2],
5084+ lwtbl[x * 4 + 1],
5085+ lwtbl[x * 4]);
5086+ }
5087+
5088+ /* Parse LWTBL */
5089+ parse_fmac_lwtbl_dw0_1(s, lwtbl);
5090+ parse_fmac_lwtbl_dw2(s, lwtbl);
5091+ parse_fmac_lwtbl_dw3(s, lwtbl);
5092+ parse_fmac_lwtbl_dw4(s, lwtbl);
5093+ parse_fmac_lwtbl_dw5(s, lwtbl);
5094+ parse_fmac_lwtbl_dw6(s, lwtbl);
5095+ parse_fmac_lwtbl_dw7(s, lwtbl);
5096+ parse_fmac_lwtbl_dw8(s, lwtbl);
5097+ parse_fmac_lwtbl_dw9(s, lwtbl);
5098+ parse_fmac_lwtbl_dw10(s, lwtbl);
5099+ parse_fmac_lwtbl_dw11(s, lwtbl);
5100+ parse_fmac_lwtbl_dw12(s, lwtbl);
5101+ parse_fmac_lwtbl_dw13(s, lwtbl);
5102+ parse_fmac_lwtbl_dw14(s, lwtbl);
5103+ parse_fmac_lwtbl_mlo_info(s, lwtbl);
5104+ parse_fmac_lwtbl_dw31(s, lwtbl);
5105+ parse_fmac_lwtbl_dw32(s, lwtbl);
5106+ parse_fmac_lwtbl_rx_stats(s, lwtbl);
5107+
5108+ mt7996_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
5109+ UWTBL_LEN_IN_DW, uwtbl);
5110+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
5111+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
5112+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
5113+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
5114+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
5115+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
5116+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
5117+ x,
5118+ uwtbl[x * 4 + 3],
5119+ uwtbl[x * 4 + 2],
5120+ uwtbl[x * 4 + 1],
5121+ uwtbl[x * 4]);
5122+ }
5123+
5124+ /* Parse UWTBL */
5125+ parse_fmac_uwtbl_mlo_info(s, uwtbl);
5126+ parse_fmac_uwtbl_pn(s, uwtbl, lwtbl);
5127+ parse_fmac_uwtbl_sn(s, uwtbl);
5128+ parse_fmac_uwtbl_key_info(s, uwtbl, lwtbl);
5129+ parse_fmac_uwtbl_msdu_info(s, uwtbl);
5130+
5131+ return 0;
5132+}
5133+
5134+static int mt7996_sta_info(struct seq_file *s, void *data)
5135+{
5136+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
5137+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
5138+ u16 i = 0;
5139+
5140+ for (i=0; i < mt7996_wtbl_size(dev); i++) {
5141+ mt7996_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
5142+ LWTBL_LEN_IN_DW, lwtbl);
5143+
5144+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1]) {
5145+ u32 *addr, dw_value;
5146+
5147+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x",
5148+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
5149+
5150+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]);
5151+ dw_value = *addr;
5152+ seq_printf(s, "\t%s:%u", WTBL_LMAC_DW2[0].name,
5153+ (dw_value & WTBL_LMAC_DW2[0].mask) >> WTBL_LMAC_DW2[0].shift);
5154+
5155+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_5*4]);
5156+ dw_value = *addr;
5157+ seq_printf(s, "\tPSM:%u\n", !!(dw_value & WF_LWTBL_PSM_MASK));
5158+ }
5159+ }
5160+
5161+ return 0;
5162+}
5163+
5164+static int mt7996_token_read(struct seq_file *s, void *data)
5165+{
5166+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
5167+ int msdu_id;
5168+ struct mt76_txwi_cache *txwi;
5169+
5170+ seq_printf(s, "Token from host:\n");
5171+ spin_lock_bh(&dev->mt76.token_lock);
5172+ idr_for_each_entry(&dev->mt76.token, txwi, msdu_id) {
5173+ seq_printf(s, "%4d (pending time %u ms)\n", msdu_id,
5174+ jiffies_to_msecs(jiffies - txwi->jiffies));
5175+ }
5176+ spin_unlock_bh(&dev->mt76.token_lock);
5177+ seq_printf(s, "\n");
5178+
5179+ return 0;
5180+}
5181+
5182+int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir)
5183+{
5184+ struct mt7996_dev *dev = phy->dev;
5185+ u32 device_id = (dev->mt76.rev) >> 16;
5186+ int i = 0;
5187+ static const struct mt7996_dbg_reg_desc dbg_reg_s[] = {
5188+ { 0x7990, mt7996_dbg_offs },
5189+ { 0x7992, mt7992_dbg_offs },
5190+ };
5191+
5192+ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
5193+ if (device_id == dbg_reg_s[i].id) {
5194+ dev->dbg_reg = &dbg_reg_s[i];
5195+ break;
5196+ }
5197+ }
5198+
5199+ if (is_mt7996(&dev->mt76)) {
5200+ WTBL_LMAC_DW2 = WTBL_LMAC_DW2_7996;
5201+ WTBL_LMAC_DW5 = WTBL_LMAC_DW5_7996;
5202+ WTBL_LMAC_DW9 = WTBL_LMAC_DW9_7996;
5203+ } else {
5204+ WTBL_LMAC_DW2 = WTBL_LMAC_DW2_7992;
5205+ WTBL_LMAC_DW5 = WTBL_LMAC_DW5_7992;
5206+ WTBL_LMAC_DW9 = WTBL_LMAC_DW9_7992;
5207+ }
5208+
5209+ /* agg */
5210+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
5211+ mt7996_agginfo_read_band0);
5212+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
5213+ mt7996_agginfo_read_band1);
5214+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info2", dir,
5215+ mt7996_agginfo_read_band2);
5216+ /* amsdu */
5217+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
5218+ mt7996_amsdu_result_read);
5219+
5220+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
5221+ &fops_fw_debug_module);
5222+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
5223+ &fops_fw_debug_level);
5224+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
5225+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
5226+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_version", dir,
5227+ mt7996_dump_version);
5228+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wa_info", dir,
5229+ mt7996_fw_wa_info_read);
5230+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wm_info", dir,
5231+ mt7996_fw_wm_info_read);
5232+
5233+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
5234+ mt7996_mibinfo_band0);
5235+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
5236+ mt7996_mibinfo_band1);
5237+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info2", dir,
5238+ mt7996_mibinfo_band2);
5239+
5240+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
5241+ mt7996_sta_info);
5242+
5243+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
5244+ mt7996_trinfo_read);
5245+
5246+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
5247+ mt7996_wtbl_read);
5248+
5249+ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir, mt7996_token_read);
5250+
5251+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
5252+
5253+ return 0;
5254+}
5255+
5256+#endif
5257diff --git a/mt7996/mtk_mcu.c b/mt7996/mtk_mcu.c
5258new file mode 100644
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]5259index 0000000..c16b25a
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]5260--- /dev/null
5261+++ b/mt7996/mtk_mcu.c
5262@@ -0,0 +1,39 @@
5263+// SPDX-License-Identifier: ISC
5264+/*
5265+ * Copyright (C) 2023 MediaTek Inc.
5266+ */
5267+
5268+#include <linux/firmware.h>
5269+#include <linux/fs.h>
5270+#include "mt7996.h"
5271+#include "mcu.h"
5272+#include "mac.h"
5273+#include "mtk_mcu.h"
5274+
5275+#ifdef CONFIG_MTK_DEBUG
5276+
5277+
5278+
5279+
5280+int mt7996_mcu_muru_dbg_info(struct mt7996_dev *dev, u16 item, u8 val)
5281+{
5282+ struct {
5283+ u8 __rsv1[4];
5284+
5285+ __le16 tag;
5286+ __le16 len;
5287+
5288+ __le16 item;
5289+ u8 __rsv2[2];
5290+ __le32 value;
5291+ } __packed req = {
5292+ .tag = cpu_to_le16(UNI_CMD_MURU_DBG_INFO),
5293+ .len = cpu_to_le16(sizeof(req) - 4),
5294+ .item = cpu_to_le16(item),
5295+ .value = cpu_to_le32(val),
5296+ };
5297+
5298+ return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(MURU), &req,
5299+ sizeof(req), true);
5300+}
5301+#endif
5302diff --git a/mt7996/mtk_mcu.h b/mt7996/mtk_mcu.h
5303new file mode 100644
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]5304index 0000000..7f4d4e0
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]5305--- /dev/null
5306+++ b/mt7996/mtk_mcu.h
5307@@ -0,0 +1,19 @@
5308+/* SPDX-License-Identifier: ISC */
5309+/*
5310+ * Copyright (C) 2023 MediaTek Inc.
5311+ */
5312+
5313+#ifndef __MT7996_MTK_MCU_H
5314+#define __MT7996_MTK_MCU_H
5315+
5316+#include "../mt76_connac_mcu.h"
5317+
5318+#ifdef CONFIG_MTK_DEBUG
5319+
5320+enum {
5321+ UNI_CMD_MURU_DBG_INFO = 0x18,
5322+};
5323+
5324+#endif
5325+
5326+#endif
5327diff --git a/tools/fwlog.c b/tools/fwlog.c
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]5328index e5d4a10..3c6a61d 100644
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]5329--- a/tools/fwlog.c
5330+++ b/tools/fwlog.c
5331@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
5332 return path;
5333 }
5334
5335-static int mt76_set_fwlog_en(const char *phyname, bool en)
5336+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
5337 {
5338 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
5339
5340@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
5341 return 1;
5342 }
5343
5344- fprintf(f, "7");
5345+ if (en && val)
5346+ fprintf(f, "%s", val);
5347+ else if (en)
5348+ fprintf(f, "7");
5349+ else
5350+ fprintf(f, "0");
5351+
5352 fclose(f);
5353
5354 return 0;
5355@@ -76,6 +82,7 @@ static void handle_signal(int sig)
5356
5357 int mt76_fwlog(const char *phyname, int argc, char **argv)
5358 {
5359+#define BUF_SIZE 1504
5360 struct sockaddr_in local = {
5361 .sin_family = AF_INET,
5362 .sin_addr.s_addr = INADDR_ANY,
5363@@ -84,9 +91,9 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5364 .sin_family = AF_INET,
5365 .sin_port = htons(55688),
5366 };
5367- char buf[1504];
5368+ char *buf = calloc(BUF_SIZE, sizeof(char));
5369 int ret = 0;
5370- int yes = 1;
5371+ /* int yes = 1; */
5372 int s, fd;
5373
5374 if (argc < 1) {
5375@@ -105,13 +112,13 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5376 return 1;
5377 }
5378
5379- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
5380+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
5381 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
5382 perror("bind");
5383 return 1;
5384 }
5385
5386- if (mt76_set_fwlog_en(phyname, true))
5387+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
5388 return 1;
5389
5390 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
5391@@ -145,8 +152,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5392 if (!r)
5393 continue;
5394
5395- if (len > sizeof(buf)) {
5396- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
5397+ if (len > BUF_SIZE) {
5398+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
5399 ret = 1;
5400 break;
5401 }
5402@@ -171,7 +178,7 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5403 close(fd);
5404
5405 out:
5406- mt76_set_fwlog_en(phyname, false);
5407+ mt76_set_fwlog_en(phyname, false, NULL);
5408
5409 return ret;
5410 }
5411--
developer9237f442024-06-14 17:13:04 +0800[diff] [blame]54122.18.0
developer66e89bc2024-04-23 14:50:01 +0800[diff] [blame]5413