blob: 94d8389b39b3bd1dff2e6a5696af30e91d26e418 [file] [log] [blame]
developer5dfa8b72022-11-03 11:33:07 +08001/*
2 * switch_netlink.h: switch(netlink) set API
developercc8110b2024-08-19 13:53:34 +08003 *
developer5dfa8b72022-11-03 11:33:07 +08004 * Author: Sirui Zhao <Sirui.Zhao@mediatek.com>
5 */
6#ifndef MT753X_NETLINK_H
7#define MT753X_NETLINK_H
8
9#define MT753X_GENL_NAME "mt753x"
10#define MT753X_DSA_GENL_NAME "mt753x_dsa"
11#define MT753X_GENL_VERSION 0X1
developere78dab52024-03-25 14:26:39 +080012#define AN8855_GENL_NAME "an8855"
13#define AN8855_DSA_GENL_NAME "an8855_dsa"
developer5dfa8b72022-11-03 11:33:07 +080014
15/*add your cmd to here*/
16enum {
developere78dab52024-03-25 14:26:39 +080017 MT753X_CMD_UNSPEC = 0, /*Reserved */
18 MT753X_CMD_REQUEST, /*user->kernelrequest/get-response */
19 MT753X_CMD_REPLY, /*kernel->user event */
developer5dfa8b72022-11-03 11:33:07 +080020 MT753X_CMD_READ,
21 MT753X_CMD_WRITE,
22 __MT753X_CMD_MAX,
23};
24#define MT753X_CMD_MAX (__MT753X_CMD_MAX - 1)
25
26/*define attar types */
developere78dab52024-03-25 14:26:39 +080027enum {
developer5dfa8b72022-11-03 11:33:07 +080028 MT753X_ATTR_TYPE_UNSPEC = 0,
developere78dab52024-03-25 14:26:39 +080029 MT753X_ATTR_TYPE_MESG, /*MT753X message */
developer5dfa8b72022-11-03 11:33:07 +080030 MT753X_ATTR_TYPE_PHY,
31 MT753X_ATTR_TYPE_PHY_DEV,
32 MT753X_ATTR_TYPE_REG,
33 MT753X_ATTR_TYPE_VAL,
34 MT753X_ATTR_TYPE_DEV_NAME,
35 MT753X_ATTR_TYPE_DEV_ID,
36 __MT753X_ATTR_TYPE_MAX,
37};
38#define MT753X_ATTR_TYPE_MAX (__MT753X_ATTR_TYPE_MAX - 1)
39
40struct mt753x_attr {
41 int port_num;
42 int phy_dev;
43 int reg;
44 int value;
45 int type;
46 char op;
47 char *dev_info;
48 int dev_name;
49 int dev_id;
50};
51
developere78dab52024-03-25 14:26:39 +080052extern int chip_name;
53
developer5dfa8b72022-11-03 11:33:07 +080054int mt753x_netlink_init(const char *name);
55void mt753x_netlink_free(void);
56void mt753x_list_swdev(struct mt753x_attr *arg, int cmd);
developercc8110b2024-08-19 13:53:34 +080057int reg_read_netlink(struct mt753x_attr *arg, unsigned int offset, unsigned int *value);
58int reg_write_netlink(struct mt753x_attr *arg, unsigned int offset, unsigned int value);
developer5dfa8b72022-11-03 11:33:07 +080059int phy_cl22_read_netlink(struct mt753x_attr *arg, unsigned int port_num,
developercc8110b2024-08-19 13:53:34 +080060 unsigned int phy_addr, unsigned int *value);
developer5dfa8b72022-11-03 11:33:07 +080061int phy_cl22_write_netlink(struct mt753x_attr *arg, unsigned int port_num,
developercc8110b2024-08-19 13:53:34 +080062 unsigned int phy_addr, unsigned int value);
developer5dfa8b72022-11-03 11:33:07 +080063int phy_cl45_read_netlink(struct mt753x_attr *arg, unsigned int port_num,
developercc8110b2024-08-19 13:53:34 +080064 unsigned int phy_dev, unsigned int phy_addr, unsigned int *value);
developer5dfa8b72022-11-03 11:33:07 +080065int phy_cl45_write_netlink(struct mt753x_attr *arg, unsigned int port_num,
developercc8110b2024-08-19 13:53:34 +080066 unsigned int phy_dev, unsigned int phy_addr, unsigned int value);
developer5dfa8b72022-11-03 11:33:07 +080067int phy_dump_netlink(struct mt753x_attr *arg, int phy_addr);
68
69#endif