blob: de7d36b6f85afbc2b7c757d7021bf57dee5b7715 [file] [log] [blame]
developer21ea8132022-07-11 11:52:59 +08001/*
2 * switch_netlink.h: switch(netlink) set API
3 *
4 * Author: Sirui Zhao <Sirui.Zhao@mediatek.com>
5 */
6#ifndef MT753X_NETLINK_H
7#define MT753X_NETLINK_H
8
9#define MT753X_GENL_NAME "mt753x"
10#define MT753X_GENL_VERSION 0X1
11
12/*add your cmd to here*/
13enum {
14 MT753X_CMD_UNSPEC = 0, /*Reserved*/
15 MT753X_CMD_REQUEST, /*user->kernelrequest/get-response*/
16 MT753X_CMD_REPLY, /*kernel->user event*/
17 MT753X_CMD_READ,
18 MT753X_CMD_WRITE,
19 __MT753X_CMD_MAX,
20};
21#define MT753X_CMD_MAX (__MT753X_CMD_MAX - 1)
22
23/*define attar types */
24enum
25{
26 MT753X_ATTR_TYPE_UNSPEC = 0,
27 MT753X_ATTR_TYPE_MESG, /*MT753X message*/
28 MT753X_ATTR_TYPE_PHY,
29 MT753X_ATTR_TYPE_PHY_DEV,
30 MT753X_ATTR_TYPE_REG,
31 MT753X_ATTR_TYPE_VAL,
32 MT753X_ATTR_TYPE_DEV_NAME,
33 MT753X_ATTR_TYPE_DEV_ID,
34 __MT753X_ATTR_TYPE_MAX,
35};
36#define MT753X_ATTR_TYPE_MAX (__MT753X_ATTR_TYPE_MAX - 1)
37
38struct mt753x_attr {
39 int port_num;
40 int phy_dev;
41 int reg;
42 int value;
43 int type;
44 char op;
45 char *dev_info;
46 int dev_name;
47 int dev_id;
48};
49
50int mt753x_netlink_init(void);
51void mt753x_netlink_free(void);
52void mt753x_list_swdev(struct mt753x_attr *arg, int cmd);
53int reg_read_netlink(struct mt753x_attr *arg, int offset, int *value);
54int reg_write_netlink(struct mt753x_attr *arg, int offset, int value);
55int phy_cl22_read_netlink(struct mt753x_attr *arg, int port_num, int phy_addr, int *value);
56int phy_cl22_write_netlink(struct mt753x_attr *arg, int port_num, int phy_addr, int value);
57int phy_cl45_read_netlink(struct mt753x_attr *arg, int port_num, int phy_dev,
58 int phy_addr, int *value);
59int phy_cl45_write_netlink(struct mt753x_attr *arg, int port_num, int phy_dev,
60 int phy_addr, int value);
61int phy_dump_netlink(struct mt753x_attr *arg, int phy_addr);
62
63#endif