developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 1 | From patchwork Thu May 28 06:16:48 2020 |
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| 72 | From: <chuanjia.liu@mediatek.com> |
| 73 | To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com> |
| 74 | Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node |
| 75 | Date: Thu, 28 May 2020 14:16:48 +0800 |
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| 116 | Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, |
| 117 | srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>, |
| 118 | linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, |
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| 120 | yong.wu@mediatek.com, bhelgaas@google.com, |
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| 123 | Errors-To: |
| 124 | linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org |
| 125 | |
| 126 | From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com> |
| 127 | |
| 128 | Remove unused property and add pciecfg node. |
| 129 | |
| 130 | Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com> |
| 131 | --- |
| 132 | arch/arm/boot/dts/mt7629-rfb.dts | 3 ++- |
| 133 | arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++---------- |
| 134 | 2 files changed, 15 insertions(+), 11 deletions(-) |
| 135 | |
| 136 | --- a/arch/arm/boot/dts/mt7629-rfb.dts |
| 137 | +++ b/arch/arm/boot/dts/mt7629-rfb.dts |
| 138 | @@ -171,9 +171,10 @@ |
| 139 | }; |
| 140 | }; |
| 141 | |
| 142 | -&pcie { |
| 143 | +&pcie1 { |
| 144 | pinctrl-names = "default"; |
| 145 | pinctrl-0 = <&pcie_pins>; |
| 146 | + status = "okay"; |
| 147 | }; |
| 148 | |
| 149 | &pciephy1 { |
| 150 | --- a/arch/arm/boot/dts/mt7629.dtsi |
| 151 | +++ b/arch/arm/boot/dts/mt7629.dtsi |
| 152 | @@ -368,16 +368,21 @@ |
| 153 | #reset-cells = <1>; |
| 154 | }; |
| 155 | |
| 156 | - pcie: pcie@1a140000 { |
| 157 | + pciecfg: pciecfg@1a140000 { |
| 158 | + compatible = "mediatek,mt7629-pciecfg", "syscon"; |
| 159 | + reg = <0x1a140000 0x1000>; |
| 160 | + }; |
| 161 | + |
| 162 | + pcie1: pcie@1a145000 { |
| 163 | compatible = "mediatek,mt7629-pcie"; |
| 164 | device_type = "pci"; |
| 165 | - reg = <0x1a140000 0x1000>, |
| 166 | - <0x1a145000 0x1000>; |
| 167 | - reg-names = "subsys","port1"; |
| 168 | + reg = <0x1a145000 0x1000>; |
| 169 | + reg-names = "port1"; |
| 170 | + mediatek,pcie-cfg = <&pciecfg>; |
| 171 | #address-cells = <3>; |
| 172 | #size-cells = <2>; |
| 173 | - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, |
| 174 | - <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; |
| 175 | + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; |
| 176 | + interrupt-names = "pcie_irq"; |
| 177 | clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, |
| 178 | <&pciesys CLK_PCIE_P0_AHB_EN>, |
| 179 | <&pciesys CLK_PCIE_P1_AUX_EN>, |
| 180 | @@ -398,21 +403,19 @@ |
| 181 | power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; |
| 182 | bus-range = <0x00 0xff>; |
| 183 | ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; |
| 184 | + status = "disabled"; |
| 185 | |
| 186 | - pcie1: pcie@1,0 { |
| 187 | - device_type = "pci"; |
| 188 | + slot1: pcie@1,0 { |
| 189 | reg = <0x0800 0 0 0 0>; |
| 190 | #address-cells = <3>; |
| 191 | #size-cells = <2>; |
| 192 | #interrupt-cells = <1>; |
| 193 | ranges; |
| 194 | - num-lanes = <1>; |
| 195 | interrupt-map-mask = <0 0 0 7>; |
| 196 | interrupt-map = <0 0 0 1 &pcie_intc1 0>, |
| 197 | <0 0 0 2 &pcie_intc1 1>, |
| 198 | <0 0 0 3 &pcie_intc1 2>, |
| 199 | <0 0 0 4 &pcie_intc1 3>; |
| 200 | - |
| 201 | pcie_intc1: interrupt-controller { |
| 202 | interrupt-controller; |
| 203 | #address-cells = <0>; |