blob: 4f5d2c626dee2e4a1e39d4bea9484e7362852319 [file] [log] [blame]
developerb8853042023-02-17 11:50:45 +08001From d99756a5e6b4b3d1d520aba763fddeadff53a529 Mon Sep 17 00:00:00 2001
developer2458e702022-12-13 15:52:04 +08002From: Peter Chiu <chui-hao.chiu@mediatek.com>
developer3d5faf22022-11-29 18:07:22 +08003Date: Fri, 25 Nov 2022 14:37:58 +0800
developerb8853042023-02-17 11:50:45 +08004Subject: [PATCH 3005/3015] mt76: mt7915: wed: drop scatter and gather frame
developer3d5faf22022-11-29 18:07:22 +08005
6The scatter and gather frame may be incorrect because WED and WO may
7send frames to host driver interleaved.
8
developer780b9152022-12-15 14:09:45 +08009Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
developer3d5faf22022-11-29 18:07:22 +080010---
developer2458e702022-12-13 15:52:04 +080011 dma.c | 9 +++++++++
developer3d5faf22022-11-29 18:07:22 +080012 dma.h | 1 +
13 mt76.h | 1 +
developer2458e702022-12-13 15:52:04 +080014 3 files changed, 11 insertions(+)
developer3d5faf22022-11-29 18:07:22 +080015
16diff --git a/dma.c b/dma.c
developerf3f5d9b2023-02-07 15:24:34 +080017index b58579c5..86b0bf84 100644
developer3d5faf22022-11-29 18:07:22 +080018--- a/dma.c
19+++ b/dma.c
developerf3f5d9b2023-02-07 15:24:34 +080020@@ -449,6 +449,15 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
developer3d5faf22022-11-29 18:07:22 +080021
22 *drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A |
23 MT_DMA_CTL_DROP));
24+
developer2458e702022-12-13 15:52:04 +080025+ if (*more || (q->flags & MT_QFLAG_WED_FRAG)) {
26+ *drop = true;
27+
28+ if (!(*more) && FIELD_GET(MT_DMA_CTL_WO, desc->buf1))
29+ q->flags &= ~MT_QFLAG_WED_FRAG;
30+ else
31+ q->flags |= MT_QFLAG_WED_FRAG;
32+ }
developer3d5faf22022-11-29 18:07:22 +080033 }
34 } else {
35 buf = e->buf;
36diff --git a/dma.h b/dma.h
developerb9a96602023-01-10 19:53:25 +080037index 4b9bc7f4..ce8ac426 100644
developer3d5faf22022-11-29 18:07:22 +080038--- a/dma.h
39+++ b/dma.h
40@@ -19,6 +19,7 @@
41 #define MT_DMA_CTL_TO_HOST_A BIT(12)
42 #define MT_DMA_CTL_DROP BIT(14)
43 #define MT_DMA_CTL_TOKEN GENMASK(31, 16)
44+#define MT_DMA_CTL_WO BIT(8)
45
46 #define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
47 #define MT_DMA_PPE_ENTRY GENMASK(30, 16)
48diff --git a/mt76.h b/mt76.h
developerf3f5d9b2023-02-07 15:24:34 +080049index cb34391a..982d0bbf 100644
developer3d5faf22022-11-29 18:07:22 +080050--- a/mt76.h
51+++ b/mt76.h
52@@ -30,6 +30,7 @@
53 #define MT_QFLAG_WED_RING GENMASK(1, 0)
54 #define MT_QFLAG_WED_TYPE GENMASK(3, 2)
55 #define MT_QFLAG_WED BIT(4)
56+#define MT_QFLAG_WED_FRAG BIT(5)
57
58 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
59 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
60--
developer79a21a22023-01-09 13:57:39 +0800612.18.0
developer3d5faf22022-11-29 18:07:22 +080062