developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 1 | From a2479dc254ebe31c84fbcfda73f35e2321576494 Mon Sep 17 00:00:00 2001 |
| 2 | From: Xiangsheng Hou <xiangsheng.hou@mediatek.com> |
| 3 | Date: Tue, 19 Mar 2019 13:57:38 +0800 |
| 4 | Subject: [PATCH 1/6] mtd: mtk ecc: move mtk ecc header file to include/mtd |
| 5 | |
| 6 | Change-Id: I8dc1d30e21b40d68ef5efd9587012f82970156a5 |
| 7 | Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> |
| 8 | --- |
| 9 | drivers/mtd/nand/raw/mtk_ecc.c | 3 +-- |
| 10 | drivers/mtd/nand/raw/mtk_nand.c | 2 +- |
| 11 | {drivers/mtd/nand/raw => include/linux/mtd}/mtk_ecc.h | 0 |
| 12 | 3 files changed, 2 insertions(+), 3 deletions(-) |
| 13 | rename {drivers/mtd/nand/raw => include/linux/mtd}/mtk_ecc.h (100%) |
| 14 | |
| 15 | --- a/drivers/mtd/nand/raw/mtk_ecc.c |
| 16 | +++ b/drivers/mtd/nand/raw/mtk_ecc.c |
| 17 | @@ -15,8 +15,7 @@ |
| 18 | #include <linux/of.h> |
| 19 | #include <linux/of_platform.h> |
| 20 | #include <linux/mutex.h> |
| 21 | - |
| 22 | -#include "mtk_ecc.h" |
| 23 | +#include <linux/mtd/mtk_ecc.h> |
| 24 | |
| 25 | #define ECC_IDLE_MASK BIT(0) |
| 26 | #define ECC_IRQ_EN BIT(0) |
| 27 | --- a/drivers/mtd/nand/raw/mtk_nand.c |
| 28 | +++ b/drivers/mtd/nand/raw/mtk_nand.c |
| 29 | @@ -17,7 +17,7 @@ |
| 30 | #include <linux/iopoll.h> |
| 31 | #include <linux/of.h> |
| 32 | #include <linux/of_device.h> |
| 33 | -#include "mtk_ecc.h" |
| 34 | +#include <linux/mtd/mtk_ecc.h> |
| 35 | |
| 36 | /* NAND controller register definition */ |
| 37 | #define NFI_CNFG (0x00) |
| 38 | --- /dev/null |
| 39 | +++ b/include/linux/mtd/mtk_ecc.h |
| 40 | @@ -0,0 +1,49 @@ |
| 41 | +/* |
| 42 | + * MTK SDG1 ECC controller |
| 43 | + * |
| 44 | + * Copyright (c) 2016 Mediatek |
| 45 | + * Authors: Xiaolei Li <xiaolei.li@mediatek.com> |
| 46 | + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> |
| 47 | + * This program is free software; you can redistribute it and/or modify it |
| 48 | + * under the terms of the GNU General Public License version 2 as published |
| 49 | + * by the Free Software Foundation. |
| 50 | + */ |
| 51 | + |
| 52 | +#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ |
| 53 | +#define __DRIVERS_MTD_NAND_MTK_ECC_H__ |
| 54 | + |
| 55 | +#include <linux/types.h> |
| 56 | + |
| 57 | +enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; |
| 58 | +enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; |
| 59 | + |
| 60 | +struct device_node; |
| 61 | +struct mtk_ecc; |
| 62 | + |
| 63 | +struct mtk_ecc_stats { |
| 64 | + u32 corrected; |
| 65 | + u32 bitflips; |
| 66 | + u32 failed; |
| 67 | +}; |
| 68 | + |
| 69 | +struct mtk_ecc_config { |
| 70 | + enum mtk_ecc_operation op; |
| 71 | + enum mtk_ecc_mode mode; |
| 72 | + dma_addr_t addr; |
| 73 | + u32 strength; |
| 74 | + u32 sectors; |
| 75 | + u32 len; |
| 76 | +}; |
| 77 | + |
| 78 | +int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); |
| 79 | +void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); |
| 80 | +int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); |
| 81 | +int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); |
| 82 | +void mtk_ecc_disable(struct mtk_ecc *); |
| 83 | +void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); |
| 84 | +unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); |
| 85 | + |
| 86 | +struct mtk_ecc *of_mtk_ecc_get(struct device_node *); |
| 87 | +void mtk_ecc_release(struct mtk_ecc *); |
| 88 | + |
| 89 | +#endif |
| 90 | --- a/drivers/mtd/nand/raw/mtk_ecc.h |
| 91 | +++ /dev/null |
| 92 | @@ -1,47 +0,0 @@ |
| 93 | -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ |
| 94 | -/* |
| 95 | - * MTK SDG1 ECC controller |
| 96 | - * |
| 97 | - * Copyright (c) 2016 Mediatek |
| 98 | - * Authors: Xiaolei Li <xiaolei.li@mediatek.com> |
| 99 | - * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> |
| 100 | - */ |
| 101 | - |
| 102 | -#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ |
| 103 | -#define __DRIVERS_MTD_NAND_MTK_ECC_H__ |
| 104 | - |
| 105 | -#include <linux/types.h> |
| 106 | - |
| 107 | -enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; |
| 108 | -enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; |
| 109 | - |
| 110 | -struct device_node; |
| 111 | -struct mtk_ecc; |
| 112 | - |
| 113 | -struct mtk_ecc_stats { |
| 114 | - u32 corrected; |
| 115 | - u32 bitflips; |
| 116 | - u32 failed; |
| 117 | -}; |
| 118 | - |
| 119 | -struct mtk_ecc_config { |
| 120 | - enum mtk_ecc_operation op; |
| 121 | - enum mtk_ecc_mode mode; |
| 122 | - dma_addr_t addr; |
| 123 | - u32 strength; |
| 124 | - u32 sectors; |
| 125 | - u32 len; |
| 126 | -}; |
| 127 | - |
| 128 | -int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); |
| 129 | -void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); |
| 130 | -int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); |
| 131 | -int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); |
| 132 | -void mtk_ecc_disable(struct mtk_ecc *); |
| 133 | -void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); |
| 134 | -unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); |
| 135 | - |
| 136 | -struct mtk_ecc *of_mtk_ecc_get(struct device_node *); |
| 137 | -void mtk_ecc_release(struct mtk_ecc *); |
| 138 | - |
| 139 | -#endif |