blob: 52f3e798fcb0dd3345dd9695ecaeb7d11394e846 [file] [log] [blame]
developer9bc8ec12022-11-18 16:01:14 +08001From 2723beedc39c16ab67c7008779ebed4cf210e7ef Mon Sep 17 00:00:00 2001
developer9e5bcc52022-09-27 10:30:15 +08002From: Peter Chiu <chui-hao.chiu@mediatek.com>
3Date: Thu, 22 Sep 2022 09:54:53 +0800
developer2cbf2fb2022-11-16 12:20:48 +08004Subject: [PATCH 3008/3011] mt76: mt7915: update mt7916 trinfo when hw path
developerf1313102022-10-11 11:02:55 +08005 enable
developer9e5bcc52022-09-27 10:30:15 +08006
7---
8 mt7915/mt7915_debug.h | 10 ++++++++++
9 mt7915/mtk_debugfs.c | 16 +++++++++++++---
10 2 files changed, 23 insertions(+), 3 deletions(-)
11
12diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
developer9bc8ec12022-11-18 16:01:14 +080013index ecdc02a..0a1ee80 100644
developer9e5bcc52022-09-27 10:30:15 +080014--- a/mt7915/mt7915_debug.h
15+++ b/mt7915/mt7915_debug.h
16@@ -133,6 +133,8 @@ enum dbg_reg_rev {
17 DBG_MIB_M0ARNG0,
18 DBG_MIB_M0DR2,
19 DBG_MIB_M0DR13,
20+ DBG_WFDMA_WED_TX_CTRL,
21+ DBG_WFDMA_WED_RX_CTRL,
22 __MT_DBG_REG_REV_MAX,
23 };
24
25@@ -177,6 +179,8 @@ static const u32 mt7986_dbg_base[] = {
26
27 /* mt7915 regs with different base and offset */
28 static const struct __dbg_reg mt7915_dbg_reg[] = {
29+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
30+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
31 [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
32 [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
33 [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
34@@ -281,6 +285,8 @@ static const struct __dbg_reg mt7915_dbg_reg[] = {
35
36 /* mt7986/mt7916 regs with different base and offset */
37 static const struct __dbg_reg mt7916_dbg_reg[] = {
38+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
39+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
40 [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
41 [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
42 [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
43@@ -450,11 +456,15 @@ struct bin_debug_hdr {
44 #define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
45 #define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
46 #define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
47+#define MT_DBG_WFDMA_WED_TX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_TX_CTRL)
48+#define MT_DBG_WFDMA_WED_RX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_RX_CTRL)
49
50 #define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
51 #define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
52 #define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
53
54+#define MT_DBG_WFDMA_WED_TX_CTRL(n) (MT_DBG_WFDMA_WED_TX_CTRL_BASE + (0x10 * (n)))
55+#define MT_DBG_WFDMA_WED_RX_CTRL(n) (MT_DBG_WFDMA_WED_RX_CTRL_BASE + (0x10 * (n)))
56 /* WFDMA COMMON */
57 #define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
58 #define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
59diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
developer9bc8ec12022-11-18 16:01:14 +080060index facdd69..f25f9c6 100644
developer9e5bcc52022-09-27 10:30:15 +080061--- a/mt7915/mtk_debugfs.c
62+++ b/mt7915/mtk_debugfs.c
developer9bc8ec12022-11-18 16:01:14 +080063@@ -856,12 +856,22 @@ mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
developer9e5bcc52022-09-27 10:30:15 +080064 "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
65 dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
66 dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
67- dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
68- dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
69+
70+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) {
71+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
72+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
73+ } else {
74+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
75+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
76+ }
77+
78 dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
79 dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
80 dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
81- dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
82+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed))
83+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
84+ else
85+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
86 dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
87 dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
88 dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
89--
developerb81e95d2022-11-08 10:16:29 +0800902.18.0
developer9e5bcc52022-09-27 10:30:15 +080091