blob: c7c67073ba4a6682f18678f0c151e634eeded6f7 [file] [log] [blame]
developera20cdc22024-05-31 18:57:31 +08001From eebe902614c5e2759492afcd1f84665d241077cb Mon Sep 17 00:00:00 2001
developer1a173672023-12-21 14:49:33 +08002From: Rex Lu <rex.lu@mediatek.com>
3Date: Mon, 11 Dec 2023 19:21:16 +0800
developera20cdc22024-05-31 18:57:31 +08004Subject: [PATCH 3/4] wifi: mt76: mt7915: support backaward compatiable
developer1a173672023-12-21 14:49:33 +08005
6---
developera46f6132024-03-26 14:09:54 +08007 mt7915/mmio.c | 4 ++--
8 wed.c | 2 +-
9 2 files changed, 3 insertions(+), 3 deletions(-)
developer1a173672023-12-21 14:49:33 +080010
developera46f6132024-03-26 14:09:54 +080011diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developerdc9eeae2024-04-08 14:36:46 +080012index 142f308..11db3ed 100644
developera46f6132024-03-26 14:09:54 +080013--- a/mt7915/mmio.c
14+++ b/mt7915/mmio.c
15@@ -697,7 +697,7 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
16 MT_RXQ_WED_RING_BASE;
17 wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) +
18 MT_WPDMA_GLO_CFG;
19- wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) +
20+ wed->wlan.wpdma_rx[0] = pci_resource_start(pci_dev, 0) +
21 MT_RXQ_WED_DATA_RING_BASE;
22 } else {
23 struct platform_device *plat_dev = pdev_ptr;
24@@ -717,7 +717,7 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
25 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE;
26 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE;
27 wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG;
28- wed->wlan.wpdma_rx = res->start + MT_RXQ_WED_DATA_RING_BASE;
29+ wed->wlan.wpdma_rx[0] = res->start + MT_RXQ_WED_DATA_RING_BASE;
30 }
31
32 wed->wlan.nbuf = is_mt7915(&dev->mt76) ?
developer753619c2024-02-22 13:42:45 +080033diff --git a/wed.c b/wed.c
developerdc9eeae2024-04-08 14:36:46 +080034index 5ed681e..652f59e 100644
developer753619c2024-02-22 13:42:45 +080035--- a/wed.c
36+++ b/wed.c
developera46f6132024-03-26 14:09:54 +080037@@ -175,7 +175,7 @@ int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset)
developer1a173672023-12-21 14:49:33 +080038 break;
developera46f6132024-03-26 14:09:54 +080039 case MT76_WED_RRO_Q_MSDU_PG:
40 q->flags &= ~MT_QFLAG_WED;
developer753619c2024-02-22 13:42:45 +080041- __mt76_dma_queue_reset(dev, q);
developera46f6132024-03-26 14:09:54 +080042+ __mt76_dma_queue_reset(dev, q, false);
43 mtk_wed_device_msdu_pg_rx_ring_setup(q->wed, ring, q->regs);
44 q->head = q->ndesc - 1;
45 q->queued = q->head;
developer1a173672023-12-21 14:49:33 +080046--
472.18.0
48