developer | a20cdc2 | 2024-05-31 18:57:31 +0800 | [diff] [blame] | 1 | From 1de98ecb4505e3f99759caf4e9df9e263dfa403a Mon Sep 17 00:00:00 2001 |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 2 | From: "Allen.Ye" <allen.ye@mediatek.com> |
| 3 | Date: Fri, 11 Aug 2023 16:46:53 +0800 |
developer | a20cdc2 | 2024-05-31 18:57:31 +0800 | [diff] [blame] | 4 | Subject: [PATCH 1033/1051] wifi: mt76: mt7915: Disable RegDB when enable |
developer | 753619c | 2024-02-22 13:42:45 +0800 | [diff] [blame] | 5 | single sku |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 6 | |
| 7 | --- |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 8 | mt7915/debugfs.c | 49 +++++++++++++++++++++++++++++++++++++++++++----- |
developer | 70180b0 | 2023-11-14 17:01:47 +0800 | [diff] [blame] | 9 | mt7915/init.c | 11 +++++++++-- |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 10 | mt7915/regs.h | 8 ++++---- |
developer | 1a17367 | 2023-12-21 14:49:33 +0800 | [diff] [blame] | 11 | 3 files changed, 57 insertions(+), 11 deletions(-) |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 12 | |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 13 | diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c |
developer | dc9eeae | 2024-04-08 14:36:46 +0800 | [diff] [blame] | 14 | index 24e88f7..502b493 100644 |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 15 | --- a/mt7915/debugfs.c |
| 16 | +++ b/mt7915/debugfs.c |
developer | dc9eeae | 2024-04-08 14:36:46 +0800 | [diff] [blame] | 17 | @@ -1020,10 +1020,16 @@ mt7915_rate_txpower_get(struct file *file, char __user *user_buf, |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 18 | { |
| 19 | struct mt7915_phy *phy = file->private_data; |
| 20 | struct mt7915_dev *dev = phy->dev; |
| 21 | + struct ieee80211_channel *chan = phy->mt76->chandef.chan; |
| 22 | + struct ieee80211_supported_band sband; |
| 23 | s8 txpwr[MT7915_SKU_RATE_NUM]; |
| 24 | - static const size_t sz = 2048; |
| 25 | + static const size_t sz = 4096; |
| 26 | u8 band = phy->mt76->band_idx; |
| 27 | int i, offs = 0, len = 0; |
| 28 | + u32 target_power = 0; |
| 29 | + int n_chains = hweight16(phy->mt76->chainmask); |
| 30 | + int nss_delta = mt76_tx_power_nss_delta(n_chains); |
| 31 | + int pwr_delta; |
| 32 | ssize_t ret; |
| 33 | char *buf; |
| 34 | u32 reg; |
developer | dc9eeae | 2024-04-08 14:36:46 +0800 | [diff] [blame] | 35 | @@ -1082,11 +1088,38 @@ mt7915_rate_txpower_get(struct file *file, char __user *user_buf, |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 36 | len += scnprintf(buf + len, sz - len, "BW160/"); |
| 37 | mt7915_txpower_puts(HE_RU2x996, 17); |
| 38 | |
| 39 | - reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_TPC_CTRL_STAT(band) : |
| 40 | - MT_WF_PHY_TPC_CTRL_STAT_MT7916(band); |
| 41 | + reg = is_mt7915(&dev->mt76) ? MT_WF_IRPI_TPC_CTRL_STAT(band) : |
| 42 | + MT_WF_IRPI_TPC_CTRL_STAT_MT7916(band); |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 43 | |
| 44 | - len += scnprintf(buf + len, sz - len, "\nTx power (bbp) : %6ld\n", |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 45 | - mt76_get_field(dev, reg, MT_WF_PHY_TPC_POWER)); |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 46 | + len += scnprintf(buf + len, sz - len, "\nTx power (bbp) : %6ld [0.5 dBm]\n", |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 47 | + mt76_get_field(dev, reg, MT_WF_IRPI_TPC_POWER)); |
| 48 | + |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 49 | + len += scnprintf(buf + len, sz - len, "RegDB maximum power:\t%d [dBm]\n", |
| 50 | + chan->max_reg_power); |
| 51 | + |
| 52 | + if (chan->band == NL80211_BAND_2GHZ) |
| 53 | + sband = phy->mt76->sband_2g.sband; |
| 54 | + else if (chan->band == NL80211_BAND_5GHZ) |
| 55 | + sband = phy->mt76->sband_5g.sband; |
| 56 | + else if (chan->band == NL80211_BAND_6GHZ) |
| 57 | + sband = phy->mt76->sband_6g.sband; |
| 58 | + |
| 59 | + pwr_delta = mt7915_eeprom_get_power_delta(dev, sband.band); |
| 60 | + |
| 61 | + for (i = 0; i < n_chains; i++) { |
| 62 | + u32 val; |
| 63 | + |
| 64 | + val = mt7915_eeprom_get_target_power(dev, chan, i); |
| 65 | + target_power = max(target_power, val); |
| 66 | + } |
| 67 | + |
| 68 | + target_power += pwr_delta + nss_delta; |
| 69 | + target_power = DIV_ROUND_UP(target_power, 2); |
| 70 | + len += scnprintf(buf + len, sz - len, "eeprom maximum power:\t%d [dBm]\n", |
| 71 | + target_power); |
| 72 | + |
| 73 | + len += scnprintf(buf + len, sz - len, "nss_delta:\t%d [0.5 dBm]\n", |
| 74 | + nss_delta); |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 75 | |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 76 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| 77 | |
developer | dc9eeae | 2024-04-08 14:36:46 +0800 | [diff] [blame] | 78 | @@ -1263,6 +1296,8 @@ static int |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 79 | mt7915_txpower_info_show(struct seq_file *file, void *data) |
| 80 | { |
| 81 | struct mt7915_phy *phy = file->private; |
| 82 | + struct mt76_phy *mphy = phy->mt76; |
| 83 | + struct mt76_dev *dev = mphy->dev; |
| 84 | struct { |
| 85 | u8 category; |
| 86 | u8 rsv1; |
developer | dc9eeae | 2024-04-08 14:36:46 +0800 | [diff] [blame] | 87 | @@ -1304,6 +1339,7 @@ mt7915_txpower_info_show(struct seq_file *file, void *data) |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 88 | s8 mu_tx_power_manual; |
| 89 | u8 rsv3; |
| 90 | } __packed basic_info = {}; |
| 91 | + struct device_node *np; |
| 92 | int ret; |
| 93 | |
| 94 | ret = mt7915_mcu_get_txpower_sku(phy, (s8 *)&basic_info, sizeof(basic_info), |
developer | dc9eeae | 2024-04-08 14:36:46 +0800 | [diff] [blame] | 95 | @@ -1338,6 +1374,9 @@ mt7915_txpower_info_show(struct seq_file *file, void *data) |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 96 | seq_printf(file, " Theraml Compensation Value: %d\n", |
| 97 | basic_info.thermal_compensate_value); |
| 98 | |
| 99 | + np = mt76_find_power_limits_node(dev); |
| 100 | + seq_printf(file, " RegDB: %s\n", !np ? "enable" : "disable"); |
| 101 | + |
| 102 | out: |
| 103 | return ret; |
| 104 | } |
| 105 | diff --git a/mt7915/init.c b/mt7915/init.c |
developer | a20cdc2 | 2024-05-31 18:57:31 +0800 | [diff] [blame] | 106 | index 20d6efd..4fa48fb 100644 |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 107 | --- a/mt7915/init.c |
| 108 | +++ b/mt7915/init.c |
developer | 1a17367 | 2023-12-21 14:49:33 +0800 | [diff] [blame] | 109 | @@ -283,9 +283,11 @@ static void __mt7915_init_txpower(struct mt7915_phy *phy, |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 110 | int nss_delta = mt76_tx_power_nss_delta(n_chains); |
| 111 | int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); |
| 112 | struct mt76_power_limits limits; |
| 113 | + struct device_node *np; |
| 114 | |
developer | 70180b0 | 2023-11-14 17:01:47 +0800 | [diff] [blame] | 115 | phy->sku_limit_en = true; |
| 116 | phy->sku_path_en = true; |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 117 | + np = mt76_find_power_limits_node(&dev->mt76); |
| 118 | for (i = 0; i < sband->n_channels; i++) { |
| 119 | struct ieee80211_channel *chan = &sband->channels[i]; |
| 120 | u32 target_power = 0; |
developer | 1a17367 | 2023-12-21 14:49:33 +0800 | [diff] [blame] | 121 | @@ -309,8 +311,13 @@ static void __mt7915_init_txpower(struct mt7915_phy *phy, |
developer | 70180b0 | 2023-11-14 17:01:47 +0800 | [diff] [blame] | 122 | |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 123 | target_power += nss_delta; |
| 124 | target_power = DIV_ROUND_UP(target_power, 2); |
| 125 | - chan->max_power = min_t(int, chan->max_reg_power, |
developer | 70180b0 | 2023-11-14 17:01:47 +0800 | [diff] [blame] | 126 | - target_power); |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 127 | + |
| 128 | + /* can NOT find country node in dts */ |
| 129 | + if (!np) |
| 130 | + chan->max_power = min_t(int, chan->max_reg_power, |
developer | 70180b0 | 2023-11-14 17:01:47 +0800 | [diff] [blame] | 131 | + target_power); |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 132 | + else |
| 133 | + chan->max_power = target_power; |
| 134 | chan->orig_mpwr = target_power; |
| 135 | } |
| 136 | } |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 137 | diff --git a/mt7915/regs.h b/mt7915/regs.h |
developer | dc9eeae | 2024-04-08 14:36:46 +0800 | [diff] [blame] | 138 | index 4d05e39..ca355d1 100644 |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 139 | --- a/mt7915/regs.h |
| 140 | +++ b/mt7915/regs.h |
developer | a46f613 | 2024-03-26 14:09:54 +0800 | [diff] [blame] | 141 | @@ -1215,6 +1215,10 @@ enum offs_rev { |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 142 | #define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16)) |
| 143 | #define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16)) |
| 144 | |
| 145 | +#define MT_WF_IRPI_TPC_CTRL_STAT(_phy) MT_WF_IRPI(0xc794 + ((_phy) << 16)) |
| 146 | +#define MT_WF_IRPI_TPC_CTRL_STAT_MT7916(_phy) MT_WF_IRPI(0xc794 + ((_phy) << 20)) |
| 147 | +#define MT_WF_IRPI_TPC_POWER GENMASK(31, 24) |
| 148 | + |
| 149 | #define MT_WF_IPI_RESET 0x831a3008 |
| 150 | |
| 151 | /* PHY */ |
developer | a46f613 | 2024-03-26 14:09:54 +0800 | [diff] [blame] | 152 | @@ -1231,10 +1235,6 @@ enum offs_rev { |
developer | bd9fa1e | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 153 | #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) |
| 154 | #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) |
| 155 | |
| 156 | -#define MT_WF_PHY_TPC_CTRL_STAT(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 16)) |
| 157 | -#define MT_WF_PHY_TPC_CTRL_STAT_MT7916(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 20)) |
| 158 | -#define MT_WF_PHY_TPC_POWER GENMASK(15, 8) |
| 159 | - |
| 160 | #define MT_MCU_WM_CIRQ_BASE 0x89010000 |
| 161 | #define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs)) |
| 162 | #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80) |
developer | dff5277 | 2023-08-18 17:03:34 +0800 | [diff] [blame] | 163 | -- |
| 164 | 2.18.0 |
| 165 | |