blob: 3cb1dab69f0aa1541bf0228f67a70cb508c4651d [file] [log] [blame]
developerec4ebe42022-04-12 11:17:45 +08001From 004eb24e939b5b31f828333f37fb5cb2a877d6f2 Mon Sep 17 00:00:00 2001
2From: Kristian Evensen <kristian.evensen@gmail.com>
3Date: Sun, 17 Jun 2018 14:41:47 +0200
4Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
5
6---
7 arch/arm/boot/dts/Makefile | 1 +
8 .../dts/mt7623a-unielec-u7623-02-emmc-512m.dts | 18 +
9 .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi | 366 +++++++++++++++++++++
10 3 files changed, 385 insertions(+)
11 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
12 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
13
14--- a/arch/arm/boot/dts/Makefile
15+++ b/arch/arm/boot/dts/Makefile
16@@ -1272,6 +1272,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
17 mt7623a-rfb-nand.dtb \
18 mt7623n-rfb-emmc.dtb \
19 mt7623n-bananapi-bpi-r2.dtb \
20+ mt7623a-unielec-u7623-02-emmc-512m.dtb \
21 mt7629-rfb.dtb \
22 mt8127-moose.dtb \
23 mt8135-evbp1.dtb
24--- /dev/null
25+++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
26@@ -0,0 +1,18 @@
27+/*
28+ * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
29+ *
30+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
31+ */
32+
33+/dts-v1/;
34+#include "mt7623a-unielec-u7623-02-emmc.dtsi"
35+
36+/ {
37+ model = "UniElec U7623-02 eMMC (512M RAM)";
38+ compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
39+
40+ memory@80000000 {
41+ device_type = "memory";
42+ reg = <0 0x80000000 0 0x20000000>;
43+ };
44+};
45--- /dev/null
46+++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
47@@ -0,0 +1,340 @@
48+/*
49+ * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
50+ *
51+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
52+ */
53+
54+#include <dt-bindings/input/input.h>
55+#include "mt7623.dtsi"
56+#include "mt6323.dtsi"
57+
58+/ {
59+ compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
60+
61+ aliases {
62+ serial2 = &uart2;
63+ };
64+
65+ chosen {
66+ bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs console=ttyS0,115200 blkdevparts=mmcblk0:3M@6M(recovery),256M@9M(root)";
67+ stdout-path = "serial2:115200n8";
68+ };
69+
70+ cpus {
71+ cpu@0 {
72+ proc-supply = <&mt6323_vproc_reg>;
73+ };
74+
75+ cpu@1 {
76+ proc-supply = <&mt6323_vproc_reg>;
77+ };
78+
79+ cpu@2 {
80+ proc-supply = <&mt6323_vproc_reg>;
81+ };
82+
83+ cpu@3 {
84+ proc-supply = <&mt6323_vproc_reg>;
85+ };
86+ };
87+
88+ reg_1p8v: regulator-1p8v {
89+ compatible = "regulator-fixed";
90+ regulator-name = "fixed-1.8V";
91+ regulator-min-microvolt = <1800000>;
92+ regulator-max-microvolt = <1800000>;
93+ regulator-boot-on;
94+ regulator-always-on;
95+ };
96+
97+ reg_3p3v: regulator-3p3v {
98+ compatible = "regulator-fixed";
99+ regulator-name = "fixed-3.3V";
100+ regulator-min-microvolt = <3300000>;
101+ regulator-max-microvolt = <3300000>;
102+ regulator-boot-on;
103+ regulator-always-on;
104+ };
105+
106+ reg_5v: regulator-5v {
107+ compatible = "regulator-fixed";
108+ regulator-name = "fixed-5V";
109+ regulator-min-microvolt = <5000000>;
110+ regulator-max-microvolt = <5000000>;
111+ regulator-boot-on;
112+ regulator-always-on;
113+ };
114+
115+ gpio-keys {
116+ compatible = "gpio-keys";
117+ pinctrl-names = "default";
118+ pinctrl-0 = <&key_pins_a>;
119+
120+ factory {
121+ label = "factory";
122+ linux,code = <KEY_RESTART>;
123+ gpios = <&pio 256 GPIO_ACTIVE_LOW>;
124+ };
125+ };
126+
127+ leds {
128+ compatible = "gpio-leds";
129+ pinctrl-names = "default";
130+ pinctrl-0 = <&led_pins_unielec>;
131+
132+ led3 {
133+ label = "u7623-01:green:led3";
134+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
135+ };
136+
137+ led4 {
138+ label = "u7623-01:green:led4";
139+ gpios = <&pio 15 GPIO_ACTIVE_LOW>;
140+ };
141+ };
142+};
143+
144+&crypto {
145+ status = "okay";
146+};
147+
148+&eth {
149+ status = "okay";
150+
151+ gmac0: mac@0 {
152+ compatible = "mediatek,eth-mac";
153+ reg = <0>;
154+ phy-mode = "trgmii";
155+
156+ fixed-link {
157+ speed = <1000>;
158+ full-duplex;
159+ pause;
160+ };
161+ };
162+
163+ mdio: mdio-bus {
164+ #address-cells = <1>;
165+ #size-cells = <0>;
166+
167+ mt7530: switch@0 {
168+ compatible = "mediatek,mt7530";
169+ };
170+ };
171+};
172+
173+&mt7530 {
174+ compatible = "mediatek,mt7530";
175+ #address-cells = <1>;
176+ #size-cells = <0>;
177+ reg = <0>;
178+ pinctrl-names = "default";
179+ mediatek,mcm;
180+ resets = <&ethsys 2>;
181+ reset-names = "mcm";
182+ core-supply = <&mt6323_vpa_reg>;
183+ io-supply = <&mt6323_vemc3v3_reg>;
184+
185+ dsa,mii-bus = <&mdio>;
186+
187+ ports {
188+ #address-cells = <1>;
189+ #size-cells = <0>;
190+ reg = <0>;
191+
192+ port@0 {
193+ reg = <0>;
194+ label = "lan0";
195+ cpu = <&cpu_port0>;
196+ };
197+
198+ port@1 {
199+ reg = <1>;
200+ label = "lan1";
201+ cpu = <&cpu_port0>;
202+ };
203+
204+ port@2 {
205+ reg = <2>;
206+ label = "lan2";
207+ cpu = <&cpu_port0>;
208+ };
209+
210+ port@3 {
211+ reg = <3>;
212+ label = "lan3";
213+ cpu = <&cpu_port0>;
214+ };
215+
216+ port@4 {
217+ reg = <4>;
218+ label = "wan";
219+ cpu = <&cpu_port0>;
220+ };
221+
222+ cpu_port0: port@6 {
223+ reg = <6>;
224+ label = "cpu";
225+ ethernet = <&gmac0>;
226+ phy-mode = "trgmii";
227+
228+ fixed-link {
229+ speed = <1000>;
230+ full-duplex;
231+ };
232+ };
233+ };
234+};
235+
236+&mmc0 {
237+ pinctrl-names = "default", "state_uhs";
238+ pinctrl-0 = <&mmc0_pins_default>;
239+ pinctrl-1 = <&mmc0_pins_uhs>;
240+ status = "okay";
241+ bus-width = <8>;
242+ max-frequency = <50000000>;
243+ cap-mmc-highspeed;
244+ vmmc-supply = <&reg_3p3v>;
245+ vqmmc-supply = <&reg_1p8v>;
246+ non-removable;
247+};
248+
249+&pio {
250+ key_pins_a: keys-alt {
251+ pins-keys {
252+ pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
253+ <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
254+ input-enable;
255+ };
256+ };
257+
258+ led_pins_unielec: leds-unielec {
259+ pins-leds {
260+ pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
261+ <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
262+ };
263+ };
264+
265+ mmc0_pins_default: mmc0default {
266+ pins_cmd_dat {
267+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
268+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
269+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
270+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
271+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
272+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
273+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
274+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
275+ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
276+ input-enable;
277+ bias-pull-up;
278+ };
279+
280+ pins_clk {
281+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
282+ bias-pull-down;
283+ };
284+
285+ pins_rst {
286+ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
287+ bias-pull-up;
288+ };
289+ };
290+
291+ mmc0_pins_uhs: mmc0 {
292+ pins_cmd_dat {
293+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
294+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
295+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
296+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
297+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
298+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
299+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
300+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
301+ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
302+ input-enable;
303+ drive-strength = <MTK_DRIVE_2mA>;
304+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
305+ };
306+
307+ pins_clk {
308+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
309+ drive-strength = <MTK_DRIVE_2mA>;
310+ bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
311+ };
312+
313+ pins_rst {
314+ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
315+ bias-pull-up;
316+ };
317+ };
318+
319+ pcie_default: pcie_pin_default {
320+ pins_cmd_dat {
321+ pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
322+ <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
323+ bias-disable;
324+ };
325+ };
326+};
327+
328+&pwm {
329+ pinctrl-names = "default";
330+ pinctrl-0 = <&pwm_pins_a>;
331+ status = "okay";
332+};
333+
334+&pwrap {
335+ mt6323 {
336+ mt6323led: led {
337+ compatible = "mediatek,mt6323-led";
338+ #address-cells = <1>;
339+ #size-cells = <0>;
340+
341+ led@0 {
342+ reg = <0>;
343+ label = "led0";
344+ };
345+ };
346+ };
347+};
348+
349+&uart2 {
350+ pinctrl-names = "default";
351+ pinctrl-0 = <&uart2_pins_b>;
352+ status = "okay";
353+};
354+
355+&usb1 {
356+ vusb33-supply = <&reg_3p3v>;
357+ vbus-supply = <&reg_3p3v>;
358+ status = "okay";
359+};
360+
361+&u3phy1 {
362+ status = "okay";
363+};
364+
365+&u3phy2 {
366+ status = "okay";
367+ mediatek,phy-switch = <&hifsys>;
368+};
369+
370+&pcie {
371+ pinctrl-names = "default";
372+ pinctrl-0 = <&pcie_default>;
373+ status = "okay";
374+
375+ pcie@1,0 {
376+ status = "okay";
377+ };
378+
379+ pcie@2,0 {
380+ status = "okay";
381+ };
382+};
383+
384+&pcie1_phy {
385+ status = "okay";
386+};
387+