blob: c12e8d888fdf304df0fae14f79b5ca6aac3e8c40 [file] [log] [blame]
developer880c8292022-07-11 11:52:59 +08001/*
2 * switch_ioctl.h: switch(ioctl) set API
3 */
4
5#ifndef SWITCH_IOCTL_H
6#define SWITCH_IOCTL_H
7
8#define ETH_DEVNAME "eth1"
9#define BR_DEVNAME "brlan0"
10
11#define RAETH_MII_READ 0x89F3
12#define RAETH_MII_WRITE 0x89F4
13#define RAETH_ESW_PHY_DUMP 0x89F7
14
15struct esw_reg {
16 unsigned int off;
17 unsigned int val;
18};
19
20struct ra_mii_ioctl_data {
21 __u32 phy_id;
22 __u32 reg_num;
23 __u32 val_in;
24 __u32 val_out;
25 __u32 port_num;
26 __u32 dev_addr;
27 __u32 reg_addr;
28};
29
30struct ra_switch_ioctl_data {
31 unsigned int cmd;
32 unsigned int on_off;
33 unsigned int port;
34 unsigned int bw;
35 unsigned int vid;
36 unsigned int fid;
37 unsigned int port_map;
38 unsigned int rx_port_map;
39 unsigned int tx_port_map;
40 unsigned int igmp_query_interval;
41 unsigned int reg_addr;
42 unsigned int reg_val;
43 unsigned int mode;
44 unsigned int qos_queue_num;
45 unsigned int qos_type;
46 unsigned int qos_pri;
47 unsigned int qos_dscp;
48 unsigned int qos_table_idx;
49 unsigned int qos_weight;
50 unsigned char mac[6];
51};
52
53extern int chip_name;
54
55void switch_ioctl_init(void);
56void switch_ioctl_fini(void);
57int reg_read_ioctl(int offset, int *value);
58int reg_write_ioctl(int offset, int value);
59int phy_dump_ioctl(int phy_addr);
60int mii_mgr_cl22_read_ioctl(unsigned int port_num, unsigned int reg, int *value);
61int mii_mgr_cl22_write_ioctl(unsigned int port_num, unsigned int reg,
62 unsigned int value);
63int mii_mgr_cl45_read_ioctl(int port_num, int dev, int reg, int *value);
64int mii_mgr_cl45_write_ioctl(int port_num, int dev, int reg, int value);
65#endif