| developer | e35b8e4 | 2023-10-16 11:04:00 +0800 | [diff] [blame] | 1 | From 531d586b936634fad23651d18d2bbc832692c520 Mon Sep 17 00:00:00 2001 |
| 2 | From: "sujuan.chen" <sujuan.chen@mediatek.com> |
| 3 | Date: Fri, 11 Aug 2023 18:26:39 +0800 |
| 4 | Subject: [PATCH 74/98] wifi: mt76: mt7996: add rro timeout setting |
| 5 | |
| 6 | Signed-off-by: sujuan.chen <sujuan.chen@mediatek.com> |
| 7 | --- |
| 8 | mt7996/init.c | 5 +++++ |
| 9 | mt7996/mcu.c | 11 ++++++++++- |
| 10 | mt7996/mt7996.h | 2 +- |
| 11 | mt7996/regs.h | 2 ++ |
| 12 | 4 files changed, 18 insertions(+), 2 deletions(-) |
| 13 | |
| 14 | diff --git a/mt7996/init.c b/mt7996/init.c |
| 15 | index 1ece390..51649dd 100644 |
| 16 | --- a/mt7996/init.c |
| 17 | +++ b/mt7996/init.c |
| 18 | @@ -506,6 +506,11 @@ void mt7996_mac_init(struct mt7996_dev *dev) |
| 19 | /* rro module init */ |
| 20 | mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); |
| 21 | if (dev->has_rro) { |
| 22 | + u16 timeout; |
| 23 | + |
| 24 | + timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_VER1 ? 512 : 128; |
| 25 | + |
| 26 | + mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); |
| 27 | mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1); |
| 28 | mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0); |
| 29 | } else { |
| 30 | diff --git a/mt7996/mcu.c b/mt7996/mcu.c |
| 31 | index ce38a5e..bebd020 100644 |
| 32 | --- a/mt7996/mcu.c |
| 33 | +++ b/mt7996/mcu.c |
| 34 | @@ -4626,7 +4626,7 @@ int mt7996_mcu_trigger_assert(struct mt7996_dev *dev) |
| 35 | &req, sizeof(req), false); |
| 36 | } |
| 37 | |
| 38 | -int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val) |
| 39 | +int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val) |
| 40 | { |
| 41 | struct { |
| 42 | u8 __rsv1[4]; |
| 43 | @@ -4648,6 +4648,11 @@ int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val) |
| 44 | u8 path; |
| 45 | u8 __rsv2[3]; |
| 46 | } __packed txfree_path; |
| 47 | + struct { |
| 48 | + u16 flush_one; |
| 49 | + u16 flush_all; |
| 50 | + u8 __rsv2[4]; |
| 51 | + } __packed timeout; |
| 52 | }; |
| 53 | } __packed req = { |
| 54 | .tag = cpu_to_le16(tag), |
| 55 | @@ -4664,6 +4669,10 @@ int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val) |
| 56 | case UNI_RRO_SET_TXFREE_PATH: |
| 57 | req.txfree_path.path = val; |
| 58 | break; |
| 59 | + case UNI_RRO_SET_FLUSH_TIMEOUT: |
| 60 | + req.timeout.flush_one = val; |
| 61 | + req.timeout.flush_all = val * 2; |
| 62 | + break; |
| 63 | default: |
| 64 | return -EINVAL; |
| 65 | } |
| 66 | diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h |
| 67 | index af67c59..06e00f4 100644 |
| 68 | --- a/mt7996/mt7996.h |
| 69 | +++ b/mt7996/mt7996.h |
| 70 | @@ -676,7 +676,7 @@ int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx, |
| 71 | u16 rate_idx, bool beacon); |
| 72 | int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); |
| 73 | int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); |
| 74 | -int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val); |
| 75 | +int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val); |
| 76 | int mt7996_mcu_reset_rro_sessions(struct mt7996_dev *dev, u16 seid); |
| 77 | int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); |
| 78 | int mt7996_mcu_red_config(struct mt7996_dev *dev, bool enable); |
| 79 | diff --git a/mt7996/regs.h b/mt7996/regs.h |
| 80 | index a0b5270..77a2f9d 100644 |
| 81 | --- a/mt7996/regs.h |
| 82 | +++ b/mt7996/regs.h |
| 83 | @@ -667,6 +667,8 @@ enum offs_rev { |
| 84 | #define MT_PAD_GPIO_ADIE_NUM_7992 BIT(15) |
| 85 | |
| 86 | #define MT_HW_REV 0x70010204 |
| 87 | +#define MT_HW_VER1 0x8a00 |
| 88 | + |
| 89 | #define MT_WF_SUBSYS_RST 0x70028600 |
| 90 | |
| 91 | /* PCIE MAC */ |
| 92 | -- |
| 93 | 2.18.0 |
| 94 | |