blob: 293bb810bf1a3a8618a1cf3a1025261c630727cd [file] [log] [blame]
developer79a21a22023-01-09 13:57:39 +08001From f5d57a09b9aaa434403288bb2c07132120788891 Mon Sep 17 00:00:00 2001
developer2458e702022-12-13 15:52:04 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Fri, 2 Dec 2022 17:17:06 +0800
developer79a21a22023-01-09 13:57:39 +08004Subject: [PATCH 3010/3013] mt76: mt7915: wed: add mt7916 2 pcie support when
developer2458e702022-12-13 15:52:04 +08005 wed on
6
7It should use bit 23 in interrupt mask for wfdma band1 data
8for 2 pcie mt7916, and use bit 19 for band1 data for 1 pcie.
9
10Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
11---
12 mt7915/dma.c | 8 ++++++--
developer780b9152022-12-15 14:09:45 +080013 mt7915/mcu.c | 3 ++-
developer2458e702022-12-13 15:52:04 +080014 mt7915/mmio.c | 10 +++++-----
developer780b9152022-12-15 14:09:45 +080015 3 files changed, 13 insertions(+), 8 deletions(-)
developer2458e702022-12-13 15:52:04 +080016
17diff --git a/mt7915/dma.c b/mt7915/dma.c
developer2aa1e642022-12-19 11:33:22 +080018index 1ae6c33..3626008 100644
developer2458e702022-12-13 15:52:04 +080019--- a/mt7915/dma.c
20+++ b/mt7915/dma.c
21@@ -88,8 +88,12 @@ static void mt7915_dma_config(struct mt7915_dev *dev)
22 MT7916_RXQ_BAND0);
23 RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MT7916,
24 MT7916_RXQ_MCU_WA);
25- RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916,
26- MT7916_RXQ_BAND1);
27+ if (dev->hif2)
28+ RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916,
29+ MT7916_RXQ_BAND1);
30+ else
31+ RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916,
32+ MT7916_RXQ_BAND1);
33 RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MAIN_MT7916,
34 MT7916_RXQ_MCU_WA_MAIN);
35 TXQ_CONFIG(0, WFDMA0, MT_INT_WED_TX_DONE_BAND0,
36diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer79a21a22023-01-09 13:57:39 +080037index 15f20ad..a268734 100644
developer2458e702022-12-13 15:52:04 +080038--- a/mt7915/mcu.c
39+++ b/mt7915/mcu.c
developer2aa1e642022-12-19 11:33:22 +080040@@ -2365,7 +2365,8 @@ int mt7915_mcu_init_firmware(struct mt7915_dev *dev)
developer2458e702022-12-13 15:52:04 +080041 return ret;
42
developer780b9152022-12-15 14:09:45 +080043 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
developer2458e702022-12-13 15:52:04 +080044- if (is_mt7915(&dev->mt76))
developer780b9152022-12-15 14:09:45 +080045+ if (is_mt7915(&dev->mt76) ||
46+ !mtk_wed_get_rx_capa(&dev->mt76.mmio.wed))
47 ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY),
48 0, 0, 0);
developer2458e702022-12-13 15:52:04 +080049 else
50diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer2aa1e642022-12-19 11:33:22 +080051index b29fe7a..4bc8e8c 100644
developer2458e702022-12-13 15:52:04 +080052--- a/mt7915/mmio.c
53+++ b/mt7915/mmio.c
developer2aa1e642022-12-19 11:33:22 +080054@@ -966,13 +966,13 @@ irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
developer2458e702022-12-13 15:52:04 +080055 struct mt7915_dev *dev = dev_instance;
56 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
57
58- if (mtk_wed_device_active(wed)) {
59+ if (mtk_wed_device_active(wed))
60 mtk_wed_device_irq_set_mask(wed, 0);
61- } else {
62+ else
63 mt76_wr(dev, MT_INT_MASK_CSR, 0);
64- if (dev->hif2)
65- mt76_wr(dev, MT_INT1_MASK_CSR, 0);
66- }
67+
68+ if (dev->hif2)
69+ mt76_wr(dev, MT_INT1_MASK_CSR, 0);
70
71 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
72 return IRQ_NONE;
73--
developer79a21a22023-01-09 13:57:39 +0800742.18.0
developer2458e702022-12-13 15:52:04 +080075