blob: 2aa0131340b7dda35f9acd385f756e4fdda8e3ce [file] [log] [blame]
developer69bcd592024-03-25 14:26:39 +08001From 7f1319357888271ea4aeeda81723b19a8f5ef2c0 Mon Sep 17 00:00:00 2001
developerc89c5472022-08-02 13:00:04 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developer740bee82023-10-16 10:58:43 +08003Date: Mon, 18 Sep 2023 11:05:45 +0800
developer69bcd592024-03-25 14:26:39 +08004Subject: [PATCH] add-wed-ser-support
developerc89c5472022-08-02 13:00:04 +08005
developerc89c5472022-08-02 13:00:04 +08006---
developerd5169582023-02-17 10:32:38 +08007 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 +
developer69bcd592024-03-25 14:26:39 +08008 drivers/net/ethernet/mediatek/mtk_wed.c | 391 ++++++++++++++-----
9 drivers/net/ethernet/mediatek/mtk_wed.h | 10 +
10 drivers/net/ethernet/mediatek/mtk_wed_regs.h | 9 +
11 include/linux/soc/mediatek/mtk_wed.h | 25 +-
12 5 files changed, 342 insertions(+), 101 deletions(-)
developerc89c5472022-08-02 13:00:04 +080013
developer6e3b5d12022-08-16 15:37:38 +080014diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developer69bcd592024-03-25 14:26:39 +080015index 268c9e7..a24b223 100644
developer6e3b5d12022-08-16 15:37:38 +080016--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
17+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
developer69bcd592024-03-25 14:26:39 +080018@@ -4619,6 +4619,9 @@ static void mtk_pending_work(struct work_struct *work)
developer1721ef62022-11-24 14:42:19 +080019 for (i = 0; i < MTK_MAC_COUNT; i++) {
20 if (!eth->netdev[i])
21 continue;
developer6e3b5d12022-08-16 15:37:38 +080022+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
developerd5169582023-02-17 10:32:38 +080023+ mtk_wed_fe_reset();
developer6e3b5d12022-08-16 15:37:38 +080024+#else
developerafda3572022-12-28 16:28:30 +080025 if (mtk_reset_flag == MTK_FE_STOP_TRAFFIC) {
26 pr_info("send MTK_FE_STOP_TRAFFIC event\n");
27 call_netdevice_notifiers(MTK_FE_STOP_TRAFFIC,
developer69bcd592024-03-25 14:26:39 +080028@@ -4644,6 +4647,7 @@ static void mtk_pending_work(struct work_struct *work)
developerd5169582023-02-17 10:32:38 +080029 pr_warn("wait for MTK_FE_START_RESET\n");
developer740bee82023-10-16 10:58:43 +080030 }
developer1721ef62022-11-24 14:42:19 +080031 rtnl_lock();
developer6e3b5d12022-08-16 15:37:38 +080032+#endif
developer1721ef62022-11-24 14:42:19 +080033 break;
34 }
developer6e3b5d12022-08-16 15:37:38 +080035
developer69bcd592024-03-25 14:26:39 +080036@@ -4682,6 +4686,9 @@ static void mtk_pending_work(struct work_struct *work)
developerafda3572022-12-28 16:28:30 +080037 for (i = 0; i < MTK_MAC_COUNT; i++) {
38 if (!eth->netdev[i])
developer1721ef62022-11-24 14:42:19 +080039 continue;
developer6e3b5d12022-08-16 15:37:38 +080040+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
developerd5169582023-02-17 10:32:38 +080041+ mtk_wed_fe_reset_complete();
developer6e3b5d12022-08-16 15:37:38 +080042+#else
developerafda3572022-12-28 16:28:30 +080043 if (mtk_reset_flag == MTK_FE_STOP_TRAFFIC) {
44 pr_info("send MTK_FE_START_TRAFFIC event\n");
45 call_netdevice_notifiers(MTK_FE_START_TRAFFIC,
developer69bcd592024-03-25 14:26:39 +080046@@ -4691,6 +4698,7 @@ static void mtk_pending_work(struct work_struct *work)
developerafda3572022-12-28 16:28:30 +080047 call_netdevice_notifiers(MTK_FE_RESET_DONE,
48 eth->netdev[i]);
49 }
developer6e3b5d12022-08-16 15:37:38 +080050+#endif
developerafda3572022-12-28 16:28:30 +080051 call_netdevice_notifiers(MTK_FE_RESET_NAT_DONE,
52 eth->netdev[i]);
developer1721ef62022-11-24 14:42:19 +080053 break;
developerc89c5472022-08-02 13:00:04 +080054diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c
developer69bcd592024-03-25 14:26:39 +080055index ad9f3d5..b993f0e 100644
developerc89c5472022-08-02 13:00:04 +080056--- a/drivers/net/ethernet/mediatek/mtk_wed.c
57+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
developer6e3b5d12022-08-16 15:37:38 +080058@@ -13,8 +13,10 @@
59 #include <linux/debugfs.h>
60 #include <linux/iopoll.h>
61 #include <linux/soc/mediatek/mtk_wed.h>
62+#include <net/rtnetlink.h>
63
64 #include "mtk_eth_soc.h"
65+#include "mtk_eth_reset.h"
66 #include "mtk_wed_regs.h"
67 #include "mtk_wed.h"
68 #include "mtk_ppe.h"
developer69bcd592024-03-25 14:26:39 +080069@@ -80,10 +82,13 @@ mtk_wdma_rx_reset(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +080070
71 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_DMA_EN);
developer69bcd592024-03-25 14:26:39 +080072 ret = readx_poll_timeout(mtk_wdma_read_reset, dev, status,
73- !(status & mask), 0, 1000)
74+ !(status & mask), 0, 10000);
75 if (ret)
76 dev_err(dev->hw->dev, "rx reset failed \n");
77
developerc89c5472022-08-02 13:00:04 +080078+ wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
79+ wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
developer69bcd592024-03-25 14:26:39 +080080+
81 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) {
82 if (!dev->rx_wdma[i].desc)
83 continue;
84@@ -91,6 +96,8 @@ mtk_wdma_rx_reset(struct mtk_wed_device *dev)
85 wdma_w32(dev,
86 MTK_WDMA_RING_RX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);
developerc89c5472022-08-02 13:00:04 +080087 }
88+
developer69bcd592024-03-25 14:26:39 +080089+ return ret;
developerc89c5472022-08-02 13:00:04 +080090 }
91
92 static void
developer69bcd592024-03-25 14:26:39 +080093@@ -101,16 +108,15 @@ mtk_wdma_tx_reset(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +080094
95 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
96 if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
97- !(status & mask), 0, 1000))
98+ !(status & mask), 0, 10000))
developer69bcd592024-03-25 14:26:39 +080099 dev_err(dev->hw->dev, "tx reset failed \n");
developerc89c5472022-08-02 13:00:04 +0800100
developer69bcd592024-03-25 14:26:39 +0800101- for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) {
102- if (!dev->tx_wdma[i].desc)
103- continue;
developerc89c5472022-08-02 13:00:04 +0800104+ wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
105+ wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
developer69bcd592024-03-25 14:26:39 +0800106
107+ for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
108 wdma_w32(dev,
109 MTK_WDMA_RING_TX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);
developer6e3b5d12022-08-16 15:37:38 +0800110- }
developer6e3b5d12022-08-16 15:37:38 +0800111 }
112
developer69bcd592024-03-25 14:26:39 +0800113 static void
114@@ -176,6 +182,59 @@ mtk_wed_wo_reset(struct mtk_wed_device *dev)
developerd5169582023-02-17 10:32:38 +0800115 iounmap((void *)reg);
116 }
117
118+void mtk_wed_fe_reset(void)
119+{
120+ int i;
121+
122+ mutex_lock(&hw_lock);
123+
124+ for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
125+ struct mtk_wed_hw *hw = hw_list[i];
developer69bcd592024-03-25 14:26:39 +0800126+ struct mtk_wed_device *dev;
developerd5169582023-02-17 10:32:38 +0800127+ int err;
128+
developer69bcd592024-03-25 14:26:39 +0800129+ if (!hw)
130+ break;
131+
132+ dev = hw->wed_dev;
developerd5169582023-02-17 10:32:38 +0800133+ if (!dev || !dev->wlan.reset)
134+ continue;
135+
136+ pr_info("%s: receive fe reset start event, trigger SER\n", __func__);
137+
138+ /* reset callback blocks until WLAN reset is completed */
139+ err = dev->wlan.reset(dev);
140+ if (err)
141+ dev_err(dev->dev, "wlan reset failed: %d\n", err);
142+ }
143+
144+ mutex_unlock(&hw_lock);
145+}
146+
147+void mtk_wed_fe_reset_complete(void)
148+{
149+ int i;
150+
151+ mutex_lock(&hw_lock);
152+
153+ for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
154+ struct mtk_wed_hw *hw = hw_list[i];
developer69bcd592024-03-25 14:26:39 +0800155+ struct mtk_wed_device *dev;
developerd5169582023-02-17 10:32:38 +0800156+
developer69bcd592024-03-25 14:26:39 +0800157+ if (!hw)
158+ break;
159+
160+ dev = hw->wed_dev;
developerd5169582023-02-17 10:32:38 +0800161+ if (!dev || !dev->wlan.reset_complete)
162+ continue;
163+
164+ pr_info("%s: receive fe reset done event, continue SER\n", __func__);
165+ dev->wlan.reset_complete(dev);
166+ }
167+
168+ mutex_unlock(&hw_lock);
169+}
170+
171 static struct mtk_wed_hw *
172 mtk_wed_assign(struct mtk_wed_device *dev)
173 {
developer69bcd592024-03-25 14:26:39 +0800174@@ -473,8 +532,8 @@ mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
175 }
176
177 if (i == 3) {
developerc89c5472022-08-02 13:00:04 +0800178- dev_err(dev->hw->dev, "mtk_wed%d: rx dma enable failed!\n",
179- dev->hw->index);
180+ dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable failed!\n",
181+ dev->hw->index, idx);
developer69bcd592024-03-25 14:26:39 +0800182 return;
developerc89c5472022-08-02 13:00:04 +0800183 }
developerc89c5472022-08-02 13:00:04 +0800184
developer69bcd592024-03-25 14:26:39 +0800185@@ -522,16 +581,8 @@ mtk_wed_dma_disable(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800186 static void
developerd5169582023-02-17 10:32:38 +0800187 mtk_wed_stop(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800188 {
189- mtk_wed_dma_disable(dev);
developerc89c5472022-08-02 13:00:04 +0800190-
developerc89c5472022-08-02 13:00:04 +0800191 mtk_wed_set_ext_int(dev, false);
192
developer69bcd592024-03-25 14:26:39 +0800193- wed_clr(dev, MTK_WED_CTRL,
194- MTK_WED_CTRL_WDMA_INT_AGENT_EN |
195- MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
196- MTK_WED_CTRL_WED_TX_BM_EN |
197- MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
198-
199 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
200 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
201 wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
202@@ -543,39 +594,49 @@ mtk_wed_stop(struct mtk_wed_device *dev)
203
204 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
205 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
206- wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
207-
208 }
209
210 static void
211-mtk_wed_detach(struct mtk_wed_device *dev)
developerd5169582023-02-17 10:32:38 +0800212+mtk_wed_deinit(struct mtk_wed_device *dev)
developer69bcd592024-03-25 14:26:39 +0800213 {
214- struct device_node *wlan_node;
215- struct mtk_wed_hw *hw = dev->hw;
developerd5169582023-02-17 10:32:38 +0800216+ mtk_wed_stop(dev);
217+ mtk_wed_dma_disable(dev);
developerd5169582023-02-17 10:32:38 +0800218
developer69bcd592024-03-25 14:26:39 +0800219- mutex_lock(&hw_lock);
220+ wed_clr(dev, MTK_WED_CTRL,
221+ MTK_WED_CTRL_WDMA_INT_AGENT_EN |
222+ MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
223+ MTK_WED_CTRL_WED_TX_BM_EN |
224+ MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
225
226- mtk_wed_stop(dev);
227+ if (dev->hw->version == 1)
developerd5169582023-02-17 10:32:38 +0800228+ return;
developerc89c5472022-08-02 13:00:04 +0800229
developer69bcd592024-03-25 14:26:39 +0800230- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
231- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
developerd5169582023-02-17 10:32:38 +0800232+ wed_clr(dev, MTK_WED_CTRL,
233+ MTK_WED_CTRL_RX_ROUTE_QM_EN |
234+ MTK_WED_CTRL_WED_RX_BM_EN |
235+ MTK_WED_CTRL_RX_RRO_QM_EN);
developer69bcd592024-03-25 14:26:39 +0800236+}
developerc89c5472022-08-02 13:00:04 +0800237
developer69bcd592024-03-25 14:26:39 +0800238- mtk_wed_reset(dev, MTK_WED_RESET_WED);
239+static void
240+__mtk_wed_detach(struct mtk_wed_device *dev)
241+{
242+ struct device_node *wlan_node;
243+ struct mtk_wed_hw *hw = dev->hw;
developerc89c5472022-08-02 13:00:04 +0800244
developer69bcd592024-03-25 14:26:39 +0800245- if (mtk_wed_get_rx_capa(dev)) {
246- wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
247- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
248- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
249- }
developerd5169582023-02-17 10:32:38 +0800250+ mtk_wed_deinit(dev);
developerc89c5472022-08-02 13:00:04 +0800251
developerc89c5472022-08-02 13:00:04 +0800252+ mtk_wdma_rx_reset(dev);
developer69bcd592024-03-25 14:26:39 +0800253+ mtk_wed_reset(dev, MTK_WED_RESET_WED);
254 mtk_wed_free_tx_buffer(dev);
developerc89c5472022-08-02 13:00:04 +0800255 mtk_wed_free_tx_rings(dev);
developer69bcd592024-03-25 14:26:39 +0800256
257 if (mtk_wed_get_rx_capa(dev)) {
258- mtk_wed_wo_reset(dev);
259+ if(hw->wed_wo)
260+ mtk_wed_wo_reset(dev);
261 mtk_wed_free_rx_rings(dev);
262- mtk_wed_wo_exit(hw);
263- mtk_wdma_rx_reset(dev);
264+ if(hw->wed_wo)
265+ mtk_wed_wo_exit(hw);
266+ mtk_wdma_tx_reset(dev);
developerc89c5472022-08-02 13:00:04 +0800267 }
268
developer3d5faf22022-11-29 18:07:22 +0800269 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
developer69bcd592024-03-25 14:26:39 +0800270@@ -593,6 +654,13 @@ mtk_wed_detach(struct mtk_wed_device *dev)
271 module_put(THIS_MODULE);
272
273 hw->wed_dev = NULL;
274+}
275+
276+static void
277+mtk_wed_detach(struct mtk_wed_device *dev)
278+{
279+ mutex_lock(&hw_lock);
280+ __mtk_wed_detach(dev);
281 mutex_unlock(&hw_lock);
282 }
283
284@@ -665,7 +733,7 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800285 {
286 u32 mask, set;
287
288- mtk_wed_stop(dev);
developerd5169582023-02-17 10:32:38 +0800289+ mtk_wed_deinit(dev);
developerc89c5472022-08-02 13:00:04 +0800290 mtk_wed_reset(dev, MTK_WED_RESET_WED);
developer69bcd592024-03-25 14:26:39 +0800291 mtk_wed_set_wpdma(dev);
developerc89c5472022-08-02 13:00:04 +0800292
developer69bcd592024-03-25 14:26:39 +0800293@@ -715,7 +783,6 @@ mtk_wed_rro_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
294
295 ring->desc_size = sizeof(*ring->desc);
296 ring->size = size;
297- memset(ring->desc, 0, size);
298
299 return 0;
300 }
301@@ -938,44 +1005,140 @@ mtk_wed_ring_reset(struct mtk_wed_ring *ring, int size, bool tx)
developerc89c5472022-08-02 13:00:04 +0800302 }
303
304 static u32
305-mtk_wed_check_busy(struct mtk_wed_device *dev)
306+mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
307 {
308- if (wed_r32(dev, MTK_WED_GLO_CFG) & MTK_WED_GLO_CFG_TX_DMA_BUSY)
309- return true;
310-
311- if (wed_r32(dev, MTK_WED_WPDMA_GLO_CFG) &
312- MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY)
313- return true;
314-
315- if (wed_r32(dev, MTK_WED_CTRL) & MTK_WED_CTRL_WDMA_INT_AGENT_BUSY)
316- return true;
317-
318- if (wed_r32(dev, MTK_WED_WDMA_GLO_CFG) &
319- MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
320- return true;
321-
322- if (wdma_r32(dev, MTK_WDMA_GLO_CFG) &
323- MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
324- return true;
325-
326- if (wed_r32(dev, MTK_WED_CTRL) &
327- (MTK_WED_CTRL_WED_TX_BM_BUSY | MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY))
developer69bcd592024-03-25 14:26:39 +0800328+ if (wed_r32(dev, reg) & mask)
developerc89c5472022-08-02 13:00:04 +0800329 return true;
330
331 return false;
332 }
333
334 static int
335-mtk_wed_poll_busy(struct mtk_wed_device *dev)
336+mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
337 {
338- int sleep = 15000;
339+ int sleep = 1000;
340 int timeout = 100 * sleep;
341 u32 val;
342
343 return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
344- timeout, false, dev);
345+ timeout, false, dev, reg, mask);
developerd5169582023-02-17 10:32:38 +0800346 }
347
developer69bcd592024-03-25 14:26:39 +0800348+static int
developerc89c5472022-08-02 13:00:04 +0800349+mtk_wed_rx_reset(struct mtk_wed_device *dev)
350+{
351+ struct mtk_wed_wo *wo = dev->hw->wed_wo;
developer69bcd592024-03-25 14:26:39 +0800352+ u8 val = WO_STATE_SER_RESET;
353+ int i, ret;
developerc89c5472022-08-02 13:00:04 +0800354+
developer69bcd592024-03-25 14:26:39 +0800355+ ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
356+ MTK_WED_WO_CMD_CHANGE_STATE, &val,
357+ sizeof(val), true);
358+
359+ if (ret)
360+ return ret;
developerc89c5472022-08-02 13:00:04 +0800361+
362+ wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN);
developer69bcd592024-03-25 14:26:39 +0800363+ ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
364+ MTK_WED_WPDMA_RX_D_RX_DRV_BUSY);
365+ if (ret) {
developerc89c5472022-08-02 13:00:04 +0800366+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
367+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV);
368+ } else {
369+ wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
370+ MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
371+ MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
372+
373+ wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
374+ MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
375+ MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
376+ wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
377+ MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
378+ MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
379+
380+ wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
381+ }
382+
383+ /* reset rro qm */
384+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN);
developer69bcd592024-03-25 14:26:39 +0800385+ ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
386+ MTK_WED_CTRL_RX_RRO_QM_BUSY);
387+ if (ret) {
developerc89c5472022-08-02 13:00:04 +0800388+ mtk_wed_reset(dev, MTK_WED_RESET_RX_RRO_QM);
389+ } else {
390+ wed_set(dev, MTK_WED_RROQM_RST_IDX,
391+ MTK_WED_RROQM_RST_IDX_MIOD |
392+ MTK_WED_RROQM_RST_IDX_FDBK);
393+ wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
394+ }
395+
396+ /* reset route qm */
397+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
developer69bcd592024-03-25 14:26:39 +0800398+ ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
399+ MTK_WED_CTRL_RX_ROUTE_QM_BUSY);
400+ if (ret) {
developerc89c5472022-08-02 13:00:04 +0800401+ mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
402+ } else {
403+ wed_set(dev, MTK_WED_RTQM_GLO_CFG,
404+ MTK_WED_RTQM_Q_RST);
405+ }
406+
407+ /* reset tx wdma */
408+ mtk_wdma_tx_reset(dev);
409+
410+ /* reset tx wdma drv */
411+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN);
412+ mtk_wed_poll_busy(dev, MTK_WED_CTRL,
413+ MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
414+ mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
415+
416+ /* reset wed rx dma */
developer69bcd592024-03-25 14:26:39 +0800417+ ret = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG,
418+ MTK_WED_GLO_CFG_RX_DMA_BUSY);
developerc89c5472022-08-02 13:00:04 +0800419+ wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_RX_DMA_EN);
developer69bcd592024-03-25 14:26:39 +0800420+ if (ret) {
developerc89c5472022-08-02 13:00:04 +0800421+ mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
422+ } else {
developer69bcd592024-03-25 14:26:39 +0800423+ struct mtk_eth *eth = dev->hw->eth;
424+
425+ if(MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
426+ wed_set(dev, MTK_WED_RESET_IDX,
427+ MTK_WED_RESET_IDX_RX_V2);
428+ else
429+ wed_set(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_IDX_RX);
developerc89c5472022-08-02 13:00:04 +0800430+ wed_w32(dev, MTK_WED_RESET_IDX, 0);
431+ }
432+
433+ /* reset rx bm */
434+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
435+ mtk_wed_poll_busy(dev, MTK_WED_CTRL,
developer69bcd592024-03-25 14:26:39 +0800436+ MTK_WED_CTRL_WED_RX_BM_BUSY);
developerc89c5472022-08-02 13:00:04 +0800437+ mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
438+
439+ /* wo change to enable state */
developer69bcd592024-03-25 14:26:39 +0800440+ val = WO_STATE_ENABLE;
441+ ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
442+ MTK_WED_WO_CMD_CHANGE_STATE, &val,
443+ sizeof(val), true);
444+
445+ if (ret)
446+ return ret;
developerc89c5472022-08-02 13:00:04 +0800447+
448+ /* wed_rx_ring_reset */
449+ for (i = 0; i < ARRAY_SIZE(dev->rx_ring); i++) {
developer69bcd592024-03-25 14:26:39 +0800450+ if (!dev->rx_ring[i].desc)
developerc89c5472022-08-02 13:00:04 +0800451+ continue;
452+
developer69bcd592024-03-25 14:26:39 +0800453+ mtk_wed_ring_reset(&dev->rx_ring[i], MTK_WED_RX_RING_SIZE,
454+ false);
developerc89c5472022-08-02 13:00:04 +0800455+ }
456+
developer69bcd592024-03-25 14:26:39 +0800457+ mtk_wed_free_rx_buffer(dev);
458+
459+ return 0;
developerd5169582023-02-17 10:32:38 +0800460+}
461+
developerc89c5472022-08-02 13:00:04 +0800462+
463 static void
464 mtk_wed_reset_dma(struct mtk_wed_device *dev)
465 {
developer69bcd592024-03-25 14:26:39 +0800466@@ -991,22 +1154,25 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
467 true);
developerc89c5472022-08-02 13:00:04 +0800468 }
469
470- if (mtk_wed_poll_busy(dev))
471- busy = mtk_wed_check_busy(dev);
472+ /* 1.Reset WED Tx DMA */
473+ wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_TX_DMA_EN);
developer69bcd592024-03-25 14:26:39 +0800474+ busy = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG,
475+ MTK_WED_GLO_CFG_TX_DMA_BUSY);
developerc89c5472022-08-02 13:00:04 +0800476
477 if (busy) {
478 mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
479 } else {
developer69bcd592024-03-25 14:26:39 +0800480- wed_w32(dev, MTK_WED_RESET_IDX,
developerc89c5472022-08-02 13:00:04 +0800481- MTK_WED_RESET_IDX_TX |
482- MTK_WED_RESET_IDX_RX);
developer69bcd592024-03-25 14:26:39 +0800483+ wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_IDX_TX);
developerc89c5472022-08-02 13:00:04 +0800484 wed_w32(dev, MTK_WED_RESET_IDX, 0);
485 }
486
487- wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
488- wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
489+ /* 2. Reset WDMA Rx DMA/Driver_Engine */
490+ busy = !!mtk_wdma_rx_reset(dev);
491
492- mtk_wdma_rx_reset(dev);
493+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
developer69bcd592024-03-25 14:26:39 +0800494+ if (!busy)
495+ busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG,
496+ MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY);
developerc89c5472022-08-02 13:00:04 +0800497
498 if (busy) {
499 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
developer69bcd592024-03-25 14:26:39 +0800500@@ -1023,6 +1189,9 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800501 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
502 }
503
504+ /* 3. Reset WED WPDMA Tx Driver Engine */
developer69bcd592024-03-25 14:26:39 +0800505+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
developerc89c5472022-08-02 13:00:04 +0800506+
507 for (i = 0; i < 100; i++) {
508 val = wed_r32(dev, MTK_WED_TX_BM_INTF);
509 if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
developer69bcd592024-03-25 14:26:39 +0800510@@ -1030,8 +1199,21 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800511 }
developer69bcd592024-03-25 14:26:39 +0800512
developerc89c5472022-08-02 13:00:04 +0800513 mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);
developerc89c5472022-08-02 13:00:04 +0800514+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_BM_EN);
515 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
516
517+ /* 4. Reset WED WPDMA Tx Driver Engine */
518+ busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
developer69bcd592024-03-25 14:26:39 +0800519+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY);
520+
developerc89c5472022-08-02 13:00:04 +0800521+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
522+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
523+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
524+
developer69bcd592024-03-25 14:26:39 +0800525+ if(!busy)
526+ mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
527+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY);
528+
developerc89c5472022-08-02 13:00:04 +0800529 if (busy) {
530 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
531 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
developer69bcd592024-03-25 14:26:39 +0800532@@ -1043,6 +1225,16 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800533 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
developerc89c5472022-08-02 13:00:04 +0800534 }
535
developer69bcd592024-03-25 14:26:39 +0800536+ dev->init_done = false;
537+ if (dev->hw->version == 1)
538+ return;
539+
540+ if (!busy) {
541+ wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_WPDMA_IDX_RX);
542+ wed_w32(dev, MTK_WED_RESET_IDX, 0);
543+ }
544+
545+ mtk_wed_rx_reset(dev);
developer6e3b5d12022-08-16 15:37:38 +0800546 }
developer69bcd592024-03-25 14:26:39 +0800547
548 static int
549@@ -1062,7 +1254,8 @@ mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
developer6e3b5d12022-08-16 15:37:38 +0800550 }
551
552 static int
553-mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
developer69bcd592024-03-25 14:26:39 +0800554+mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
555+ bool reset)
developer6e3b5d12022-08-16 15:37:38 +0800556 {
developer69bcd592024-03-25 14:26:39 +0800557 u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
558 struct mtk_wed_ring *wdma;
559@@ -1071,8 +1264,8 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
560 return -EINVAL;
developer6e3b5d12022-08-16 15:37:38 +0800561
developer69bcd592024-03-25 14:26:39 +0800562 wdma = &dev->rx_wdma[idx];
563- if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, desc_size,
564- true))
565+ if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
566+ desc_size, true))
567 return -ENOMEM;
developer6e3b5d12022-08-16 15:37:38 +0800568
569 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
developer69bcd592024-03-25 14:26:39 +0800570@@ -1090,7 +1283,8 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
developerc89c5472022-08-02 13:00:04 +0800571 }
developer6e3b5d12022-08-16 15:37:38 +0800572
573 static int
574-mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
developer69bcd592024-03-25 14:26:39 +0800575+mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
576+ bool reset)
developer6e3b5d12022-08-16 15:37:38 +0800577 {
developer69bcd592024-03-25 14:26:39 +0800578 u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
579 struct mtk_wed_ring *wdma;
580@@ -1099,8 +1293,8 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
581 return -EINVAL;
developer6e3b5d12022-08-16 15:37:38 +0800582
developer69bcd592024-03-25 14:26:39 +0800583 wdma = &dev->tx_wdma[idx];
developer6e3b5d12022-08-16 15:37:38 +0800584- if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
developer69bcd592024-03-25 14:26:39 +0800585- desc_size, true))
586+ if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
587+ desc_size, true))
588 return -ENOMEM;
developer6e3b5d12022-08-16 15:37:38 +0800589
590 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
developer69bcd592024-03-25 14:26:39 +0800591@@ -1112,6 +1306,9 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
developer6e3b5d12022-08-16 15:37:38 +0800592 wdma_w32(dev,
593 MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
developer69bcd592024-03-25 14:26:39 +0800594
developer6e3b5d12022-08-16 15:37:38 +0800595+ if (reset)
developer69bcd592024-03-25 14:26:39 +0800596+ mtk_wed_ring_reset(wdma, MTK_WED_WDMA_RING_SIZE, true);
597+
598 if (!idx) {
599 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_BASE,
600 wdma->desc_phys);
601@@ -1267,9 +1464,12 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
developerc89c5472022-08-02 13:00:04 +0800602 {
developer69bcd592024-03-25 14:26:39 +0800603 int i;
developerc89c5472022-08-02 13:00:04 +0800604
developer69bcd592024-03-25 14:26:39 +0800605+ if (mtk_wed_get_rx_capa(dev) && mtk_wed_rx_buffer_alloc(dev))
606+ return;
developerc89c5472022-08-02 13:00:04 +0800607+
developer69bcd592024-03-25 14:26:39 +0800608 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
609 if (!dev->rx_wdma[i].desc)
developer6e3b5d12022-08-16 15:37:38 +0800610- mtk_wed_wdma_rx_ring_setup(dev, i, 16);
611+ mtk_wed_wdma_rx_ring_setup(dev, i, 16, false);
612
developer69bcd592024-03-25 14:26:39 +0800613
developer6e3b5d12022-08-16 15:37:38 +0800614 mtk_wed_hw_init(dev);
developer69bcd592024-03-25 14:26:39 +0800615@@ -1278,10 +1478,9 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
616 mtk_wed_set_ext_int(dev, true);
617
618 if (dev->hw->version == 1) {
619- u32 val;
620-
621- val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
622- FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index);
623+ u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
624+ FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID,
625+ dev->hw->index);
developer6e3b5d12022-08-16 15:37:38 +0800626
developer69bcd592024-03-25 14:26:39 +0800627 val |= BIT(0) | (BIT(1) * !!dev->hw->index);
628 regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
629@@ -1353,10 +1552,6 @@ mtk_wed_attach(struct mtk_wed_device *dev)
630 goto out;
developerc89c5472022-08-02 13:00:04 +0800631
developer69bcd592024-03-25 14:26:39 +0800632 if (mtk_wed_get_rx_capa(dev)) {
633- ret = mtk_wed_rx_buffer_alloc(dev);
developerc89c5472022-08-02 13:00:04 +0800634- if (ret)
developer69bcd592024-03-25 14:26:39 +0800635- goto out;
developerc89c5472022-08-02 13:00:04 +0800636-
637 ret = mtk_wed_rro_alloc(dev);
638 if (ret)
developer69bcd592024-03-25 14:26:39 +0800639 goto out;
640@@ -1364,6 +1559,10 @@ mtk_wed_attach(struct mtk_wed_device *dev)
developer6e3b5d12022-08-16 15:37:38 +0800641
642 mtk_wed_hw_init_early(dev);
643
644+ init_completion(&dev->fe_reset_done);
645+ init_completion(&dev->wlan_reset_done);
646+ atomic_set(&dev->fe_reset, 0);
647+
developer69bcd592024-03-25 14:26:39 +0800648 if (hw->version == 1) {
developer6e3b5d12022-08-16 15:37:38 +0800649 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
650 BIT(hw->index), 0);
developer69bcd592024-03-25 14:26:39 +0800651@@ -1373,8 +1572,10 @@ mtk_wed_attach(struct mtk_wed_device *dev)
652 }
653
654 out:
655- if (ret)
656- mtk_wed_detach(dev);
657+ if (ret) {
658+ dev_err(dev->hw->dev, "failed to attach wed device\n");
659+ __mtk_wed_detach(dev);
660+ }
661 unlock:
662 mutex_unlock(&hw_lock);
663
664@@ -1382,7 +1583,8 @@ mtk_wed_attach(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800665 }
666
667 static int
668-mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
669+mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx,
670+ void __iomem *regs, bool reset)
671 {
672 struct mtk_wed_ring *ring = &dev->tx_ring[idx];
673
developer69bcd592024-03-25 14:26:39 +0800674@@ -1401,11 +1603,12 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
675 if (WARN_ON(idx >= ARRAY_SIZE(dev->tx_ring)))
676 return -EINVAL;
developerc89c5472022-08-02 13:00:04 +0800677
developer69bcd592024-03-25 14:26:39 +0800678- if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE,
679- sizeof(*ring->desc), true))
680+ if (!reset && mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE,
681+ sizeof(*ring->desc), true))
682 return -ENOMEM;
developerc89c5472022-08-02 13:00:04 +0800683
developer6e3b5d12022-08-16 15:37:38 +0800684- if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
developer69bcd592024-03-25 14:26:39 +0800685+ if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE,
686+ reset))
developer6e3b5d12022-08-16 15:37:38 +0800687 return -ENOMEM;
developerc89c5472022-08-02 13:00:04 +0800688
developer6e3b5d12022-08-16 15:37:38 +0800689 ring->reg_base = MTK_WED_RING_TX(idx);
developer69bcd592024-03-25 14:26:39 +0800690@@ -1450,18 +1653,20 @@ mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
developerc89c5472022-08-02 13:00:04 +0800691 }
692
693 static int
694-mtk_wed_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
developer69bcd592024-03-25 14:26:39 +0800695+mtk_wed_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs,
696+ bool reset)
developerc89c5472022-08-02 13:00:04 +0800697 {
698 struct mtk_wed_ring *ring = &dev->rx_ring[idx];
699
developer69bcd592024-03-25 14:26:39 +0800700 if (WARN_ON(idx >= ARRAY_SIZE(dev->rx_ring)))
701 return -EINVAL;
developerc89c5472022-08-02 13:00:04 +0800702
developer69bcd592024-03-25 14:26:39 +0800703- if (mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE,
704- sizeof(*ring->desc), false))
705+ if (!reset && mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE,
706+ sizeof(*ring->desc), false))
707 return -ENOMEM;
developerc89c5472022-08-02 13:00:04 +0800708
developerc89c5472022-08-02 13:00:04 +0800709- if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
developer69bcd592024-03-25 14:26:39 +0800710+ if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE,
711+ reset))
developer6e3b5d12022-08-16 15:37:38 +0800712 return -ENOMEM;
713
developerc89c5472022-08-02 13:00:04 +0800714 ring->reg_base = MTK_WED_RING_RX_DATA(idx);
developerc89c5472022-08-02 13:00:04 +0800715diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h
developer69bcd592024-03-25 14:26:39 +0800716index 1bfd96f..2ce1a5b 100644
developerc89c5472022-08-02 13:00:04 +0800717--- a/drivers/net/ethernet/mediatek/mtk_wed.h
718+++ b/drivers/net/ethernet/mediatek/mtk_wed.h
developer69bcd592024-03-25 14:26:39 +0800719@@ -160,6 +160,9 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
developerd5169582023-02-17 10:32:38 +0800720 void mtk_wed_exit(void);
721 int mtk_wed_flow_add(int index);
722 void mtk_wed_flow_remove(int index);
723+void mtk_wed_fe_reset(void);
724+void mtk_wed_fe_reset_complete(void);
725+
726 #else
727 static inline void
728 mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
developer69bcd592024-03-25 14:26:39 +0800729@@ -178,6 +181,13 @@ static inline int mtk_wed_flow_add(int index)
developerd5169582023-02-17 10:32:38 +0800730 static inline void mtk_wed_flow_remove(int index)
731 {
732 }
733+static inline void mtk_wed_fe_reset(void)
734+{
735+}
736+
737+static inline void mtk_wed_fe_reset_complete(void)
738+{
739+}
developer6e3b5d12022-08-16 15:37:38 +0800740 #endif
developerd5169582023-02-17 10:32:38 +0800741
742 #ifdef CONFIG_DEBUG_FS
developerc89c5472022-08-02 13:00:04 +0800743diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
developer69bcd592024-03-25 14:26:39 +0800744index a79305f..645b8b1 100644
developerc89c5472022-08-02 13:00:04 +0800745--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
746+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
developer69bcd592024-03-25 14:26:39 +0800747@@ -32,11 +32,15 @@ struct mtk_wdma_desc {
developerc89c5472022-08-02 13:00:04 +0800748
749 #define MTK_WED_RESET 0x008
750 #define MTK_WED_RESET_TX_BM BIT(0)
751+#define MTK_WED_RESET_RX_BM BIT(1)
752 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
753 #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)
754 #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)
755+#define MTK_WED_RESET_WPDMA_RX_D_DRV BIT(10)
756 #define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11)
757 #define MTK_WED_RESET_WED_TX_DMA BIT(12)
758+#define MTK_WED_RESET_WED_RX_DMA BIT(13)
759+#define MTK_WED_RESET_WDMA_TX_DRV BIT(16)
760 #define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
761 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
762 #define MTK_WED_RESET_RX_RRO_QM BIT(20)
developer69bcd592024-03-25 14:26:39 +0800763@@ -174,6 +178,8 @@ struct mtk_wdma_desc {
developerc89c5472022-08-02 13:00:04 +0800764 #define MTK_WED_RESET_IDX 0x20c
765 #define MTK_WED_RESET_IDX_TX GENMASK(3, 0)
developerc89c5472022-08-02 13:00:04 +0800766 #define MTK_WED_RESET_IDX_RX GENMASK(17, 16)
developer69bcd592024-03-25 14:26:39 +0800767+#define MTK_WED_RESET_IDX_RX_V2 GENMASK(7, 6)
developerc89c5472022-08-02 13:00:04 +0800768+#define MTK_WED_RESET_WPDMA_IDX_RX GENMASK(31, 30)
769
770 #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4)
771 #define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4)
developer69bcd592024-03-25 14:26:39 +0800772@@ -287,6 +293,9 @@ struct mtk_wdma_desc {
developerc89c5472022-08-02 13:00:04 +0800773
774 #define MTK_WED_WPDMA_RX_D_GLO_CFG 0x75c
775 #define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)
776+#define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY BIT(1)
777+#define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE BIT(3)
778+#define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE BIT(4)
779 #define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL GENMASK(11, 7)
780 #define MTK_WED_WPDMA_RX_D_RXD_READ_LEN GENMASK(31, 24)
781
782diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h
developer69bcd592024-03-25 14:26:39 +0800783index 658f392..6772ea8 100644
developerc89c5472022-08-02 13:00:04 +0800784--- a/include/linux/soc/mediatek/mtk_wed.h
785+++ b/include/linux/soc/mediatek/mtk_wed.h
developer69bcd592024-03-25 14:26:39 +0800786@@ -151,16 +151,21 @@ struct mtk_wed_device {
developer6e3b5d12022-08-16 15:37:38 +0800787 void (*release_rx_buf)(struct mtk_wed_device *wed);
developer3d5faf22022-11-29 18:07:22 +0800788 void (*update_wo_rx_stats)(struct mtk_wed_device *wed,
789 struct mtk_wed_wo_rx_stats *stats);
developerd5169582023-02-17 10:32:38 +0800790+ int (*reset)(struct mtk_wed_device *wed);
791+ void (*reset_complete)(struct mtk_wed_device *wed);
developer6e3b5d12022-08-16 15:37:38 +0800792 } wlan;
793+ struct completion fe_reset_done;
794+ struct completion wlan_reset_done;
795+ atomic_t fe_reset;
796 #endif
797 };
798
developerc89c5472022-08-02 13:00:04 +0800799 struct mtk_wed_ops {
800 int (*attach)(struct mtk_wed_device *dev);
801 int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,
802- void __iomem *regs);
803+ void __iomem *regs, bool reset);
developerc89c5472022-08-02 13:00:04 +0800804 int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring,
developer69bcd592024-03-25 14:26:39 +0800805- void __iomem *regs);
developerc89c5472022-08-02 13:00:04 +0800806+ void __iomem *regs, bool reset);
developer69bcd592024-03-25 14:26:39 +0800807 int (*txfree_ring_setup)(struct mtk_wed_device *dev,
808 void __iomem *regs);
developerc89c5472022-08-02 13:00:04 +0800809 int (*msg_update)(struct mtk_wed_device *dev, int cmd_id,
developer69bcd592024-03-25 14:26:39 +0800810@@ -216,8 +221,8 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800811 #define mtk_wed_device_active(_dev) !!(_dev)->ops
812 #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
813 #define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask)
814-#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \
815- (_dev)->ops->tx_ring_setup(_dev, _ring, _regs)
developerc89c5472022-08-02 13:00:04 +0800816+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) \
developer69bcd592024-03-25 14:26:39 +0800817+ (_dev)->ops->tx_ring_setup(_dev, _ring, _regs, _reset)
developerc89c5472022-08-02 13:00:04 +0800818 #define mtk_wed_device_txfree_ring_setup(_dev, _regs) \
819 (_dev)->ops->txfree_ring_setup(_dev, _regs)
developerc89c5472022-08-02 13:00:04 +0800820 #define mtk_wed_device_reg_read(_dev, _reg) \
developer69bcd592024-03-25 14:26:39 +0800821@@ -228,12 +233,14 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800822 (_dev)->ops->irq_get(_dev, _mask)
823 #define mtk_wed_device_irq_set_mask(_dev, _mask) \
824 (_dev)->ops->irq_set_mask(_dev, _mask)
developer69bcd592024-03-25 14:26:39 +0800825-#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) \
826- (_dev)->ops->rx_ring_setup(_dev, _ring, _regs)
827+#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) \
828+ (_dev)->ops->rx_ring_setup(_dev, _ring, _regs, reset)
developerc89c5472022-08-02 13:00:04 +0800829 #define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \
830 (_dev)->ops->ppe_check(_dev, _skb, _reason, _hash)
developer69bcd592024-03-25 14:26:39 +0800831 #define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
832 (_dev)->ops->msg_update(_dev, _id, _msg, _len)
833+#define mtk_wed_device_stop(_dev) (_dev)->ops->stop(_dev)
834+#define mtk_wed_device_dma_reset(_dev) (_dev)->ops->reset_dma(_dev)
developerc89c5472022-08-02 13:00:04 +0800835 #else
developer69bcd592024-03-25 14:26:39 +0800836 static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
837 {
838@@ -241,15 +248,17 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
developerc89c5472022-08-02 13:00:04 +0800839 }
840 #define mtk_wed_device_detach(_dev) do {} while (0)
841 #define mtk_wed_device_start(_dev, _mask) do {} while (0)
842-#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV
developerc89c5472022-08-02 13:00:04 +0800843+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
844 #define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV
developerc89c5472022-08-02 13:00:04 +0800845 #define mtk_wed_device_reg_read(_dev, _reg) 0
846 #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
847 #define mtk_wed_device_irq_get(_dev, _mask) 0
848 #define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)
developer69bcd592024-03-25 14:26:39 +0800849-#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) -ENODEV
850+#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
developerc89c5472022-08-02 13:00:04 +0800851 #define mtk_wed_device_ppe_check(_dev, _hash) do {} while (0)
developer69bcd592024-03-25 14:26:39 +0800852 #define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV
853+#define mtk_wed_device_stop(_dev) do {} while (0)
854+#define mtk_wed_device_dma_reset(_dev) do {} while (0)
developerc89c5472022-08-02 13:00:04 +0800855 #endif
856
developer69bcd592024-03-25 14:26:39 +0800857 #endif
developerc89c5472022-08-02 13:00:04 +0800858--
8592.18.0
860