developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1 | From f99c7b63e766c2ff8851a8ba6ff77f3d8bfef0d5 Mon Sep 17 00:00:00 2001 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 2 | From: Bo Jiao <Bo.Jiao@mediatek.com> |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 3 | Date: Mon, 18 Sep 2023 10:55:08 +0800 |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 4 | Subject: [PATCH 02/24] dts netsys2 wed changes |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 5 | |
| 6 | --- |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 7 | .../boot/dts/mediatek/mt7981-spim-nor-rfb.dts | 8 ----- |
| 8 | arch/arm64/boot/dts/mediatek/mt7981.dtsi | 21 ++++-------- |
| 9 | arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 33 +++++++------------ |
| 10 | arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 33 +++++++------------ |
| 11 | 4 files changed, 28 insertions(+), 67 deletions(-) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 12 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 13 | diff --git a/arch/arm64/boot/dts/mediatek/mt7981-spim-nor-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7981-spim-nor-rfb.dts |
| 14 | index 3fa55a0..f5c70a4 100755 |
| 15 | --- a/arch/arm64/boot/dts/mediatek/mt7981-spim-nor-rfb.dts |
| 16 | +++ b/arch/arm64/boot/dts/mediatek/mt7981-spim-nor-rfb.dts |
| 17 | @@ -211,11 +211,3 @@ |
| 18 | &xhci { |
| 19 | status = "okay"; |
| 20 | }; |
| 21 | - |
| 22 | -&wed { |
| 23 | - dy_txbm_enable = "true"; |
| 24 | - dy_txbm_budget = <8>; |
| 25 | - txbm_init_sz = <8>; |
| 26 | - txbm_max_sz = <32>; |
| 27 | - status = "okay"; |
| 28 | -}; |
| 29 | diff --git a/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
| 30 | index 91415e4..283421a 100644 |
| 31 | --- a/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
| 32 | +++ b/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
| 33 | @@ -90,22 +90,12 @@ |
| 34 | #io-channel-cells = <1>; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | - wed: wed@15010000 { |
| 38 | - compatible = "mediatek,wed"; |
| 39 | - wed_num = <2>; |
| 40 | - /* add this property for wed get the pci slot number. */ |
| 41 | - pci_slot_map = <0>, <1>; |
| 42 | - reg = <0 0x15010000 0 0x1000>, |
| 43 | - <0 0x15011000 0 0x1000>; |
| 44 | + wed0: wed@15010000 { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 45 | + compatible = "mediatek,mt7981-wed", |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 46 | + "syscon"; |
| 47 | + reg = <0 0x15010000 0 0x1000>; |
| 48 | interrupt-parent = <&gic>; |
| 49 | - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 50 | - <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 51 | - }; |
| 52 | - |
| 53 | - wdma: wdma@15104800 { |
| 54 | - compatible = "mediatek,wed-wdma"; |
| 55 | - reg = <0 0x15104800 0 0x400>, |
| 56 | - <0 0x15104c00 0 0x400>; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 57 | + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 58 | }; |
| 59 | |
| 60 | ap2woccif: ap2woccif@151A5000 { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 61 | @@ -423,6 +413,7 @@ |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 62 | mediatek,ethsys = <ðsys>; |
| 63 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 64 | mediatek,infracfg = <&topmisc>; |
| 65 | + mediatek,wed = <&wed0>; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 66 | #reset-cells = <1>; |
| 67 | #address-cells = <1>; |
| 68 | #size-cells = <0>; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 69 | diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
| 70 | index 2c7e171..3a4f279 100644 |
| 71 | --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
| 72 | +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 73 | @@ -58,32 +58,20 @@ |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | - wed: wed@15010000 { |
| 78 | - compatible = "mediatek,wed"; |
| 79 | - wed_num = <2>; |
| 80 | - /* add this property for wed get the pci slot number. */ |
| 81 | - pci_slot_map = <0>, <1>; |
| 82 | - reg = <0 0x15010000 0 0x1000>, |
| 83 | - <0 0x15011000 0 0x1000>; |
| 84 | + wed0: wed@15010000 { |
| 85 | + compatible = "mediatek,mt7986-wed", |
| 86 | + "syscon"; |
| 87 | + reg = <0 0x15010000 0 0x1000>; |
| 88 | interrupt-parent = <&gic>; |
| 89 | - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 90 | - <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 91 | + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 92 | }; |
| 93 | |
| 94 | - wed2: wed2@15011000 { |
| 95 | - compatible = "mediatek,wed2"; |
| 96 | - wed_num = <2>; |
| 97 | - reg = <0 0x15010000 0 0x1000>, |
| 98 | - <0 0x15011000 0 0x1000>; |
| 99 | + wed1: wed@15011000 { |
| 100 | + compatible = "mediatek,mt7986-wed", |
| 101 | + "syscon"; |
| 102 | + reg = <0 0x15011000 0 0x1000>; |
| 103 | interrupt-parent = <&gic>; |
| 104 | - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 105 | - <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 106 | - }; |
| 107 | - |
| 108 | - wdma: wdma@15104800 { |
| 109 | - compatible = "mediatek,wed-wdma"; |
| 110 | - reg = <0 0x15104800 0 0x400>, |
| 111 | - <0 0x15104c00 0 0x400>; |
| 112 | + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 113 | }; |
| 114 | |
| 115 | ap2woccif: ap2woccif@151A5000 { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 116 | @@ -494,6 +482,7 @@ |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 117 | <&topckgen CK_TOP_CB_SGM_325M>; |
| 118 | mediatek,ethsys = <ðsys>; |
| 119 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 120 | + mediatek,wed = <&wed0>, <&wed1>; |
| 121 | #reset-cells = <1>; |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <0>; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 124 | diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 125 | index 26f093b..ce884f0 100644 |
| 126 | --- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 127 | +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 128 | @@ -58,32 +58,20 @@ |
| 129 | }; |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | - wed: wed@15010000 { |
| 133 | - compatible = "mediatek,wed"; |
| 134 | - wed_num = <2>; |
| 135 | - /* add this property for wed get the pci slot number. */ |
| 136 | - pci_slot_map = <0>, <1>; |
| 137 | - reg = <0 0x15010000 0 0x1000>, |
| 138 | - <0 0x15011000 0 0x1000>; |
| 139 | + wed0: wed@15010000 { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 140 | + compatible = "mediatek,mt7986-wed", |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 141 | + "syscon"; |
| 142 | + reg = <0 0x15010000 0 0x1000>; |
| 143 | interrupt-parent = <&gic>; |
| 144 | - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 145 | - <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 146 | + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 147 | }; |
| 148 | |
| 149 | - wed2: wed2@15011000 { |
| 150 | - compatible = "mediatek,wed2"; |
| 151 | - wed_num = <2>; |
| 152 | - reg = <0 0x15010000 0 0x1000>, |
| 153 | - <0 0x15011000 0 0x1000>; |
| 154 | + wed1: wed@15011000 { |
| 155 | + compatible = "mediatek,mt7986-wed", |
| 156 | + "syscon"; |
| 157 | + reg = <0 0x15011000 0 0x1000>; |
| 158 | interrupt-parent = <&gic>; |
| 159 | - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 160 | - <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 161 | - }; |
| 162 | - |
| 163 | - wdma: wdma@15104800 { |
| 164 | - compatible = "mediatek,wed-wdma"; |
| 165 | - reg = <0 0x15104800 0 0x400>, |
| 166 | - <0 0x15104c00 0 0x400>; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 167 | + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 168 | }; |
| 169 | |
| 170 | ap2woccif: ap2woccif@151A5000 { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 171 | @@ -408,6 +396,7 @@ |
| 172 | <&topckgen CK_TOP_CB_SGM_325M>; |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 173 | mediatek,ethsys = <ðsys>; |
| 174 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 175 | + mediatek,wed = <&wed0>, <&wed1>; |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 176 | #reset-cells = <1>; |
| 177 | #address-cells = <1>; |
| 178 | #size-cells = <0>; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 179 | -- |
| 180 | 2.18.0 |
| 181 | |