| developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1 | /* FILE NAME: an8855_reg.h
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| 2 | * PURPOSE:
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| 3 | * It provides AN8855 register definition.
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| 4 | * NOTES:
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| 5 | *
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| 6 | */
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| 7 |
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| 8 | #ifndef AN8855_REG_H
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| 9 | #define AN8855_REG_H
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| 10 |
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| 11 | #define PORT_CTRL_BASE 0x10208000
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| 12 | #define PORT_CTRL_PORT_OFFSET 0x200
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| 13 | #define PORT_CTRL_REG(p, r) (PORT_CTRL_BASE + (p) * PORT_CTRL_PORT_OFFSET + (r))
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| 14 | #define PCR(p) PORT_CTRL_REG(p, 0x04)
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| 15 |
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| 16 | #define PORT_MAC_CTRL_BASE 0x10210000
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| 17 | #define PORT_MAC_CTRL_PORT_OFFSET 0x200
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| 18 | #define PORT_MAC_CTRL_REG(p, r) (PORT_MAC_CTRL_BASE + (p) * PORT_MAC_CTRL_PORT_OFFSET + (r))
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| 19 | #define PMCR(p) PORT_MAC_CTRL_REG(p, 0x00)
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| 20 |
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| 21 | /* Port debug count register */
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| 22 | #define DBG_CNT_BASE 0x3018
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| 23 | #define DBG_CNT_PORT_BASE 0x100
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| 24 | #define DBG_CNT(p) (DBG_CNT_BASE + (p) * DBG_CNT_PORT_BASE)
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| 25 | #define DIS_CLR (1 << 31)
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| 26 |
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| 27 | #define GMACCR (PORT_MAC_CTRL_BASE + 0x30e0)
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| 28 | #define MTCC_LMT_S 8
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| 29 | #define MAX_RX_JUMBO_S 4
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| 30 |
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| 31 | /* Values of MAX_RX_PKT_LEN */
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| 32 | #define RX_PKT_LEN_1518 0
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| 33 | #define RX_PKT_LEN_1536 1
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| 34 | #define RX_PKT_LEN_1522 2
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| 35 | #define RX_PKT_LEN_MAX_JUMBO 3
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| 36 |
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| 37 | /* Fields of PMCR */
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| 38 | #define FORCE_MODE (1 << 31)
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| 39 | #define IPG_CFG_S 20
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| 40 | #define IPG_CFG_M 0x300000
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| 41 | #define EXT_PHY (1 << 19)
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| 42 | #define MAC_MODE (1 << 18)
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| 43 | #define MAC_TX_EN (1 << 16)
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| 44 | #define MAC_RX_EN (1 << 15)
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| 45 | #define MAC_PRE (1 << 14)
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| 46 | #define BKOFF_EN (1 << 12)
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| 47 | #define BACKPR_EN (1 << 11)
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| 48 | #define FORCE_EEE1G (1 << 7)
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| 49 | #define FORCE_EEE100 (1 << 6)
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| 50 | #define FORCE_RX_FC (1 << 5)
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| 51 | #define FORCE_TX_FC (1 << 4)
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| 52 | #define FORCE_SPD_S 28
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| 53 | #define FORCE_SPD_M 0x70000000
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| 54 | #define FORCE_DPX (1 << 25)
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| 55 | #define FORCE_LINK (1 << 24)
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| 56 |
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| 57 | /* Fields of PMSR */
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| 58 | #define EEE1G_STS (1 << 7)
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| 59 | #define EEE100_STS (1 << 6)
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| 60 | #define RX_FC_STS (1 << 5)
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| 61 | #define TX_FC_STS (1 << 4)
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| 62 | #define MAC_SPD_STS_S 28
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| 63 | #define MAC_SPD_STS_M 0x70000000
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| 64 | #define MAC_DPX_STS (1 << 25)
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| 65 | #define MAC_LNK_STS (1 << 24)
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| 66 |
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| 67 | /* Values of MAC_SPD_STS */
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| 68 | #define MAC_SPD_10 0
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| 69 | #define MAC_SPD_100 1
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| 70 | #define MAC_SPD_1000 2
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| 71 | #define MAC_SPD_2500 3
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| 72 |
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| 73 | /* Values of IPG_CFG */
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| 74 | #define IPG_96BIT 0
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| 75 | #define IPG_96BIT_WITH_SHORT_IPG 1
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| 76 | #define IPG_64BIT 2
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| 77 |
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| 78 | #define SGMII_REG_BASE 0x5000
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| 79 | #define SGMII_REG_PORT_BASE 0x1000
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| 80 | #define SGMII_REG(p, r) (SGMII_REG_BASE + (p) * SGMII_REG_PORT_BASE + (r))
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| 81 | #define PCS_CONTROL_1(p) SGMII_REG(p, 0x00)
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| 82 | #define SGMII_MODE(p) SGMII_REG(p, 0x20)
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| 83 | #define QPHY_PWR_STATE_CTRL(p) SGMII_REG(p, 0xe8)
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| 84 | #define PHYA_CTRL_SIGNAL3(p) SGMII_REG(p, 0x128)
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| 85 |
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| 86 | /* Fields of PCS_CONTROL_1 */
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| 87 | #define SGMII_LINK_STATUS (1 << 18)
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| 88 | #define SGMII_AN_ENABLE (1 << 12)
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| 89 | #define SGMII_AN_RESTART (1 << 9)
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| 90 |
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| 91 | /* Fields of SGMII_MODE */
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| 92 | #define SGMII_REMOTE_FAULT_DIS (1 << 8)
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| 93 | #define SGMII_IF_MODE_FORCE_DUPLEX (1 << 4)
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| 94 | #define SGMII_IF_MODE_FORCE_SPEED_S 0x2
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| 95 | #define SGMII_IF_MODE_FORCE_SPEED_M 0x0c
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| 96 | #define SGMII_IF_MODE_ADVERT_AN (1 << 1)
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| 97 |
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| 98 | /* Values of SGMII_IF_MODE_FORCE_SPEED */
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| 99 | #define SGMII_IF_MODE_FORCE_SPEED_10 0
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| 100 | #define SGMII_IF_MODE_FORCE_SPEED_100 1
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| 101 | #define SGMII_IF_MODE_FORCE_SPEED_1000 2
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| 102 |
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| 103 | /* Fields of QPHY_PWR_STATE_CTRL */
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| 104 | #define PHYA_PWD (1 << 4)
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| 105 |
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| 106 | /* Fields of PHYA_CTRL_SIGNAL3 */
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| 107 | #define RG_TPHY_SPEED_S 2
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| 108 | #define RG_TPHY_SPEED_M 0x0c
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| 109 |
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| 110 | /* Values of RG_TPHY_SPEED */
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| 111 | #define RG_TPHY_SPEED_1000 0
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| 112 | #define RG_TPHY_SPEED_2500 1
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| 113 |
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| 114 | #define SYS_CTRL 0x7000
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| 115 | #define SW_PHY_RST (1 << 2)
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| 116 | #define SW_SYS_RST (1 << 1)
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| 117 | #define SW_REG_RST (1 << 0)
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| 118 |
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| 119 | #define PHY_IAC (0x1000e000)
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| 120 | #define IAC_MAX_BUSY_TIME (1000)
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| 121 |
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| 122 | #define CLKGEN_CTRL 0x7500
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| 123 | #define CLK_SKEW_OUT_S 8
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| 124 | #define CLK_SKEW_OUT_M 0x300
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| 125 | #define CLK_SKEW_IN_S 6
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| 126 | #define CLK_SKEW_IN_M 0xc0
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| 127 | #define RXCLK_NO_DELAY (1 << 5)
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| 128 | #define TXCLK_NO_REVERSE (1 << 4)
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| 129 | #define GP_MODE_S 1
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| 130 | #define GP_MODE_M 0x06
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| 131 | #define GP_CLK_EN (1 << 0)
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| 132 |
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| 133 | /* Values of GP_MODE */
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| 134 | #define GP_MODE_RGMII 0
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| 135 | #define GP_MODE_MII 1
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| 136 | #define GP_MODE_REV_MII 2
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| 137 |
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| 138 | /* Values of CLK_SKEW_IN */
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| 139 | #define CLK_SKEW_IN_NO_CHANGE 0
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| 140 | #define CLK_SKEW_IN_DELAY_100PPS 1
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| 141 | #define CLK_SKEW_IN_DELAY_200PPS 2
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| 142 | #define CLK_SKEW_IN_REVERSE 3
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| 143 |
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| 144 | /* Values of CLK_SKEW_OUT */
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| 145 | #define CLK_SKEW_OUT_NO_CHANGE 0
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| 146 | #define CLK_SKEW_OUT_DELAY_100PPS 1
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| 147 | #define CLK_SKEW_OUT_DELAY_200PPS 2
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| 148 | #define CLK_SKEW_OUT_REVERSE 3
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| 149 |
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| 150 | #define HWSTRAP 0x7800
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| 151 | #define XTAL_FSEL_S 7
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| 152 | #define XTAL_FSEL_M (1 << 7)
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| 153 |
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| 154 | #define XTAL_40MHZ 0
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| 155 | #define XTAL_25MHZ 1
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| 156 |
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| 157 | #define PLLGP_EN 0x7820
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| 158 | #define EN_COREPLL (1 << 2)
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| 159 | #define SW_CLKSW (1 << 1)
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| 160 | #define SW_PLLGP (1 << 0)
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| 161 |
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| 162 | #define PLLGP_CR0 0x78a8
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| 163 | #define RG_COREPLL_EN (1 << 22)
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| 164 | #define RG_COREPLL_POSDIV_S 23
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| 165 | #define RG_COREPLL_POSDIV_M 0x3800000
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| 166 | #define RG_COREPLL_SDM_PCW_S 1
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| 167 | #define RG_COREPLL_SDM_PCW_M 0x3ffffe
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| 168 | #define RG_COREPLL_SDM_PCW_CHG (1 << 0)
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| 169 |
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| 170 | #define MHWSTRAP 0x7804
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| 171 | #define TOP_SIG_SR 0x780c
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| 172 | #define PAD_DUAL_SGMII_EN (1 << 1)
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| 173 |
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| 174 | /* RGMII and SGMII PLL clock */
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| 175 | #define ANA_PLLGP_CR2 0x78b0
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| 176 | #define ANA_PLLGP_CR5 0x78bc
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| 177 |
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| 178 | /* Efuse Register Define */
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| 179 | #define GBE_EFUSE 0x7bc8
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| 180 | #define GBE_SEL_EFUSE_EN (1 << 0)
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| 181 |
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| 182 | /* GPIO_PAD_0 */
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| 183 | #define GPIO_MODE0 0x7c0c
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| 184 | #define GPIO_MODE0_S 0
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| 185 | #define GPIO_MODE0_M 0xf
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| 186 | #define GPIO_0_INTERRUPT_MODE 0x1
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| 187 |
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| 188 | #define SMT0_IOLB 0x7f04
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| 189 | #define SMT_IOLB_5_SMI_MDC_EN (1 << 5)
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| 190 |
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| 191 | #endif /* End of AN8855_REG_H */
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