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git01.mediatek.com / filogic / rdk-b / meta-filogic / 617abbdc84135e6594119bf98869f7dded53b6be / . / recipes-wifi / linux-mt76 / files / patches-3.x / 0081-mtk-wifi-mt76-mt7996-add-kite-two-pcie-with-two-wed-.patch
blob: 663b42aa7d579f9cbb663307295c1cd846ac71af [file] [log] [blame]
developer617abbd2024-04-23 14:50:01 +0800[diff] [blame^]1From 3945c5fb09e36f31863f019dc12d242aa4e3644c Mon Sep 17 00:00:00 2001
2From: Rex Lu <rex.lu@mediatek.com>
3Date: Tue, 19 Mar 2024 13:16:12 +0800
4Subject: [PATCH 081/116] mtk: wifi: mt76: mt7996: add kite two pcie with two
5 wed support
6
7CR-Id: WCNCR00259516
8Signed-off-by: Rex Lu <rex.lu@mediatek.com>
9---
10 mt7996/dma.c | 68 ++++++++++++++++++++++++++++++++++++++-------------
11 mt7996/init.c | 54 +++++++++++++++++++++++-----------------
12 mt7996/main.c | 5 ++--
13 mt7996/mmio.c | 15 ++++++++++--
14 mt7996/pci.c | 5 ++--
15 mt7996/regs.h | 1 +
16 6 files changed, 101 insertions(+), 47 deletions(-)
17
18diff --git a/mt7996/dma.c b/mt7996/dma.c
19index 3dc0e8a1d..a2490fa77 100644
20--- a/mt7996/dma.c
21+++ b/mt7996/dma.c
22@@ -108,8 +108,8 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
23 }
24
25 /* data tx queue */
26- TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
27 if (is_mt7996(&dev->mt76)) {
28+ TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
29 if (dev->hif2) {
30 if (dev->option_type == 2) {
31 /* bn1:ring21 bn2:ring19 */
32@@ -125,7 +125,15 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
33 TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
34 }
35 } else {
36- TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
37+ if (dev->hif2) {
38+ /* bn0:ring18 bn1:ring21 */
39+ TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
40+ TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
41+ } else {
42+ /* single pcie bn0:ring18 bn1:ring19 */
43+ TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
44+ TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
45+ }
46 }
47
48 /* mcu tx queue */
49@@ -285,8 +293,11 @@ void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset)
50 if (mt7996_band_valid(dev, MT_BAND0))
51 irq_mask |= MT_INT_BAND0_RX_DONE;
52
53- if (mt7996_band_valid(dev, MT_BAND1))
54+ if (mt7996_band_valid(dev, MT_BAND1)) {
55 irq_mask |= MT_INT_BAND1_RX_DONE;
56+ if (is_mt7992(&dev->mt76) && dev->hif2)
57+ irq_mask |= MT_INT_RX_TXFREE_BAND1_EXT;
58+ }
59
60 if (mt7996_band_valid(dev, MT_BAND2))
61 irq_mask |= MT_INT_BAND2_RX_DONE;
62@@ -379,27 +390,46 @@ static void mt7996_dma_enable(struct mt7996_dev *dev, bool reset)
63 MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 |
64 MT_WFDMA_HOST_CONFIG_BAND2_PCIE1);
65
66- if (dev->option_type == 2)
67- mt76_set(dev, MT_WFDMA_HOST_CONFIG,
68- MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 |
69- MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
70- else
71- mt76_set(dev, MT_WFDMA_HOST_CONFIG,
72- MT_WFDMA_HOST_CONFIG_BAND2_PCIE1);
73-
74- if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
75- is_mt7992(&dev->mt76)) {
76+ switch (dev->option_type) {
77+ case 2:
78+ /* eagle + 7988d */
79+ if (is_mt7996(&dev->mt76))
80+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
81+ MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 |
82+ MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
83+ else
84+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
85+ MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
86+ break;
87+ case 3:
88 mt76_set(dev, MT_WFDMA_HOST_CONFIG,
89- MT_WFDMA_HOST_CONFIG_PDMA_BAND |
90- MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
91+ MT_WFDMA_HOST_CONFIG_BAND0_PCIE1);
92+
93+ break;
94+ default:
95+ if (is_mt7996(&dev->mt76))
96+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
97+ MT_WFDMA_HOST_CONFIG_BAND2_PCIE1);
98+ else
99+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
100+ MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
101+ break;
102 }
103
104 /* AXI read outstanding number */
105 mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL,
106 MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK, 0x14);
107
108- if (dev->hif2->speed < PCIE_SPEED_8_0GT ||
109- (dev->hif2->speed == PCIE_SPEED_8_0GT && dev->hif2->width < 2)) {
110+ if (dev->hif2->speed < PCIE_SPEED_5_0GT ||
111+ (dev->hif2->speed == PCIE_SPEED_5_0GT && dev->hif2->width < 2)) {
112+ mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
113+ WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK,
114+ FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 0x1));
115+ mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2,
116+ MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK,
117+ FIELD_PREP(MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 0x1));
118+ } else if (dev->hif2->speed < PCIE_SPEED_8_0GT ||
119+ (dev->hif2->speed == PCIE_SPEED_8_0GT && dev->hif2->width < 2)) {
120 mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
121 WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK,
122 FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 0x3));
123@@ -648,6 +678,10 @@ int mt7996_dma_init(struct mt7996_dev *dev)
124
125 /* tx free notify event from WA for mt7992 band1 */
126 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;
127+ if (mtk_wed_device_active(wed_hif2)) {
128+ dev->mt76.q_rx[MT_RXQ_BAND1_WA].flags = MT_WED_Q_TXFREE;
129+ dev->mt76.q_rx[MT_RXQ_BAND1_WA].wed = wed_hif2;
130+ }
131 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],
132 MT_RXQ_ID(MT_RXQ_BAND1_WA),
133 MT7996_RX_MCU_RING_SIZE,
134diff --git a/mt7996/init.c b/mt7996/init.c
135index 1e7cd5235..768979ef7 100644
136--- a/mt7996/init.c
137+++ b/mt7996/init.c
138@@ -525,39 +525,46 @@ void mt7996_mac_init(struct mt7996_dev *dev)
139 }
140
141 /* rro module init */
142+ rx_path_type = is_mt7996(&dev->mt76) ? 2 : 7;
143+ rro_bypass = is_mt7996(&dev->mt76) ? 1 : 2;
144+ txfree_path = is_mt7996(&dev->mt76) ? 0: 1;
145+
146 switch (dev->option_type) {
147 case 2:
148- /* eagle + 7988d */
149- rx_path_type = 3;
150- rro_bypass = dev->has_rro ? 1 : 3;
151- txfree_path = dev->has_rro ? 0 : 1;
152+ if (is_mt7996(&dev->mt76)) {
153+ /* eagle + 7988d */
154+ rx_path_type = 3;
155+ rro_bypass = 1;
156+ txfree_path = 0;
157+ }
158 break;
159 case 3:
160- /* eagle + Airoha */
161- rx_path_type = 6;
162- rro_bypass = dev->has_rro ? 1 : 3;
163- txfree_path = dev->has_rro ? 0 : 1;
164+ /* Airoha */
165+ if (is_mt7996(&dev->mt76)) {
166+ rx_path_type = 6;
167+ rro_bypass = 1;
168+ txfree_path = 0;
169+ } else {
170+ rx_path_type = 8;
171+ rro_bypass = 2;
172+ txfree_path = 1;
173+ }
174 break;
175 case 4:
176- /* Bollinger */
177- rx_path_type = 2;
178- rro_bypass = dev->has_rro ? 1 : 3;
179- txfree_path = dev->has_rro ? 0 : 1;
180+ if (is_mt7996(&dev->mt76)) {
181+ /* Bollinger */
182+ rx_path_type = 2;
183+ rro_bypass = 1;
184+ txfree_path = 0;
185+ }
186 break;
187 default:
188- if (is_mt7996(&dev->mt76))
189- rx_path_type = 2;
190- else
191- rx_path_type = 7;
192-
193- rro_bypass = dev->has_rro ? 1 : 3;
194- txfree_path = dev->has_rro ? 0 : 1;
195 break;
196 }
197
198 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, dev->hif2 ? rx_path_type : 0);
199- mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, rro_bypass);
200- mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, txfree_path);
201+ mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, dev->has_rro ? rro_bypass : 3);
202+ mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, dev->has_rro ? txfree_path : 1);
203
204 if (dev->has_rro) {
205 u16 timeout;
206@@ -641,7 +648,7 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
207 if (phy)
208 return 0;
209
210- if (is_mt7996(&dev->mt76) && dev->hif2) {
211+ if (dev->hif2) {
212 switch (dev->option_type) {
213 case 2:
214 /* eagle + 7988d */
215@@ -651,7 +658,8 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
216 }
217 break;
218 default:
219- if (band == MT_BAND2) {
220+ if ((is_mt7996(&dev->mt76) && band == MT_BAND2) ||
221+ (is_mt7992(&dev->mt76) && band == MT_BAND1)) {
222 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
223 wed = &dev->mt76.mmio.wed_hif2;
224 }
225diff --git a/mt7996/main.c b/mt7996/main.c
226index f7ea49f18..2fe9bf28f 100644
227--- a/mt7996/main.c
228+++ b/mt7996/main.c
229@@ -1607,7 +1607,7 @@ mt7996_net_fill_forward_path(struct ieee80211_hw *hw,
230 struct mt7996_phy *phy = mt7996_hw_phy(hw);
231 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
232
233- if (phy != &dev->phy && dev->hif2) {
234+ if (dev->hif2) {
235 switch (dev->option_type) {
236 case 2:
237 /* eagle + 7988d */
238@@ -1615,7 +1615,8 @@ mt7996_net_fill_forward_path(struct ieee80211_hw *hw,
239 wed = &dev->mt76.mmio.wed_hif2;
240 break;
241 default:
242- if (phy->mt76->band_idx == MT_BAND2)
243+ if ((is_mt7996(&dev->mt76) && phy->mt76->band_idx == MT_BAND2) ||
244+ (is_mt7992(&dev->mt76) && phy->mt76->band_idx == MT_BAND1))
245 wed = &dev->mt76.mmio.wed_hif2;
246 break;
247 }
248diff --git a/mt7996/mmio.c b/mt7996/mmio.c
249index 91567a04b..6028182e1 100644
250--- a/mt7996/mmio.c
251+++ b/mt7996/mmio.c
252@@ -336,10 +336,16 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
253 MT_TXQ_RING_BASE(0) +
254 MT7996_TXQ_BAND2 * MT_RING_SIZE;
255 if (dev->has_rro) {
256+ u8 rxq_id = is_mt7996(&dev->mt76) ?
257+ MT7996_RXQ_TXFREE2 : MT7996_RXQ_MCU_WA_EXT;
258+
259 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs +
260 MT_RXQ_RING_BASE(0) +
261- MT7996_RXQ_TXFREE2 * MT_RING_SIZE;
262- wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1;
263+ rxq_id * MT_RING_SIZE;
264+ if (is_mt7996(&dev->mt76))
265+ wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1;
266+ else
267+ wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_BAND1_EXT) - 1;
268 } else {
269 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs +
270 MT_RXQ_RING_BASE(0) +
271@@ -423,6 +429,8 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
272 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE;
273 }
274 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt;
275+ if(dev->hif2 && is_mt7992(&dev->mt76))
276+ wed->wlan.id = 0x7992;
277 }
278
279 wed->wlan.nbuf = MT7996_TOKEN_SIZE;
280@@ -553,6 +561,9 @@ static void mt7996_irq_tasklet(struct tasklet_struct *t)
281
282 if (intr1 & MT_INT_RX_DONE_BAND2_EXT)
283 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]);
284+
285+ if (is_mt7992(&dev->mt76) && (intr1 & MT_INT_RX_TXFREE_BAND1_EXT))
286+ napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
287 }
288
289 if (mtk_wed_device_active(wed)) {
290diff --git a/mt7996/pci.c b/mt7996/pci.c
291index 24d69d4dc..382b6a898 100644
292--- a/mt7996/pci.c
293+++ b/mt7996/pci.c
294@@ -110,7 +110,7 @@ static int mt7996_pci_probe(struct pci_dev *pdev,
295 int irq, ret;
296 struct mt76_dev *mdev;
297
298- hif2_enable |= (id->device == 0x7990 || id->device == 0x7991);
299+ hif2_enable |= (id->device == 0x7990 || id->device == 0x7991 || id->device == 0x799a);
300
301 ret = pcim_enable_device(pdev);
302 if (ret)
303@@ -171,8 +171,7 @@ static int mt7996_pci_probe(struct pci_dev *pdev,
304 hif2_dev = container_of(hif2->dev, struct pci_dev, dev);
305 ret = 0;
306
307- if (is_mt7996(&dev->mt76))
308- ret = mt7996_mmio_wed_init(dev, hif2_dev, true, &irq);
309+ ret = mt7996_mmio_wed_init(dev, hif2_dev, true, &irq);
310
311 if (ret < 0)
312 goto free_wed_or_irq_vector;
313diff --git a/mt7996/regs.h b/mt7996/regs.h
314index a0e4b3e11..e18935172 100644
315--- a/mt7996/regs.h
316+++ b/mt7996/regs.h
317@@ -525,6 +525,7 @@ enum offs_rev {
318 #define MT_INT_RX_TXFREE_MAIN BIT(17)
319 #define MT_INT_RX_TXFREE_BAND1 BIT(15)
320 #define MT_INT_RX_TXFREE_TRI BIT(15)
321+#define MT_INT_RX_TXFREE_BAND1_EXT BIT(19) /* for mt7992 two PCIE*/
322 #define MT_INT_RX_DONE_BAND2_EXT BIT(23)
323 #define MT_INT_RX_TXFREE_EXT BIT(26)
324 #define MT_INT_MCU_CMD BIT(29)
325--
3262.39.2
327