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developer2cbf2fb2022-11-16 12:20:48 +08001From 8758539453946b5e3941f2e46d7ae4f933823dd2 Mon Sep 17 00:00:00 2001
developer42b63282022-06-16 13:33:13 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Thu, 21 Apr 2022 15:43:19 +0800
developer2cbf2fb2022-11-16 12:20:48 +08004Subject: [PATCH 1111/1128] mt76: testmode: additional supports
developer42b63282022-06-16 13:33:13 +08005
6Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
7---
developer4df64ba2022-09-01 14:44:55 +08008 dma.c | 3 +-
9 mac80211.c | 12 +
10 mt76.h | 108 ++++-
11 mt76_connac_mcu.c | 4 +
12 mt76_connac_mcu.h | 2 +
13 mt7915/init.c | 2 +-
developer2cbf2fb2022-11-16 12:20:48 +080014 mt7915/mac.c | 37 +-
developer4df64ba2022-09-01 14:44:55 +080015 mt7915/main.c | 2 +-
16 mt7915/mcu.c | 10 +-
17 mt7915/mcu.h | 28 +-
18 mt7915/mmio.c | 2 +
19 mt7915/mt7915.h | 14 +-
20 mt7915/regs.h | 3 +
21 mt7915/testmode.c | 1171 ++++++++++++++++++++++++++++++++++++++++++---
22 mt7915/testmode.h | 278 +++++++++++
23 testmode.c | 275 +++++++++--
24 testmode.h | 75 +++
25 tools/fields.c | 80 ++++
26 tx.c | 3 +-
developer2cbf2fb2022-11-16 12:20:48 +080027 19 files changed, 1962 insertions(+), 147 deletions(-)
developer42b63282022-06-16 13:33:13 +080028
29diff --git a/dma.c b/dma.c
developer29344f12022-10-17 12:01:44 +080030index 4b181305..82b4da26 100644
developer42b63282022-06-16 13:33:13 +080031--- a/dma.c
32+++ b/dma.c
33@@ -426,8 +426,7 @@ free:
34 if (mt76_is_testmode_skb(dev, skb, &hw)) {
35 struct mt76_phy *phy = hw->priv;
36
37- if (tx_info.skb == phy->test.tx_skb)
38- phy->test.tx_done--;
39+ phy->test.tx_done--;
40 }
41 #endif
42
43diff --git a/mac80211.c b/mac80211.c
developer2cbf2fb2022-11-16 12:20:48 +080044index e5d8f45b..4b63ec69 100644
developer42b63282022-06-16 13:33:13 +080045--- a/mac80211.c
46+++ b/mac80211.c
47@@ -55,6 +55,13 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
48 CHAN5G(60, 5300),
49 CHAN5G(64, 5320),
50
51+ CHAN5G(68, 5340),
52+ CHAN5G(80, 5400),
53+ CHAN5G(84, 5420),
54+ CHAN5G(88, 5440),
55+ CHAN5G(92, 5460),
56+ CHAN5G(96, 5480),
57+
58 CHAN5G(100, 5500),
59 CHAN5G(104, 5520),
60 CHAN5G(108, 5540),
61@@ -75,6 +82,11 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
62 CHAN5G(165, 5825),
63 CHAN5G(169, 5845),
64 CHAN5G(173, 5865),
65+
66+ CHAN5G(184, 4920),
67+ CHAN5G(188, 4940),
68+ CHAN5G(192, 4960),
69+ CHAN5G(196, 4980),
70 };
71
72 static const struct ieee80211_channel mt76_channels_6ghz[] = {
73diff --git a/mt76.h b/mt76.h
developer2cbf2fb2022-11-16 12:20:48 +080074index 3a177fff..e79d74a4 100644
developer42b63282022-06-16 13:33:13 +080075--- a/mt76.h
76+++ b/mt76.h
developerf1313102022-10-11 11:02:55 +080077@@ -624,6 +624,21 @@ struct mt76_testmode_ops {
developer42b63282022-06-16 13:33:13 +080078 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
79 enum mt76_testmode_state new_state);
80 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
81+ int (*set_eeprom)(struct mt76_phy *phy, u32 offset, u8 *val, u8 action);
82+};
83+
84+struct mt76_testmode_entry_data {
85+ struct sk_buff *tx_skb;
86+
87+ u16 tx_mpdu_len;
88+ u8 tx_rate_idx;
89+ u8 tx_rate_nss;
90+ u8 tx_rate_ldpc;
91+
92+ u8 addr[3][ETH_ALEN];
93+ u8 aid;
94+ u8 ru_alloc;
95+ u8 ru_idx;
96 };
97
98 #define MT_TM_FW_RX_COUNT BIT(0)
developerf1313102022-10-11 11:02:55 +080099@@ -632,16 +647,11 @@ struct mt76_testmode_data {
developer42b63282022-06-16 13:33:13 +0800100 enum mt76_testmode_state state;
101
102 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
103- struct sk_buff *tx_skb;
104
105 u32 tx_count;
106- u16 tx_mpdu_len;
107
108 u8 tx_rate_mode;
109- u8 tx_rate_idx;
110- u8 tx_rate_nss;
111 u8 tx_rate_sgi;
112- u8 tx_rate_ldpc;
113 u8 tx_rate_stbc;
114 u8 tx_ltf;
115
developerf1313102022-10-11 11:02:55 +0800116@@ -657,10 +667,37 @@ struct mt76_testmode_data {
developer42b63282022-06-16 13:33:13 +0800117 u8 tx_power[4];
118 u8 tx_power_control;
119
120- u8 addr[3][ETH_ALEN];
121+ struct list_head tm_entry_list;
122+ struct mt76_wcid *cur_entry;
123+ u8 entry_num;
124+ union {
125+ struct mt76_testmode_entry_data ed;
126+ struct {
127+ /* must be the same as mt76_testmode_entry_data */
128+ struct sk_buff *tx_skb;
129+
130+ u16 tx_mpdu_len;
131+ u8 tx_rate_idx;
132+ u8 tx_rate_nss;
133+ u8 tx_rate_ldpc;
134+
135+ u8 addr[3][ETH_ALEN];
136+ u8 aid;
137+ u8 ru_alloc;
138+ u8 ru_idx;
139+ };
140+ };
141
142 u8 flag;
143
144+ struct {
145+ u8 type;
146+ u8 enable;
147+ } cfg;
148+
149+ u8 txbf_act;
150+ u16 txbf_param[8];
151+
152 u32 tx_pending;
153 u32 tx_queued;
154 u16 tx_queued_limit;
developerf1313102022-10-11 11:02:55 +0800155@@ -1115,6 +1152,59 @@ static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +0800156 #endif
157 }
158
159+#ifdef CONFIG_NL80211_TESTMODE
160+static inline struct mt76_wcid *
161+mt76_testmode_first_entry(struct mt76_phy *phy)
162+{
163+ if (list_empty(&phy->test.tm_entry_list) && !phy->test.aid)
164+ return &phy->dev->global_wcid;
165+
166+ return list_first_entry(&phy->test.tm_entry_list,
167+ typeof(struct mt76_wcid),
168+ list);
169+}
170+
171+static inline struct mt76_testmode_entry_data *
172+mt76_testmode_entry_data(struct mt76_phy *phy, struct mt76_wcid *wcid)
173+{
174+ if (!wcid)
175+ return NULL;
176+ if (wcid == &phy->dev->global_wcid)
177+ return &phy->test.ed;
178+
179+ return (struct mt76_testmode_entry_data *)((u8 *)wcid +
180+ phy->hw->sta_data_size);
181+}
182+
183+#define mt76_tm_for_each_entry(phy, wcid, ed) \
184+ for (wcid = mt76_testmode_first_entry(phy), \
185+ ed = mt76_testmode_entry_data(phy, wcid); \
186+ ((phy->test.aid && \
187+ !list_entry_is_head(wcid, &phy->test.tm_entry_list, list)) || \
188+ (!phy->test.aid && wcid == &phy->dev->global_wcid)) && ed; \
189+ wcid = list_next_entry(wcid, list), \
190+ ed = mt76_testmode_entry_data(phy, wcid))
191+#endif
192+
193+static inline bool __mt76_is_testmode_skb(struct mt76_phy *phy,
194+ struct sk_buff *skb)
195+{
196+#ifdef CONFIG_NL80211_TESTMODE
197+ struct mt76_testmode_entry_data *ed = &phy->test.ed;
198+ struct mt76_wcid *wcid;
199+
200+ if (skb == ed->tx_skb)
201+ return true;
202+
203+ mt76_tm_for_each_entry(phy, wcid, ed)
204+ if (skb == ed->tx_skb)
205+ return true;
206+ return false;
207+#else
208+ return false;
209+#endif
210+}
211+
212 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
213 struct sk_buff *skb,
214 struct ieee80211_hw **hw)
developerf1313102022-10-11 11:02:55 +0800215@@ -1125,7 +1215,8 @@ static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
developer4df64ba2022-09-01 14:44:55 +0800216 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
217 struct mt76_phy *phy = dev->phys[i];
218
219- if (phy && skb == phy->test.tx_skb) {
220+ if (phy && mt76_testmode_enabled(phy) &&
221+ __mt76_is_testmode_skb(phy, skb)) {
222 *hw = dev->phys[i]->hw;
223 return true;
224 }
developer2cbf2fb2022-11-16 12:20:48 +0800225@@ -1227,7 +1318,8 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +0800226 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
227 struct netlink_callback *cb, void *data, int len);
228 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
229-int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
230+int mt76_testmode_init_skb(struct mt76_phy *phy, u32 len,
231+ struct sk_buff **tx_skb, u8 (*addr)[ETH_ALEN]);
232
233 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
234 {
235diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developer2cbf2fb2022-11-16 12:20:48 +0800236index 7ab491d6..afdd42ff 100644
developer42b63282022-06-16 13:33:13 +0800237--- a/mt76_connac_mcu.c
238+++ b/mt76_connac_mcu.c
developer33907d42022-09-19 14:33:58 +0800239@@ -393,6 +393,7 @@ void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
developer42b63282022-06-16 13:33:13 +0800240 switch (vif->type) {
241 case NL80211_IFTYPE_MESH_POINT:
242 case NL80211_IFTYPE_AP:
243+ case NL80211_IFTYPE_MONITOR:
244 if (vif->p2p)
245 conn_type = CONNECTION_P2P_GC;
246 else
developer33907d42022-09-19 14:33:58 +0800247@@ -574,6 +575,9 @@ void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev,
developer42b63282022-06-16 13:33:13 +0800248 rx->rca2 = 1;
249 rx->rv = 1;
250
251+ if (vif->type == NL80211_IFTYPE_MONITOR)
252+ rx->rca1 = 0;
253+
254 if (!is_connac_v1(dev))
255 return;
256
257diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developer2cbf2fb2022-11-16 12:20:48 +0800258index c4262f39..858a2676 100644
developer42b63282022-06-16 13:33:13 +0800259--- a/mt76_connac_mcu.h
260+++ b/mt76_connac_mcu.h
developer2cbf2fb2022-11-16 12:20:48 +0800261@@ -980,6 +980,7 @@ enum {
developer42b63282022-06-16 13:33:13 +0800262 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
263 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
264 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
265+ MCU_EXT_EVENT_BF_STATUS_READ = 0x35,
266 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
267 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
268 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
developer2cbf2fb2022-11-16 12:20:48 +0800269@@ -1158,6 +1159,7 @@ enum {
developer42b63282022-06-16 13:33:13 +0800270 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
271 /* for vendor csi and air monitor */
272 MCU_EXT_CMD_SMESH_CTRL = 0xae,
273+ MCU_EXT_CMD_RX_STAT_USER_CTRL = 0xb3,
274 MCU_EXT_CMD_CERT_CFG = 0xb7,
275 MCU_EXT_CMD_CSI_CTRL = 0xc2,
276 };
277diff --git a/mt7915/init.c b/mt7915/init.c
developer2cbf2fb2022-11-16 12:20:48 +0800278index 442e19e8..69465dd0 100644
developer42b63282022-06-16 13:33:13 +0800279--- a/mt7915/init.c
280+++ b/mt7915/init.c
developer2cbf2fb2022-11-16 12:20:48 +0800281@@ -600,7 +600,7 @@ static void mt7915_init_work(struct work_struct *work)
developer42b63282022-06-16 13:33:13 +0800282 struct mt7915_dev *dev = container_of(work, struct mt7915_dev,
283 init_work);
284
285- mt7915_mcu_set_eeprom(dev);
286+ mt7915_mcu_set_eeprom(dev, dev->flash_mode);
287 mt7915_mac_init(dev);
288 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband);
289 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband);
290diff --git a/mt7915/mac.c b/mt7915/mac.c
developer2cbf2fb2022-11-16 12:20:48 +0800291index d0aa305a..9af86163 100644
developer42b63282022-06-16 13:33:13 +0800292--- a/mt7915/mac.c
293+++ b/mt7915/mac.c
developer2cbf2fb2022-11-16 12:20:48 +0800294@@ -597,16 +597,38 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
developer42b63282022-06-16 13:33:13 +0800295 {
296 #ifdef CONFIG_NL80211_TESTMODE
297 struct mt76_testmode_data *td = &phy->mt76->test;
298+ struct mt76_testmode_entry_data *ed;
299+ struct mt76_wcid *wcid;
300 const struct ieee80211_rate *r;
301- u8 bw, mode, nss = td->tx_rate_nss;
302- u8 rate_idx = td->tx_rate_idx;
303+ u8 bw, mode, nss, rate_idx, ldpc;
304 u16 rateval = 0;
305 u32 val;
306 bool cck = false;
307 int band;
308
309- if (skb != phy->mt76->test.tx_skb)
310+ txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
311+ txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
312+ phy->test.spe_idx));
313+
314+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU) {
315+ txwi[1] |= cpu_to_le32(BIT(18));
316+ txwi[2] = 0;
317+ txwi[3] &= ~cpu_to_le32(MT_TXD3_NO_ACK);
318+ le32p_replace_bits(&txwi[3], 0x1f, MT_TXD3_REM_TX_COUNT);
319+
developer4df64ba2022-09-01 14:44:55 +0800320 return;
developer42b63282022-06-16 13:33:13 +0800321+ }
322+
323+ mt76_tm_for_each_entry(phy->mt76, wcid, ed)
324+ if (ed->tx_skb == skb)
325+ break;
326+
327+ if (!ed)
developer4df64ba2022-09-01 14:44:55 +0800328+ return;
329+
developer42b63282022-06-16 13:33:13 +0800330+ nss = ed->tx_rate_nss;
331+ rate_idx = ed->tx_rate_idx;
332+ ldpc = ed->tx_rate_ldpc;
developer4df64ba2022-09-01 14:44:55 +0800333
developer42b63282022-06-16 13:33:13 +0800334 switch (td->tx_rate_mode) {
335 case MT76_TM_TX_MODE_HT:
developer2cbf2fb2022-11-16 12:20:48 +0800336@@ -696,13 +718,14 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
developer42b63282022-06-16 13:33:13 +0800337 if (mode >= MT_PHY_TYPE_HE_SU)
338 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf);
339
340- if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
341+ if (ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
342 val |= MT_TXD6_LDPC;
343
developer4df64ba2022-09-01 14:44:55 +0800344 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
developer42b63282022-06-16 13:33:13 +0800345+ if (phy->test.bf_en)
346+ val |= MT_TXD6_TX_IBF | MT_TXD6_TX_EBF;
347+
348 txwi[6] |= cpu_to_le32(val);
349- txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
350- phy->test.spe_idx));
351 #endif
352 }
353
developer2cbf2fb2022-11-16 12:20:48 +0800354@@ -1452,7 +1475,7 @@ mt7915_mac_restart(struct mt7915_dev *dev)
355 goto out;
356
357 /* set the necessary init items */
358- ret = mt7915_mcu_set_eeprom(dev);
359+ ret = mt7915_mcu_set_eeprom(dev, dev->flash_mode);
360 if (ret)
361 goto out;
362
developer42b63282022-06-16 13:33:13 +0800363diff --git a/mt7915/main.c b/mt7915/main.c
developer2cbf2fb2022-11-16 12:20:48 +0800364index 97bf5117..b4564e33 100644
developer42b63282022-06-16 13:33:13 +0800365--- a/mt7915/main.c
366+++ b/mt7915/main.c
developer2cbf2fb2022-11-16 12:20:48 +0800367@@ -223,7 +223,7 @@ static int mt7915_add_interface(struct ieee80211_hw *hw,
developer42b63282022-06-16 13:33:13 +0800368 mvif->phy = phy;
369 mvif->mt76.band_idx = phy->band_idx;
370
371- mvif->mt76.wmm_idx = vif->type != NL80211_IFTYPE_AP;
372+ mvif->mt76.wmm_idx = (vif->type != NL80211_IFTYPE_AP && vif->type != NL80211_IFTYPE_MONITOR);
373 if (ext_phy)
374 mvif->mt76.wmm_idx += 2;
375
376diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer2cbf2fb2022-11-16 12:20:48 +0800377index 2a18dd53..adc14d53 100644
developer42b63282022-06-16 13:33:13 +0800378--- a/mt7915/mcu.c
379+++ b/mt7915/mcu.c
developer2cbf2fb2022-11-16 12:20:48 +0800380@@ -363,6 +363,11 @@ mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
developer42b63282022-06-16 13:33:13 +0800381 case MCU_EXT_EVENT_BCC_NOTIFY:
382 mt7915_mcu_rx_bcc_notify(dev, skb);
383 break;
384+#ifdef CONFIG_NL80211_TESTMODE
385+ case MCU_EXT_EVENT_BF_STATUS_READ:
386+ mt7915_tm_txbf_status_read(dev, skb);
387+ break;
388+#endif
389 default:
390 break;
391 }
developer2cbf2fb2022-11-16 12:20:48 +0800392@@ -394,6 +399,7 @@ void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb)
developer42b63282022-06-16 13:33:13 +0800393 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP ||
394 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC ||
395 rxd->ext_eid == MCU_EXT_EVENT_BCC_NOTIFY ||
396+ rxd->ext_eid == MCU_EXT_EVENT_BF_STATUS_READ ||
397 !rxd->seq)
398 mt7915_mcu_rx_unsolicited_event(dev, skb);
399 else
developer2cbf2fb2022-11-16 12:20:48 +0800400@@ -2755,14 +2761,14 @@ static int mt7915_mcu_set_eeprom_flash(struct mt7915_dev *dev)
developer42b63282022-06-16 13:33:13 +0800401 return 0;
402 }
403
404-int mt7915_mcu_set_eeprom(struct mt7915_dev *dev)
405+int mt7915_mcu_set_eeprom(struct mt7915_dev *dev, bool flash_mode)
406 {
407 struct mt7915_mcu_eeprom req = {
408 .buffer_mode = EE_MODE_EFUSE,
409 .format = EE_FORMAT_WHOLE,
410 };
411
412- if (dev->flash_mode)
413+ if (flash_mode)
414 return mt7915_mcu_set_eeprom_flash(dev);
415
416 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EFUSE_BUFFER_MODE),
417diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer2cbf2fb2022-11-16 12:20:48 +0800418index 8eaf984a..1388eda0 100644
developer42b63282022-06-16 13:33:13 +0800419--- a/mt7915/mcu.h
420+++ b/mt7915/mcu.h
developeraace7f52022-06-24 13:40:42 +0800421@@ -8,10 +8,15 @@
developer42b63282022-06-16 13:33:13 +0800422
423 enum {
424 MCU_ATE_SET_TRX = 0x1,
425+ MCU_ATE_SET_TSSI = 0x5,
426+ MCU_ATE_SET_DPD = 0x6,
427+ MCU_ATE_SET_RATE_POWER_OFFSET = 0x7,
428+ MCU_ATE_SET_THERMAL_COMP = 0x8,
429 MCU_ATE_SET_FREQ_OFFSET = 0xa,
430 MCU_ATE_SET_PHY_COUNT = 0x11,
431 MCU_ATE_SET_SLOT_TIME = 0x13,
432 MCU_ATE_CLEAN_TXQUEUE = 0x1c,
433+ MCU_ATE_SET_MU_RX_AID = 0x1e,
434 };
435
developeraace7f52022-06-24 13:40:42 +0800436 struct mt7915_mcu_thermal_ctrl {
developer2cbf2fb2022-11-16 12:20:48 +0800437@@ -434,6 +439,12 @@ enum {
developer42b63282022-06-16 13:33:13 +0800438
439 enum {
440 MT_BF_SOUNDING_ON = 1,
441+ MT_BF_DATA_PACKET_APPLY = 2,
442+ MT_BF_PFMU_TAG_READ = 5,
443+ MT_BF_PFMU_TAG_WRITE = 6,
444+ MT_BF_PHASE_CAL = 14,
445+ MT_BF_IBF_PHASE_COMP = 15,
446+ MT_BF_PROFILE_WRITE_ALL = 17,
447 MT_BF_TYPE_UPDATE = 20,
448 MT_BF_MODULE_UPDATE = 25
449 };
developer2cbf2fb2022-11-16 12:20:48 +0800450@@ -668,10 +679,19 @@ struct mt7915_muru {
developer42b63282022-06-16 13:33:13 +0800451 #define MURU_OFDMA_SCH_TYPE_UL BIT(1)
452
developeraace7f52022-06-24 13:40:42 +0800453 /* Common Config */
developer42b63282022-06-16 13:33:13 +0800454-#define MURU_COMM_PPDU_FMT BIT(0)
455-#define MURU_COMM_SCH_TYPE BIT(1)
456-#define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_SCH_TYPE)
developer42b63282022-06-16 13:33:13 +0800457-/* DL&UL User config*/
developer42b63282022-06-16 13:33:13 +0800458+/* #define MURU_COMM_PPDU_FMT BIT(0) */
459+/* #define MURU_COMM_SCH_TYPE BIT(1) */
460+/* #define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_SCH_TYPE) */
developeraace7f52022-06-24 13:40:42 +0800461+#define MURU_COMM_PPDU_FMT BIT(0)
462+#define MURU_COMM_SCH_TYPE BIT(1)
463+#define MURU_COMM_BAND BIT(2)
464+#define MURU_COMM_WMM BIT(3)
465+#define MURU_COMM_SPE_IDX BIT(4)
466+#define MURU_COMM_PROC_TYPE BIT(5)
467+#define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_BAND | \
468+ MURU_COMM_WMM | MURU_COMM_SPE_IDX)
developer42b63282022-06-16 13:33:13 +0800469+
470+/* DL&UL User config */
471 #define MURU_USER_CNT BIT(4)
472
473 enum {
474diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer2cbf2fb2022-11-16 12:20:48 +0800475index 813d6f40..63b66e40 100644
developer42b63282022-06-16 13:33:13 +0800476--- a/mt7915/mmio.c
477+++ b/mt7915/mmio.c
developer2cbf2fb2022-11-16 12:20:48 +0800478@@ -127,6 +127,7 @@ static const u32 mt7915_offs[] = {
developer42b63282022-06-16 13:33:13 +0800479 [ARB_DRNGR0] = 0x194,
480 [ARB_SCR] = 0x080,
481 [RMAC_MIB_AIRTIME14] = 0x3b8,
482+ [AGG_AALCR0] = 0x048,
483 [AGG_AWSCR0] = 0x05c,
484 [AGG_PCR0] = 0x06c,
485 [AGG_ACR0] = 0x084,
developer2cbf2fb2022-11-16 12:20:48 +0800486@@ -202,6 +203,7 @@ static const u32 mt7916_offs[] = {
developer42b63282022-06-16 13:33:13 +0800487 [ARB_DRNGR0] = 0x1e0,
488 [ARB_SCR] = 0x000,
489 [RMAC_MIB_AIRTIME14] = 0x0398,
490+ [AGG_AALCR0] = 0x028,
491 [AGG_AWSCR0] = 0x030,
492 [AGG_PCR0] = 0x040,
493 [AGG_ACR0] = 0x054,
494diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer2cbf2fb2022-11-16 12:20:48 +0800495index 6458e356..0217c6c3 100644
developer42b63282022-06-16 13:33:13 +0800496--- a/mt7915/mt7915.h
497+++ b/mt7915/mt7915.h
developer2cbf2fb2022-11-16 12:20:48 +0800498@@ -314,6 +314,9 @@ struct mt7915_phy {
developer42b63282022-06-16 13:33:13 +0800499 u8 last_snr;
500
501 u8 spe_idx;
502+
503+ bool bf_en;
504+ bool bf_ever_en;
505 } test;
506 #endif
507
developer2cbf2fb2022-11-16 12:20:48 +0800508@@ -413,6 +416,14 @@ struct mt7915_dev {
developer42b63282022-06-16 13:33:13 +0800509 void __iomem *dcm;
510 void __iomem *sku;
511
512+#ifdef CONFIG_NL80211_TESTMODE
513+ struct {
514+ void *txbf_phase_cal;
515+ void *txbf_pfmu_data;
516+ void *txbf_pfmu_tag;
517+ } test;
518+#endif
519+
520 #ifdef MTK_DEBUG
521 u16 wlan_idx;
522 struct {
developer2cbf2fb2022-11-16 12:20:48 +0800523@@ -584,7 +595,7 @@ int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev,
developer42b63282022-06-16 13:33:13 +0800524 struct ieee80211_vif *vif,
525 struct ieee80211_sta *sta,
526 void *data, u32 field);
527-int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);
528+int mt7915_mcu_set_eeprom(struct mt7915_dev *dev, bool flash_mode);
529 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset);
530 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num);
531 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,
developer2cbf2fb2022-11-16 12:20:48 +0800532@@ -617,6 +628,7 @@ int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);
developer42b63282022-06-16 13:33:13 +0800533 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
534 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
535 void mt7915_mcu_exit(struct mt7915_dev *dev);
536+int mt7915_tm_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb);
537
538 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
539 {
540diff --git a/mt7915/regs.h b/mt7915/regs.h
developer2cbf2fb2022-11-16 12:20:48 +0800541index 947f02f2..3bf9e150 100644
developer42b63282022-06-16 13:33:13 +0800542--- a/mt7915/regs.h
543+++ b/mt7915/regs.h
developer2cbf2fb2022-11-16 12:20:48 +0800544@@ -61,6 +61,7 @@ enum offs_rev {
developer42b63282022-06-16 13:33:13 +0800545 ARB_DRNGR0,
546 ARB_SCR,
547 RMAC_MIB_AIRTIME14,
548+ AGG_AALCR0,
549 AGG_AWSCR0,
550 AGG_PCR0,
551 AGG_ACR0,
developer2cbf2fb2022-11-16 12:20:48 +0800552@@ -481,6 +482,8 @@ enum offs_rev {
developer42b63282022-06-16 13:33:13 +0800553 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
554 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
555
556+#define MT_AGG_AALCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AALCR0) + \
557+ (_n) * 4))
558 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \
559 (_n) * 4))
560 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \
561diff --git a/mt7915/testmode.c b/mt7915/testmode.c
developer29344f12022-10-17 12:01:44 +0800562index 8d99edcb..8f250db1 100644
developer42b63282022-06-16 13:33:13 +0800563--- a/mt7915/testmode.c
564+++ b/mt7915/testmode.c
565@@ -9,6 +9,9 @@
566 enum {
567 TM_CHANGED_TXPOWER,
568 TM_CHANGED_FREQ_OFFSET,
569+ TM_CHANGED_AID,
570+ TM_CHANGED_CFG,
571+ TM_CHANGED_TXBF_ACT,
572
573 /* must be last */
574 NUM_TM_CHANGED
575@@ -17,6 +20,9 @@ enum {
576 static const u8 tm_change_map[] = {
577 [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER,
578 [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET,
579+ [TM_CHANGED_AID] = MT76_TM_ATTR_AID,
580+ [TM_CHANGED_CFG] = MT76_TM_ATTR_CFG,
581+ [TM_CHANGED_TXBF_ACT] = MT76_TM_ATTR_TXBF_ACT,
582 };
583
584 struct reg_band {
585@@ -33,6 +39,38 @@ struct reg_band {
586 #define TM_REG_MAX_ID 20
587 static struct reg_band reg_backup_list[TM_REG_MAX_ID];
588
589+static void mt7915_tm_update_entry(struct mt7915_phy *phy);
590+
591+static u8 mt7915_tm_chan_bw(enum nl80211_chan_width width)
592+{
593+ static const u8 width_to_bw[] = {
594+ [NL80211_CHAN_WIDTH_40] = TM_CBW_40MHZ,
595+ [NL80211_CHAN_WIDTH_80] = TM_CBW_80MHZ,
596+ [NL80211_CHAN_WIDTH_80P80] = TM_CBW_8080MHZ,
597+ [NL80211_CHAN_WIDTH_160] = TM_CBW_160MHZ,
598+ [NL80211_CHAN_WIDTH_5] = TM_CBW_5MHZ,
599+ [NL80211_CHAN_WIDTH_10] = TM_CBW_10MHZ,
600+ [NL80211_CHAN_WIDTH_20] = TM_CBW_20MHZ,
601+ [NL80211_CHAN_WIDTH_20_NOHT] = TM_CBW_20MHZ,
602+ };
603+
604+ if (width >= ARRAY_SIZE(width_to_bw))
605+ return 0;
606+
607+ return width_to_bw[width];
608+}
609+
610+static void
611+mt7915_tm_update_channel(struct mt7915_phy *phy)
612+{
613+ mutex_unlock(&phy->dev->mt76.mutex);
614+ mt7915_set_channel(phy);
615+ mutex_lock(&phy->dev->mt76.mutex);
616+
617+ mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));
618+
619+ mt7915_tm_update_entry(phy);
620+}
621
622 static int
623 mt7915_tm_set_tx_power(struct mt7915_phy *phy)
624@@ -119,18 +157,28 @@ mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en)
625 }
626
627 static int
628-mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid)
629+mt7915_tm_clean_hwq(struct mt7915_phy *phy)
630 {
631+ struct mt76_testmode_entry_data *ed;
632+ struct mt76_wcid *wcid;
633 struct mt7915_dev *dev = phy->dev;
634 struct mt7915_tm_cmd req = {
635 .testmode_en = 1,
636 .param_idx = MCU_ATE_CLEAN_TXQUEUE,
637- .param.clean.wcid = wcid,
638 .param.clean.band = phy != &dev->phy,
639 };
640
641- return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
642- sizeof(req), false);
643+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
644+ int ret;
645+
646+ req.param.clean.wcid = wcid->idx;
647+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL),
648+ &req, sizeof(req), false);
649+ if (ret)
650+ return ret;
651+ }
652+
653+ return 0;
654 }
655
656 static int
developeraace7f52022-06-24 13:40:42 +0800657@@ -182,12 +230,738 @@ mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu)
developer42b63282022-06-16 13:33:13 +0800658 return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode);
659 }
660
661+static int
662+mt7915_tm_set_cfg(struct mt7915_phy *phy)
663+{
664+ static const u8 cfg_cmd[] = {
665+ [MT76_TM_CFG_TSSI] = MCU_ATE_SET_TSSI,
666+ [MT76_TM_CFG_DPD] = MCU_ATE_SET_DPD,
667+ [MT76_TM_CFG_RATE_POWER_OFFSET] = MCU_ATE_SET_RATE_POWER_OFFSET,
668+ [MT76_TM_CFG_THERMAL_COMP] = MCU_ATE_SET_THERMAL_COMP,
669+ };
670+ struct mt76_testmode_data *td = &phy->mt76->test;
671+ struct mt7915_dev *dev = phy->dev;
672+ struct mt7915_tm_cmd req = {
673+ .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF),
674+ .param_idx = cfg_cmd[td->cfg.type],
675+ .param.cfg.enable = td->cfg.enable,
676+ .param.cfg.band = phy->band_idx,
677+ };
678+
679+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
680+ sizeof(req), false);
681+}
682+
683+static int
684+mt7915_tm_add_txbf(struct mt7915_phy *phy, struct ieee80211_vif *vif,
685+ struct ieee80211_sta *sta, u8 pfmu_idx, u8 nr,
686+ u8 nc, bool ebf)
687+{
688+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
689+ struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
690+ struct mt7915_dev *dev = phy->dev;
691+ struct sk_buff *skb;
692+ struct sta_rec_bf *bf;
693+ struct tlv *tlv;
694+ u8 ndp_rate;
695+
696+ if (nr == 1)
697+ ndp_rate = 8;
698+ else if (nr == 2)
699+ ndp_rate = 16;
700+ else
701+ ndp_rate = 24;
702+
703+ skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
704+ &msta->wcid);
705+ if (IS_ERR(skb))
706+ return PTR_ERR(skb);
707+
708+ tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_BF, sizeof(*bf));
709+ bf = (struct sta_rec_bf *)tlv;
710+
711+ bf->pfmu = cpu_to_le16(pfmu_idx);
712+ bf->sounding_phy = 1;
713+ bf->bf_cap = ebf;
714+ bf->ncol = nc;
715+ bf->nrow = nr;
716+ bf->ndp_rate = ndp_rate;
717+ bf->ibf_timeout = 0xff;
718+ bf->tx_mode = MT_PHY_TYPE_HT;
719+
720+ if (ebf) {
721+ bf->mem[0].row = 0;
722+ bf->mem[1].row = 1;
723+ bf->mem[2].row = 2;
724+ bf->mem[3].row = 3;
725+ } else {
726+ bf->mem[0].row = 4;
727+ bf->mem[1].row = 5;
728+ bf->mem[2].row = 6;
729+ bf->mem[3].row = 7;
730+ }
731+
732+ return mt76_mcu_skb_send_msg(&dev->mt76, skb,
733+ MCU_EXT_CMD(STA_REC_UPDATE), true);
734+}
735+
736+static int
737+mt7915_tm_entry_add(struct mt7915_phy *phy, u8 aid)
738+{
739+ struct mt76_testmode_data *td = &phy->mt76->test;
740+ struct mt76_testmode_entry_data *ed;
741+ struct ieee80211_sband_iftype_data *sdata;
742+ struct ieee80211_supported_band *sband;
743+ struct ieee80211_sta *sta;
744+ struct mt7915_sta *msta;
745+ int tid, ret;
746+
747+ if (td->entry_num >= MT76_TM_MAX_ENTRY_NUM)
748+ return -EINVAL;
749+
750+ sta = kzalloc(sizeof(*sta) + phy->mt76->hw->sta_data_size +
751+ sizeof(*ed), GFP_KERNEL);
752+ if (!sta)
753+ return -ENOMEM;
754+
755+ msta = (struct mt7915_sta *)sta->drv_priv;
756+ ed = mt76_testmode_entry_data(phy->mt76, &msta->wcid);
757+ memcpy(ed, &td->ed, sizeof(*ed));
758+
759+ if (phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ) {
760+ sband = &phy->mt76->sband_5g.sband;
761+ sdata = phy->iftype[NL80211_BAND_5GHZ];
762+ } else if (phy->mt76->chandef.chan->band == NL80211_BAND_6GHZ) {
763+ sband = &phy->mt76->sband_6g.sband;
764+ sdata = phy->iftype[NL80211_BAND_6GHZ];
765+ } else {
766+ sband = &phy->mt76->sband_2g.sband;
767+ sdata = phy->iftype[NL80211_BAND_2GHZ];
768+ }
769+
770+ memcpy(sta->addr, ed->addr[0], ETH_ALEN);
771+ if (phy->test.bf_en) {
772+ u8 addr[ETH_ALEN] = {0x00, 0x11, 0x11, 0x11, 0x11, 0x11};
773+
774+ memcpy(sta->addr, addr, ETH_ALEN);
775+ }
776+
777+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_HT)
778+ memcpy(&sta->ht_cap, &sband->ht_cap, sizeof(sta->ht_cap));
779+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_VHT)
780+ memcpy(&sta->vht_cap, &sband->vht_cap, sizeof(sta->vht_cap));
781+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_HE_SU)
782+ memcpy(&sta->he_cap, &sdata[NL80211_IFTYPE_STATION].he_cap,
783+ sizeof(sta->he_cap));
784+ sta->aid = aid;
785+ sta->wme = 1;
786+
787+ ret = mt7915_mac_sta_add(&phy->dev->mt76, phy->monitor_vif, sta);
788+ if (ret) {
789+ kfree(sta);
790+ return ret;
791+ }
792+
793+ /* prevent from starting tx ba session */
794+ for (tid = 0; tid < 8; tid++)
795+ set_bit(tid, &msta->ampdu_state);
796+
797+ list_add_tail(&msta->wcid.list, &td->tm_entry_list);
798+ td->entry_num++;
799+
800+ return 0;
801+}
802+
803+static void
804+mt7915_tm_entry_remove(struct mt7915_phy *phy, u8 aid)
805+{
806+ struct mt76_testmode_data *td = &phy->mt76->test;
807+ struct mt76_wcid *wcid, *tmp;
808+
809+ if (list_empty(&td->tm_entry_list))
810+ return;
811+
812+ list_for_each_entry_safe(wcid, tmp, &td->tm_entry_list, list) {
813+ struct mt76_testmode_entry_data *ed;
814+ struct mt7915_dev *dev = phy->dev;
815+ struct ieee80211_sta *sta;
816+
817+ ed = mt76_testmode_entry_data(phy->mt76, wcid);
818+ if (aid && ed->aid != aid)
819+ continue;
820+
821+ sta = wcid_to_sta(wcid);
822+ mt7915_mac_sta_remove(&dev->mt76, phy->monitor_vif, sta);
823+ mt76_wcid_mask_clear(dev->mt76.wcid_mask, wcid->idx);
824+
825+ list_del_init(&wcid->list);
826+ kfree(sta);
827+ phy->mt76->test.entry_num--;
828+ }
829+}
830+
831+static int
832+mt7915_tm_set_entry(struct mt7915_phy *phy)
833+{
834+ struct mt76_testmode_data *td = &phy->mt76->test;
835+ struct mt76_testmode_entry_data *ed;
836+ struct mt76_wcid *wcid;
837+
838+ if (!td->aid) {
839+ if (td->state > MT76_TM_STATE_IDLE)
840+ mt76_testmode_set_state(phy->mt76, MT76_TM_STATE_IDLE);
841+ mt7915_tm_entry_remove(phy, td->aid);
842+ return 0;
843+ }
844+
845+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
846+ if (ed->aid == td->aid) {
847+ struct sk_buff *skb;
848+
849+ local_bh_disable();
850+ skb = ed->tx_skb;
851+ memcpy(ed, &td->ed, sizeof(*ed));
852+ ed->tx_skb = skb;
853+ local_bh_enable();
854+
855+ return 0;
856+ }
857+ }
858+
859+ return mt7915_tm_entry_add(phy, td->aid);
860+}
861+
862+static void
863+mt7915_tm_update_entry(struct mt7915_phy *phy)
864+{
865+ struct mt76_testmode_data *td = &phy->mt76->test;
866+ struct mt76_testmode_entry_data *ed, tmp;
867+ struct mt76_wcid *wcid, *last;
868+
869+ if (!td->aid || phy->test.bf_en)
870+ return;
871+
872+ memcpy(&tmp, &td->ed, sizeof(tmp));
873+ last = list_last_entry(&td->tm_entry_list,
874+ struct mt76_wcid, list);
875+
876+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
877+ memcpy(&td->ed, ed, sizeof(td->ed));
878+ mt7915_tm_entry_remove(phy, td->aid);
879+ mt7915_tm_entry_add(phy, td->aid);
880+ if (wcid == last)
881+ break;
882+ }
883+
884+ memcpy(&td->ed, &tmp, sizeof(td->ed));
885+}
886+
887+static int
888+mt7915_tm_txbf_init(struct mt7915_phy *phy, u16 *val)
889+{
890+ struct mt76_testmode_data *td = &phy->mt76->test;
891+ struct mt7915_dev *dev = phy->dev;
892+ bool enable = val[0];
893+ void *phase_cal, *pfmu_data, *pfmu_tag;
894+ u8 addr[ETH_ALEN] = {0x00, 0x22, 0x22, 0x22, 0x22, 0x22};
895+
896+ if (!enable) {
897+ phy->test.bf_en = 0;
898+ return 0;
899+ }
900+
901+ if (!dev->test.txbf_phase_cal) {
902+ phase_cal = devm_kzalloc(dev->mt76.dev,
903+ sizeof(struct mt7915_tm_txbf_phase) *
904+ MAX_PHASE_GROUP_NUM,
905+ GFP_KERNEL);
906+ if (!phase_cal)
907+ return -ENOMEM;
908+
909+ dev->test.txbf_phase_cal = phase_cal;
910+ }
911+
912+ if (!dev->test.txbf_pfmu_data) {
913+ pfmu_data = devm_kzalloc(dev->mt76.dev, 512, GFP_KERNEL);
914+ if (!pfmu_data)
915+ return -ENOMEM;
916+
917+ dev->test.txbf_pfmu_data = pfmu_data;
918+ }
919+
920+ if (!dev->test.txbf_pfmu_tag) {
921+ pfmu_tag = devm_kzalloc(dev->mt76.dev,
922+ sizeof(struct mt7915_tm_pfmu_tag), GFP_KERNEL);
923+ if (!pfmu_tag)
924+ return -ENOMEM;
925+
926+ dev->test.txbf_pfmu_tag = pfmu_tag;
927+ }
928+
929+ memcpy(phy->monitor_vif->addr, addr, ETH_ALEN);
930+ mt7915_mcu_add_dev_info(phy, phy->monitor_vif, true);
931+
932+ td->tx_rate_mode = MT76_TM_TX_MODE_HT;
933+ td->tx_mpdu_len = 1024;
934+ td->tx_rate_sgi = 0;
935+ td->tx_ipg = 100;
936+ phy->test.bf_en = 1;
937+
938+ return mt7915_tm_set_trx(phy, TM_MAC_TX, true);
939+}
940+
941+static int
942+mt7915_tm_txbf_phase_comp(struct mt7915_phy *phy, u16 *val)
943+{
944+ struct mt7915_dev *dev = phy->dev;
945+ struct {
946+ u8 category;
947+ u8 wlan_idx_lo;
948+ u8 bw;
949+ u8 jp_band;
950+ u8 dbdc_idx;
951+ bool read_from_e2p;
952+ bool disable;
953+ u8 wlan_idx_hi;
954+ u8 buf[40];
955+ } __packed req = {
956+ .category = MT_BF_IBF_PHASE_COMP,
957+ .bw = val[0],
958+ .jp_band = (val[2] == 1) ? 1 : 0,
959+ .dbdc_idx = phy->band_idx,
960+ .read_from_e2p = val[3],
961+ .disable = val[4],
962+ };
963+ struct mt7915_tm_txbf_phase *phase =
964+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
965+
966+ wait_event_timeout(dev->mt76.tx_wait, phase[val[2]].status != 0, HZ);
967+ memcpy(req.buf, &phase[val[2]].phase, sizeof(req.buf));
968+
969+ pr_info("ibf cal process: phase comp info\n");
970+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
971+ &req, sizeof(req), 0);
972+
973+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
974+ sizeof(req), true);
975+}
976+
977+static int
978+mt7915_tm_txbf_profile_tag_read(struct mt7915_phy *phy, u8 pfmu_idx)
979+{
980+ struct mt7915_dev *dev = phy->dev;
981+ struct {
982+ u8 format_id;
983+ u8 pfmu_idx;
984+ bool bfer;
985+ u8 dbdc_idx;
986+ } __packed req = {
987+ .format_id = MT_BF_PFMU_TAG_READ,
988+ .pfmu_idx = pfmu_idx,
989+ .bfer = 1,
990+ .dbdc_idx = phy != &dev->phy,
991+ };
992+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
993+
994+ tag->t1.pfmu_idx = 0;
995+
996+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
997+ sizeof(req), true);
998+}
999+
1000+static int
1001+mt7915_tm_txbf_profile_tag_write(struct mt7915_phy *phy, u8 pfmu_idx,
1002+ struct mt7915_tm_pfmu_tag *tag)
1003+{
1004+ struct mt7915_dev *dev = phy->dev;
1005+ struct {
1006+ u8 format_id;
1007+ u8 pfmu_idx;
1008+ bool bfer;
1009+ u8 dbdc_idx;
1010+ u8 buf[64];
1011+ } __packed req = {
1012+ .format_id = MT_BF_PFMU_TAG_WRITE,
1013+ .pfmu_idx = pfmu_idx,
1014+ .bfer = 1,
1015+ .dbdc_idx = phy != &dev->phy,
1016+ };
1017+
1018+ memcpy(req.buf, tag, sizeof(*tag));
1019+ wait_event_timeout(dev->mt76.tx_wait, tag->t1.pfmu_idx != 0, HZ);
1020+
1021+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1022+ sizeof(req), false);
1023+}
1024+
1025+static int
1026+mt7915_tm_txbf_apply_tx(struct mt7915_phy *phy, u16 wlan_idx, bool ebf,
1027+ bool ibf, bool phase_cal)
1028+{
1029+#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1030+#define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
1031+ struct mt7915_dev *dev = phy->dev;
1032+ struct {
1033+ u8 category;
1034+ u8 wlan_idx_lo;
1035+ bool ebf;
1036+ bool ibf;
1037+ bool mu_txbf;
1038+ bool phase_cal;
1039+ u8 wlan_idx_hi;
1040+ u8 _rsv;
1041+ } __packed req = {
1042+ .category = MT_BF_DATA_PACKET_APPLY,
1043+ .wlan_idx_lo = to_wcid_lo(wlan_idx),
1044+ .ebf = ebf,
1045+ .ibf = ibf,
1046+ .phase_cal = phase_cal,
1047+ .wlan_idx_hi = to_wcid_hi(wlan_idx),
1048+ };
1049+
1050+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1051+ sizeof(req), false);
1052+}
1053+
1054+static int mt7915_tm_txbf_set_rate(struct mt7915_phy *phy,
1055+ struct mt76_wcid *wcid)
1056+{
1057+ struct mt7915_dev *dev = phy->dev;
1058+ struct mt76_testmode_entry_data *ed = mt76_testmode_entry_data(phy->mt76, wcid);
1059+ struct ieee80211_sta *sta = wcid_to_sta(wcid);
1060+ struct sta_phy rate = {};
1061+
1062+ if (!sta)
1063+ return 0;
1064+
1065+ rate.type = MT_PHY_TYPE_HT;
1066+ rate.bw = mt7915_tm_chan_bw(phy->mt76->chandef.width);
1067+ rate.nss = ed->tx_rate_nss;
1068+ rate.mcs = ed->tx_rate_idx;
1069+ rate.ldpc = (rate.bw || ed->tx_rate_ldpc) * GENMASK(2, 0);
1070+
1071+ return mt7915_mcu_set_fixed_rate_ctrl(dev, phy->monitor_vif, sta,
1072+ &rate, RATE_PARAM_FIXED);
1073+}
1074+
1075+static int
1076+mt7915_tm_txbf_set_tx(struct mt7915_phy *phy, u16 *val)
1077+{
1078+ bool bf_on = val[0], update = val[3];
1079+ /* u16 wlan_idx = val[2]; */
1080+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1081+ struct mt76_testmode_data *td = &phy->mt76->test;
1082+ struct mt76_wcid *wcid;
1083+
1084+ if (bf_on) {
1085+ mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1086+ mt7915_tm_txbf_profile_tag_read(phy, 2);
1087+ tag->t1.invalid_prof = false;
1088+ mt7915_tm_txbf_profile_tag_write(phy, 2, tag);
1089+
1090+ phy->test.bf_ever_en = true;
1091+
1092+ if (update)
1093+ mt7915_tm_txbf_apply_tx(phy, 1, 0, 1, 1);
1094+ } else {
1095+ if (!phy->test.bf_ever_en) {
1096+ if (update)
1097+ mt7915_tm_txbf_apply_tx(phy, 1, 0, 0, 0);
1098+ } else {
1099+ phy->test.bf_ever_en = false;
1100+
1101+ mt7915_tm_txbf_profile_tag_read(phy, 2);
1102+ tag->t1.invalid_prof = true;
1103+ mt7915_tm_txbf_profile_tag_write(phy, 2, tag);
1104+ }
1105+ }
1106+
1107+ wcid = list_first_entry(&td->tm_entry_list, struct mt76_wcid, list);
1108+ mt7915_tm_txbf_set_rate(phy, wcid);
1109+
1110+ return 0;
1111+}
1112+
1113+static int
1114+mt7915_tm_txbf_profile_update(struct mt7915_phy *phy, u16 *val, bool ebf)
1115+{
1116+ static const u8 mode_to_lm[] = {
1117+ [MT76_TM_TX_MODE_CCK] = 0,
1118+ [MT76_TM_TX_MODE_OFDM] = 0,
1119+ [MT76_TM_TX_MODE_HT] = 1,
1120+ [MT76_TM_TX_MODE_VHT] = 2,
1121+ [MT76_TM_TX_MODE_HE_SU] = 3,
1122+ [MT76_TM_TX_MODE_HE_EXT_SU] = 3,
1123+ [MT76_TM_TX_MODE_HE_TB] = 3,
1124+ [MT76_TM_TX_MODE_HE_MU] = 3,
1125+ };
1126+ struct mt76_testmode_data *td = &phy->mt76->test;
1127+ struct mt76_wcid *wcid;
1128+ struct ieee80211_vif *vif = phy->monitor_vif;
1129+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1130+ u8 pfmu_idx = val[0], nc = val[2], nr;
1131+ int ret;
1132+
1133+ if (td->tx_antenna_mask == 3)
1134+ nr = 1;
1135+ else if (td->tx_antenna_mask == 7)
1136+ nr = 2;
1137+ else
1138+ nr = 3;
1139+
1140+ memset(tag, 0, sizeof(*tag));
1141+ tag->t1.pfmu_idx = pfmu_idx;
1142+ tag->t1.ebf = ebf;
1143+ tag->t1.nr = nr;
1144+ tag->t1.nc = nc;
1145+ tag->t1.invalid_prof = true;
1146+
1147+ tag->t1.snr_sts4 = 0xc0;
1148+ tag->t1.snr_sts5 = 0xff;
1149+ tag->t1.snr_sts6 = 0xff;
1150+ tag->t1.snr_sts7 = 0xff;
1151+
1152+ if (ebf) {
1153+ tag->t1.row_id1 = 0;
1154+ tag->t1.row_id2 = 1;
1155+ tag->t1.row_id3 = 2;
1156+ tag->t1.row_id4 = 3;
1157+ tag->t1.lm = mode_to_lm[MT76_TM_TX_MODE_HT];
1158+ } else {
1159+ tag->t1.row_id1 = 4;
1160+ tag->t1.row_id2 = 5;
1161+ tag->t1.row_id3 = 6;
1162+ tag->t1.row_id4 = 7;
1163+ tag->t1.lm = mode_to_lm[MT76_TM_TX_MODE_OFDM];
1164+
1165+ tag->t2.ibf_timeout = 0xff;
1166+ tag->t2.ibf_nr = nr;
1167+ }
1168+
1169+ ret = mt7915_tm_txbf_profile_tag_write(phy, pfmu_idx, tag);
1170+ if (ret)
1171+ return ret;
1172+
1173+ wcid = list_first_entry(&td->tm_entry_list, struct mt76_wcid, list);
1174+ ret = mt7915_tm_add_txbf(phy, vif, wcid_to_sta(wcid), pfmu_idx, nr, nc, ebf);
1175+ if (ret)
1176+ return ret;
1177+
1178+ if (!ebf)
1179+ return mt7915_tm_txbf_apply_tx(phy, 1, false, true, true);
1180+
1181+ return 0;
1182+}
1183+
1184+static int
1185+mt7915_tm_txbf_phase_cal(struct mt7915_phy *phy, u16 *val)
1186+{
1187+#define GROUP_L 0
1188+#define GROUP_M 1
1189+#define GROUP_H 2
1190+ struct mt7915_dev *dev = phy->dev;
1191+ struct {
1192+ u8 category;
1193+ u8 group_l_m_n;
1194+ u8 group;
1195+ bool sx2;
1196+ u8 cal_type;
1197+ u8 lna_gain_level;
1198+ u8 _rsv[2];
1199+ } __packed req = {
1200+ .category = MT_BF_PHASE_CAL,
1201+ .group = val[0],
1202+ .group_l_m_n = val[1],
1203+ .sx2 = val[2],
1204+ .cal_type = val[3],
1205+ .lna_gain_level = 0, /* for test purpose */
1206+ };
1207+ struct mt7915_tm_txbf_phase *phase =
1208+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1209+
1210+ phase[req.group].status = 0;
1211+
1212+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1213+ sizeof(req), true);
1214+}
1215+
1216+int mt7915_tm_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb)
1217+{
1218+#define BF_PFMU_TAG 16
1219+#define BF_CAL_PHASE 21
1220+ u8 format_id;
1221+
developeraace7f52022-06-24 13:40:42 +08001222+ skb_pull(skb, sizeof(struct mt76_connac2_mcu_rxd));
developer42b63282022-06-16 13:33:13 +08001223+ format_id = *(u8 *)skb->data;
1224+
1225+ if (format_id == BF_PFMU_TAG) {
1226+ struct mt7915_tm_pfmu_tag *tag = dev->test.txbf_pfmu_tag;
1227+
1228+ skb_pull(skb, 8);
1229+ memcpy(tag, skb->data, sizeof(struct mt7915_tm_pfmu_tag));
1230+ } else if (format_id == BF_CAL_PHASE) {
1231+ struct mt7915_tm_ibf_cal_info *cal;
1232+ struct mt7915_tm_txbf_phase *phase =
1233+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1234+
1235+ cal = (struct mt7915_tm_ibf_cal_info *)skb->data;
1236+ switch (cal->cal_type) {
1237+ case IBF_PHASE_CAL_NORMAL:
1238+ case IBF_PHASE_CAL_NORMAL_INSTRUMENT:
1239+ if (cal->group_l_m_n != GROUP_M)
1240+ break;
1241+ phase = &phase[cal->group];
1242+ memcpy(&phase->phase, cal->buf + 16, sizeof(phase->phase));
1243+ phase->status = cal->status;
1244+ break;
1245+ case IBF_PHASE_CAL_VERIFY:
1246+ case IBF_PHASE_CAL_VERIFY_INSTRUMENT:
1247+ break;
1248+ default:
1249+ break;
1250+ }
1251+ }
1252+
1253+ wake_up(&dev->mt76.tx_wait);
1254+
1255+ return 0;
1256+}
1257+
1258+static int
1259+mt7915_tm_txbf_profile_update_all(struct mt7915_phy *phy, u16 *val)
1260+{
1261+ struct mt76_testmode_data *td = &phy->mt76->test;
1262+ u16 pfmu_idx = val[0];
1263+ u16 subc_id = val[1];
1264+ u16 angle11 = val[2];
1265+ u16 angle21 = val[3];
1266+ u16 angle31 = val[4];
1267+ u16 angle41 = val[5];
1268+ s16 phi11 = 0, phi21 = 0, phi31 = 0;
1269+ struct mt7915_tm_pfmu_data *pfmu_data;
1270+
1271+ if (subc_id > 63)
1272+ return -EINVAL;
1273+
1274+ if (td->tx_antenna_mask == 2) {
1275+ phi11 = (s16)(angle21 - angle11);
1276+ } else if (td->tx_antenna_mask == 3) {
1277+ phi11 = (s16)(angle31 - angle11);
1278+ phi21 = (s16)(angle31 - angle21);
1279+ } else {
1280+ phi11 = (s16)(angle41 - angle11);
1281+ phi21 = (s16)(angle41 - angle21);
1282+ phi31 = (s16)(angle41 - angle31);
1283+ }
1284+
1285+ pfmu_data = (struct mt7915_tm_pfmu_data *)phy->dev->test.txbf_pfmu_data;
1286+ pfmu_data = &pfmu_data[subc_id];
1287+
1288+ if (subc_id < 32)
1289+ pfmu_data->subc_idx = cpu_to_le16(subc_id + 224);
1290+ else
1291+ pfmu_data->subc_idx = cpu_to_le16(subc_id - 32);
1292+ pfmu_data->phi11 = cpu_to_le16(phi11);
1293+ pfmu_data->phi21 = cpu_to_le16(phi21);
1294+ pfmu_data->phi31 = cpu_to_le16(phi31);
1295+
1296+ if (subc_id == 63) {
1297+ struct mt7915_dev *dev = phy->dev;
1298+ struct {
1299+ u8 format_id;
1300+ u8 pfmu_idx;
1301+ u8 dbdc_idx;
1302+ u8 _rsv;
1303+ u8 buf[512];
1304+ } __packed req = {
1305+ .format_id = MT_BF_PROFILE_WRITE_ALL,
1306+ .pfmu_idx = pfmu_idx,
1307+ .dbdc_idx = phy != &dev->phy,
1308+ };
1309+
1310+ memcpy(req.buf, dev->test.txbf_pfmu_data, 512);
1311+
1312+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION),
1313+ &req, sizeof(req), true);
1314+ }
1315+
1316+ return 0;
1317+}
1318+
1319+static int
1320+mt7915_tm_txbf_e2p_update(struct mt7915_phy *phy)
1321+{
1322+ struct mt7915_tm_txbf_phase *phase, *p;
1323+ struct mt7915_dev *dev = phy->dev;
1324+ u8 *eeprom = dev->mt76.eeprom.data;
1325+ u16 offset;
1326+ bool is_7976;
1327+ int i;
1328+
1329+ is_7976 = mt7915_check_adie(dev, false) || is_mt7916(&dev->mt76);
1330+ offset = is_7976 ? 0x60a : 0x651;
1331+
1332+ phase = (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1333+ for (i = 0; i < MAX_PHASE_GROUP_NUM; i++) {
1334+ p = &phase[i];
1335+
1336+ if (!p->status)
1337+ continue;
1338+
1339+ /* copy phase cal data to eeprom */
1340+ memcpy(eeprom + offset + i * sizeof(p->phase), &p->phase,
1341+ sizeof(p->phase));
1342+ }
1343+
1344+ return 0;
1345+}
1346+
1347+static int
1348+mt7915_tm_set_txbf(struct mt7915_phy *phy)
1349+{
1350+ struct mt76_testmode_data *td = &phy->mt76->test;
1351+ u16 *val = td->txbf_param;
1352+
1353+ pr_info("ibf cal process: act = %u, val = %u, %u, %u, %u, %u\n",
1354+ td->txbf_act, val[0], val[1], val[2], val[3], val[4]);
1355+
1356+ switch (td->txbf_act) {
1357+ case MT76_TM_TXBF_ACT_INIT:
1358+ return mt7915_tm_txbf_init(phy, val);
1359+ case MT76_TM_TXBF_ACT_UPDATE_CH:
1360+ mt7915_tm_update_channel(phy);
1361+ break;
1362+ case MT76_TM_TXBF_ACT_PHASE_COMP:
1363+ return mt7915_tm_txbf_phase_comp(phy, val);
1364+ case MT76_TM_TXBF_ACT_TX_PREP:
1365+ return mt7915_tm_txbf_set_tx(phy, val);
1366+ case MT76_TM_TXBF_ACT_IBF_PROF_UPDATE:
1367+ return mt7915_tm_txbf_profile_update(phy, val, false);
1368+ case MT76_TM_TXBF_ACT_EBF_PROF_UPDATE:
1369+ return mt7915_tm_txbf_profile_update(phy, val, true);
1370+ case MT76_TM_TXBF_ACT_PHASE_CAL:
1371+ return mt7915_tm_txbf_phase_cal(phy, val);
1372+ case MT76_TM_TXBF_ACT_PROF_UPDATE_ALL:
1373+ return mt7915_tm_txbf_profile_update_all(phy, val);
1374+ case MT76_TM_TXBF_ACT_E2P_UPDATE:
1375+ return mt7915_tm_txbf_e2p_update(phy);
1376+ default:
1377+ break;
1378+ };
1379+
1380+ return 0;
1381+}
1382+
1383 static int
developeraace7f52022-06-24 13:40:42 +08001384 mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,
developer42b63282022-06-16 13:33:13 +08001385- u16 cw_max, u16 txop)
1386+ u16 cw_max, u16 txop, u8 tx_cmd)
1387 {
developeraace7f52022-06-24 13:40:42 +08001388 struct mt7915_vif *mvif = (struct mt7915_vif *)phy->monitor_vif->drv_priv;
developer42b63282022-06-16 13:33:13 +08001389- struct mt7915_mcu_tx req = { .total = 1 };
1390+ struct mt7915_mcu_tx req = {
1391+ .valid = true,
1392+ .mode = tx_cmd,
1393+ .total = 1,
1394+ };
1395 struct edca *e = &req.edca[0];
1396
developeraace7f52022-06-24 13:40:42 +08001397 e->queue = qid + mvif->mt76.wmm_idx * MT76_CONNAC_MAX_WMM_SETS;
1398@@ -262,7 +1036,8 @@ done:
developer42b63282022-06-16 13:33:13 +08001399
developeraace7f52022-06-24 13:40:42 +08001400 return mt7915_tm_set_wmm_qid(phy,
developer42b63282022-06-16 13:33:13 +08001401 mt76_connac_lmac_mapping(IEEE80211_AC_BE),
1402- aifsn, cw, cw, 0);
1403+ aifsn, cw, cw, 0,
1404+ mode == MT76_TM_TX_MODE_HE_MU);
1405 }
1406
1407 static int
developeraace7f52022-06-24 13:40:42 +08001408@@ -338,7 +1113,7 @@ mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time)
developer42b63282022-06-16 13:33:13 +08001409 bitrate = cfg80211_calculate_bitrate(&rate);
1410 tx_len = bitrate * tx_time / 10 / 8;
1411
1412- ret = mt76_testmode_alloc_skb(phy->mt76, tx_len);
1413+ ret = mt76_testmode_init_skb(phy->mt76, tx_len, &td->tx_skb, td->addr);
1414 if (ret)
1415 return ret;
1416
developerd4975692022-07-15 18:30:03 +08001417@@ -456,64 +1231,227 @@ mt7915_tm_init(struct mt7915_phy *phy, bool en)
developer42b63282022-06-16 13:33:13 +08001418
1419 phy->mt76->test.flag |= MT_TM_FW_RX_COUNT;
1420
1421- if (!en)
1422+ if (!en) {
1423 mt7915_tm_set_tam_arb(phy, en, 0);
1424+
1425+ phy->mt76->test.aid = 0;
1426+ phy->mt76->test.tx_mpdu_len = 0;
1427+ phy->test.bf_en = 0;
1428+ mt7915_tm_set_entry(phy);
1429+ }
1430+}
1431+
1432+static bool
1433+mt7915_tm_check_skb(struct mt7915_phy *phy)
1434+{
1435+ struct mt76_testmode_entry_data *ed;
1436+ struct mt76_wcid *wcid;
1437+
1438+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
1439+ struct ieee80211_tx_info *info;
1440+
1441+ if (!ed->tx_skb)
1442+ return false;
1443+
1444+ info = IEEE80211_SKB_CB(ed->tx_skb);
1445+ info->control.vif = phy->monitor_vif;
1446+ }
1447+
1448+ return true;
1449+}
1450+
1451+static int
1452+mt7915_tm_set_ba(struct mt7915_phy *phy)
1453+{
1454+ struct mt7915_dev *dev = phy->dev;
1455+ struct mt76_testmode_data *td = &phy->mt76->test;
1456+ struct mt76_wcid *wcid;
1457+ struct ieee80211_vif *vif = phy->monitor_vif;
1458+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1459+ struct ieee80211_ampdu_params params = { .buf_size = 256 };
1460+
1461+ list_for_each_entry(wcid, &td->tm_entry_list, list) {
1462+ int tid, ret;
1463+
1464+ params.sta = wcid_to_sta(wcid);
1465+ for (tid = 0; tid < 8; tid++) {
1466+ params.tid = tid;
1467+ ret = mt7915_mcu_add_tx_ba(phy->dev, &params, true);
1468+ if (ret)
1469+ return ret;
1470+ }
1471+ }
1472+
1473+ mt76_wr(dev, MT_AGG_AALCR0(mvif->mt76.band_idx, mvif->mt76.wmm_idx),
1474+ 0x01010101);
1475+
1476+ return 0;
1477+}
1478+
1479+static int
1480+mt7915_tm_set_muru_cfg(struct mt7915_phy *phy, struct mt7915_tm_muru *muru)
1481+{
1482+/* #define MURU_SET_MANUAL_CFG 100 */
1483+ struct mt7915_dev *dev = phy->dev;
1484+ struct {
1485+ __le32 cmd;
1486+ struct mt7915_tm_muru muru;
1487+ } __packed req = {
1488+ .cmd = cpu_to_le32(MURU_SET_MANUAL_CFG),
1489+ };
1490+
1491+ memcpy(&req.muru, muru, sizeof(struct mt7915_tm_muru));
1492+
1493+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1494+ sizeof(req), false);
1495+}
1496+
1497+static int
1498+mt7915_tm_set_muru_dl(struct mt7915_phy *phy)
1499+{
1500+ struct mt76_testmode_data *td = &phy->mt76->test;
1501+ struct mt76_testmode_entry_data *ed;
1502+ struct mt76_wcid *wcid;
1503+ struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1504+ struct ieee80211_vif *vif = phy->monitor_vif;
1505+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1506+ struct mt7915_tm_muru muru = {};
1507+ struct mt7915_tm_muru_comm *comm = &muru.comm;
1508+ struct mt7915_tm_muru_dl *dl = &muru.dl;
1509+ int i;
1510+
1511+ comm->ppdu_format = MURU_PPDU_HE_MU;
1512+ comm->band = mvif->mt76.band_idx;
1513+ comm->wmm_idx = mvif->mt76.wmm_idx;
1514+ comm->spe_idx = phy->test.spe_idx;
1515+
1516+ dl->bw = mt7915_tm_chan_bw(chandef->width);
1517+ dl->gi = td->tx_rate_sgi;;
1518+ dl->ltf = td->tx_ltf;
1519+ dl->tx_mode = MT_PHY_TYPE_HE_MU;
1520+
1521+ for (i = 0; i < sizeof(dl->ru); i++)
1522+ dl->ru[i] = 0x71;
1523+
1524+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
1525+ struct mt7915_tm_muru_dl_usr *dl_usr = &dl->usr[dl->user_num];
1526+
1527+ dl_usr->wlan_idx = cpu_to_le16(wcid->idx);
1528+ dl_usr->ru_alloc_seg = ed->aid < 8 ? 0 : 1;
1529+ dl_usr->ru_idx = ed->ru_idx;
1530+ dl_usr->mcs = ed->tx_rate_idx;
1531+ dl_usr->nss = ed->tx_rate_nss - 1;
1532+ dl_usr->ldpc = ed->tx_rate_ldpc;
1533+ dl->ru[dl->user_num] = ed->ru_alloc;
1534+
1535+ dl->user_num++;
1536+ }
1537+
1538+ muru.cfg_comm = cpu_to_le32(MURU_COMM_SET);
1539+ muru.cfg_dl = cpu_to_le32(MURU_DL_SET);
1540+
1541+ return mt7915_tm_set_muru_cfg(phy, &muru);
1542+}
1543+
1544+static int
1545+mt7915_tm_set_muru_pkt_cnt(struct mt7915_phy *phy, bool enable, u32 tx_count)
1546+{
1547+#define MURU_SET_TX_PKT_CNT 105
1548+#define MURU_SET_TX_EN 106
1549+ struct mt7915_dev *dev = phy->dev;
1550+ struct {
1551+ __le32 cmd;
1552+ u8 band;
1553+ u8 enable;
1554+ u8 _rsv[2];
1555+ __le32 tx_count;
1556+ } __packed req = {
1557+ .band = phy != &dev->phy,
1558+ .enable = enable,
1559+ .tx_count = enable ? cpu_to_le32(tx_count) : 0,
1560+ };
1561+ int ret;
1562+
1563+ req.cmd = enable ? cpu_to_le32(MURU_SET_TX_PKT_CNT) :
1564+ cpu_to_le32(MURU_SET_TX_EN);
1565+
1566+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1567+ sizeof(req), false);
1568+ if (ret)
1569+ return ret;
1570+
1571+ req.cmd = enable ? cpu_to_le32(MURU_SET_TX_EN) :
1572+ cpu_to_le32(MURU_SET_TX_PKT_CNT);
1573+
1574+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1575+ sizeof(req), false);
1576 }
1577
1578 static void
1579-mt7915_tm_update_channel(struct mt7915_phy *phy)
1580+mt7915_tm_tx_frames_mu(struct mt7915_phy *phy, bool enable)
1581 {
1582- mutex_unlock(&phy->dev->mt76.mutex);
1583- mt7915_set_channel(phy);
1584- mutex_lock(&phy->dev->mt76.mutex);
1585+ struct mt76_testmode_data *td = &phy->mt76->test;
1586
1587- mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));
1588+ if (enable) {
1589+ struct mt7915_dev *dev = phy->dev;
1590+
1591+ mt7915_tm_set_ba(phy);
1592+ mt7915_tm_set_muru_dl(phy);
1593+ mt76_rr(dev, MT_MIB_DR8(phy != &dev->phy));
1594+ } else {
1595+ /* set to zero for counting real tx free num */
1596+ td->tx_done = 0;
1597+ }
1598+
1599+ mt7915_tm_set_muru_pkt_cnt(phy, enable, td->tx_count);
1600+ usleep_range(100000, 200000);
1601 }
1602
1603 static void
developerd4975692022-07-15 18:30:03 +08001604 mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
1605 {
developer42b63282022-06-16 13:33:13 +08001606 struct mt76_testmode_data *td = &phy->mt76->test;
1607- struct mt7915_dev *dev = phy->dev;
1608- struct ieee80211_tx_info *info;
1609- u8 duty_cycle = td->tx_duty_cycle;
1610- u32 tx_time = td->tx_time;
1611- u32 ipg = td->tx_ipg;
1612
1613 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1614- mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx);
1615+ mt7915_tm_set_trx(phy, TM_MAC_TX, false);
1616
1617 if (en) {
1618- mt7915_tm_update_channel(phy);
1619+ u32 tx_time = td->tx_time, ipg = td->tx_ipg;
1620+ u8 duty_cycle = td->tx_duty_cycle;
1621+
1622+ if (!phy->test.bf_en)
1623+ mt7915_tm_update_channel(phy);
1624
developerd4975692022-07-15 18:30:03 +08001625 if (td->tx_spe_idx)
developer42b63282022-06-16 13:33:13 +08001626 phy->test.spe_idx = td->tx_spe_idx;
developerd4975692022-07-15 18:30:03 +08001627 else
1628 phy->test.spe_idx = mt76_connac_spe_idx(td->tx_antenna_mask);
developer42b63282022-06-16 13:33:13 +08001629- }
1630
1631- mt7915_tm_set_tam_arb(phy, en,
1632- td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);
1633+ /* if all three params are set, duty_cycle will be ignored */
1634+ if (duty_cycle && tx_time && !ipg) {
1635+ ipg = tx_time * 100 / duty_cycle - tx_time;
1636+ } else if (duty_cycle && !tx_time && ipg) {
1637+ if (duty_cycle < 100)
1638+ tx_time = duty_cycle * ipg / (100 - duty_cycle);
1639+ }
1640
1641- /* if all three params are set, duty_cycle will be ignored */
1642- if (duty_cycle && tx_time && !ipg) {
1643- ipg = tx_time * 100 / duty_cycle - tx_time;
1644- } else if (duty_cycle && !tx_time && ipg) {
1645- if (duty_cycle < 100)
1646- tx_time = duty_cycle * ipg / (100 - duty_cycle);
1647- }
1648+ mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
1649+ mt7915_tm_set_tx_len(phy, tx_time);
1650
1651- mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
1652- mt7915_tm_set_tx_len(phy, tx_time);
1653+ if (ipg)
1654+ td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
1655
1656- if (ipg)
1657- td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
1658+ if (!mt7915_tm_check_skb(phy))
1659+ return;
1660+ } else {
1661+ mt7915_tm_clean_hwq(phy);
1662+ }
1663
1664- if (!en || !td->tx_skb)
1665- return;
1666+ mt7915_tm_set_tam_arb(phy, en,
1667+ td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);
1668
1669- info = IEEE80211_SKB_CB(td->tx_skb);
1670- info->control.vif = phy->monitor_vif;
1671+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1672+ mt7915_tm_tx_frames_mu(phy, en);
1673
1674 mt7915_tm_set_trx(phy, TM_MAC_TX, en);
1675 }
developerd4975692022-07-15 18:30:03 +08001676@@ -542,10 +1480,6 @@ mt7915_tm_get_rx_stats(struct mt7915_phy *phy, bool clear)
developer42b63282022-06-16 13:33:13 +08001677 return ret;
1678
1679 rs_band = (struct mt7915_tm_rx_stat_band *)skb->data;
1680- /* pr_info("mdrdy_cnt = %d\n", le32_to_cpu(rs_band->mdrdy_cnt)); */
1681- /* pr_info("fcs_err = %d\n", le16_to_cpu(rs_band->fcs_err)); */
1682- /* pr_info("len_mismatch = %d\n", le16_to_cpu(rs_band->len_mismatch)); */
1683- /* pr_info("fcs_ok = %d\n", le16_to_cpu(rs_band->fcs_succ)); */
1684
1685 if (!clear) {
developer4df64ba2022-09-01 14:44:55 +08001686 enum mt76_rxq_id q = req.band ? MT_RXQ_BAND1 : MT_RXQ_MAIN;
developerd4975692022-07-15 18:30:03 +08001687@@ -560,13 +1494,61 @@ mt7915_tm_get_rx_stats(struct mt7915_phy *phy, bool clear)
developer42b63282022-06-16 13:33:13 +08001688 return 0;
1689 }
1690
1691+static int
1692+mt7915_tm_set_rx_user_idx(struct mt7915_phy *phy, u8 aid)
1693+{
1694+ struct mt7915_dev *dev = phy->dev;
1695+ struct mt76_wcid *wcid = NULL;
1696+ struct mt76_testmode_entry_data *ed;
1697+ struct {
1698+ u8 band;
1699+ u8 _rsv;
1700+ __le16 wlan_idx;
1701+ } __packed req = {
1702+ .band = phy->band_idx,
1703+ };
1704+
1705+ mt76_tm_for_each_entry(phy->mt76, wcid, ed)
1706+ if (ed->aid == aid)
1707+ break;
1708+
1709+ if (!wcid)
1710+ return -EINVAL;
1711+
1712+ req.wlan_idx = cpu_to_le16(wcid->idx);
1713+
1714+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_STAT_USER_CTRL),
1715+ &req, sizeof(req), false);
1716+}
1717+
1718+static int
1719+mt7915_tm_set_muru_aid(struct mt7915_phy *phy, u16 aid)
1720+{
1721+ struct mt7915_dev *dev = phy->dev;
1722+ struct mt7915_tm_cmd req = {
1723+ .testmode_en = 1,
1724+ .param_idx = MCU_ATE_SET_MU_RX_AID,
1725+ .param.rx_aid.band = cpu_to_le32(phy->band_idx),
1726+ .param.rx_aid.aid = cpu_to_le16(aid),
1727+ };
1728+
1729+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
1730+ sizeof(req), false);
1731+}
1732+
1733 static void
1734 mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
1735 {
1736+ struct mt76_testmode_data *td = &phy->mt76->test;
1737+
1738+ mt7915_tm_set_trx(phy, TM_MAC_TX, false);
1739 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1740
1741 if (en) {
1742- mt7915_tm_update_channel(phy);
1743+ if (!phy->test.bf_en)
1744+ mt7915_tm_update_channel(phy);
1745+ if (td->aid)
1746+ mt7915_tm_set_rx_user_idx(phy, td->aid);
1747
1748 /* read-clear */
1749 mt7915_tm_get_rx_stats(phy, true);
developerd4975692022-07-15 18:30:03 +08001750@@ -574,9 +1556,12 @@ mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
developer42b63282022-06-16 13:33:13 +08001751 /* clear fw count */
1752 mt7915_tm_set_phy_count(phy, 0);
1753 mt7915_tm_set_phy_count(phy, 1);
1754-
1755- mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
1756 }
1757+
1758+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1759+ mt7915_tm_set_muru_aid(phy, en ? td->aid : 0xf800);
1760+
1761+ mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
1762 }
1763
1764 static int
developerd4975692022-07-15 18:30:03 +08001765@@ -613,35 +1598,7 @@ mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en)
developer42b63282022-06-16 13:33:13 +08001766 tx_cont->center_ch = freq1;
1767 tx_cont->tx_ant = td->tx_antenna_mask;
1768 tx_cont->band = phy != &dev->phy;
1769-
1770- switch (chandef->width) {
1771- case NL80211_CHAN_WIDTH_40:
1772- tx_cont->bw = CMD_CBW_40MHZ;
1773- break;
1774- case NL80211_CHAN_WIDTH_80:
1775- tx_cont->bw = CMD_CBW_80MHZ;
1776- break;
1777- case NL80211_CHAN_WIDTH_80P80:
1778- tx_cont->bw = CMD_CBW_8080MHZ;
1779- break;
1780- case NL80211_CHAN_WIDTH_160:
1781- tx_cont->bw = CMD_CBW_160MHZ;
1782- break;
1783- case NL80211_CHAN_WIDTH_5:
1784- tx_cont->bw = CMD_CBW_5MHZ;
1785- break;
1786- case NL80211_CHAN_WIDTH_10:
1787- tx_cont->bw = CMD_CBW_10MHZ;
1788- break;
1789- case NL80211_CHAN_WIDTH_20:
1790- tx_cont->bw = CMD_CBW_20MHZ;
1791- break;
1792- case NL80211_CHAN_WIDTH_20_NOHT:
1793- tx_cont->bw = CMD_CBW_20MHZ;
1794- break;
1795- default:
1796- return -EINVAL;
1797- }
1798+ tx_cont->bw = mt7915_tm_chan_bw(chandef->width);
1799
1800 if (!en) {
1801 req.op.rf.param.func_data = cpu_to_le32(phy != &dev->phy);
developerd4975692022-07-15 18:30:03 +08001802@@ -725,6 +1682,12 @@ mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed)
developer42b63282022-06-16 13:33:13 +08001803 mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0);
1804 if (changed & BIT(TM_CHANGED_TXPOWER))
1805 mt7915_tm_set_tx_power(phy);
1806+ if (changed & BIT(TM_CHANGED_AID))
1807+ mt7915_tm_set_entry(phy);
1808+ if (changed & BIT(TM_CHANGED_CFG))
1809+ mt7915_tm_set_cfg(phy);
1810+ if (changed & BIT(TM_CHANGED_TXBF_ACT))
1811+ mt7915_tm_set_txbf(phy);
1812 }
1813
1814 static int
developer27b55252022-09-05 19:09:45 +08001815@@ -804,6 +1767,7 @@ static int
developer42b63282022-06-16 13:33:13 +08001816 mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
1817 {
1818 struct mt7915_phy *phy = mphy->priv;
1819+ struct mt7915_dev *dev = phy->dev;
1820 void *rx, *rssi;
1821 int i;
1822
developer27b55252022-09-05 19:09:45 +08001823@@ -849,11 +1813,68 @@ mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
developer42b63282022-06-16 13:33:13 +08001824
1825 nla_nest_end(msg, rx);
1826
1827+ if (mphy->test.tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1828+ mphy->test.tx_done += mt76_rr(dev, MT_MIB_DR8(phy != &dev->phy));
1829+
1830 return mt7915_tm_get_rx_stats(phy, false);
1831 }
1832
1833+static int
1834+mt7915_tm_write_back_to_efuse(struct mt7915_dev *dev)
1835+{
1836+ struct mt7915_mcu_eeprom_info req = {};
1837+ u8 *eeprom = dev->mt76.eeprom.data;
1838+ int i, ret = -EINVAL;
1839+
1840+ /* prevent from damaging chip id in efuse */
1841+ if (mt76_chip(&dev->mt76) != get_unaligned_le16(eeprom))
1842+ goto out;
1843+
1844+ for (i = 0; i < mt7915_eeprom_size(dev); i += MT76_TM_EEPROM_BLOCK_SIZE) {
1845+ req.addr = cpu_to_le32(i);
1846+ memcpy(&req.data, eeprom + i, MT76_TM_EEPROM_BLOCK_SIZE);
1847+
1848+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EFUSE_ACCESS),
1849+ &req, sizeof(req), true);
1850+ if (ret)
1851+ return ret;
1852+ }
1853+
1854+out:
1855+ return ret;
1856+}
1857+
1858+static int
1859+mt7915_tm_set_eeprom(struct mt76_phy *mphy, u32 offset, u8 *val, u8 action)
1860+{
1861+ struct mt7915_phy *phy = mphy->priv;
1862+ struct mt7915_dev *dev = phy->dev;
1863+ u8 *eeprom = dev->mt76.eeprom.data;
1864+ int ret = 0;
1865+
1866+ if (offset >= mt7915_eeprom_size(dev))
1867+ return -EINVAL;
1868+
1869+ switch (action) {
1870+ case MT76_TM_EEPROM_ACTION_UPDATE_DATA:
1871+ memcpy(eeprom + offset, val, MT76_TM_EEPROM_BLOCK_SIZE);
1872+ break;
1873+ case MT76_TM_EEPROM_ACTION_UPDATE_BUFFER_MODE:
1874+ ret = mt7915_mcu_set_eeprom(dev, true);
1875+ break;
1876+ case MT76_TM_EEPROM_ACTION_WRITE_TO_EFUSE:
1877+ ret = mt7915_tm_write_back_to_efuse(dev);
1878+ break;
1879+ default:
1880+ break;
1881+ }
1882+
1883+ return ret;
1884+}
1885+
1886 const struct mt76_testmode_ops mt7915_testmode_ops = {
1887 .set_state = mt7915_tm_set_state,
1888 .set_params = mt7915_tm_set_params,
1889 .dump_stats = mt7915_tm_dump_stats,
1890+ .set_eeprom = mt7915_tm_set_eeprom,
1891 };
1892diff --git a/mt7915/testmode.h b/mt7915/testmode.h
developer29344f12022-10-17 12:01:44 +08001893index a1c54c89..01b08e9e 100644
developer42b63282022-06-16 13:33:13 +08001894--- a/mt7915/testmode.h
1895+++ b/mt7915/testmode.h
1896@@ -4,6 +4,8 @@
1897 #ifndef __MT7915_TESTMODE_H
1898 #define __MT7915_TESTMODE_H
1899
1900+#include "mcu.h"
1901+
1902 struct mt7915_tm_trx {
1903 u8 type;
1904 u8 enable;
1905@@ -39,6 +41,11 @@ struct mt7915_tm_cfg {
1906 u8 _rsv[2];
1907 };
1908
1909+struct mt7915_tm_mu_rx_aid {
1910+ __le32 band;
1911+ __le16 aid;
1912+};
1913+
1914 struct mt7915_tm_cmd {
1915 u8 testmode_en;
1916 u8 param_idx;
1917@@ -50,6 +57,7 @@ struct mt7915_tm_cmd {
1918 struct mt7915_tm_slot_time slot;
1919 struct mt7915_tm_clean_txq clean;
1920 struct mt7915_tm_cfg cfg;
1921+ struct mt7915_tm_mu_rx_aid rx_aid;
1922 u8 test[72];
1923 } param;
1924 } __packed;
1925@@ -109,6 +117,16 @@ enum {
1926 TAM_ARB_OP_MODE_FORCE_SU = 5,
1927 };
1928
1929+enum {
1930+ TM_CBW_20MHZ,
1931+ TM_CBW_40MHZ,
1932+ TM_CBW_80MHZ,
1933+ TM_CBW_10MHZ,
1934+ TM_CBW_5MHZ,
1935+ TM_CBW_160MHZ,
1936+ TM_CBW_8080MHZ,
1937+};
1938+
1939 struct mt7915_tm_rx_stat_band {
1940 u8 category;
1941
1942@@ -130,4 +148,264 @@ struct mt7915_tm_rx_stat_band {
1943 __le16 mdrdy_cnt_ofdm;
1944 };
1945
1946+struct mt7915_tm_muru_comm {
1947+ u8 ppdu_format;
1948+ u8 sch_type;
1949+ u8 band;
1950+ u8 wmm_idx;
1951+ u8 spe_idx;
1952+ u8 proc_type;
1953+};
1954+
1955+struct mt7915_tm_muru_dl_usr {
1956+ __le16 wlan_idx;
1957+ u8 ru_alloc_seg;
1958+ u8 ru_idx;
1959+ u8 ldpc;
1960+ u8 nss;
1961+ u8 mcs;
1962+ u8 mu_group_idx;
1963+ u8 vht_groud_id;
1964+ u8 vht_up;
1965+ u8 he_start_stream;
1966+ u8 he_mu_spatial;
1967+ u8 ack_policy;
1968+ __le16 tx_power_alpha;
1969+};
1970+
1971+struct mt7915_tm_muru_dl {
1972+ u8 user_num;
1973+ u8 tx_mode;
1974+ u8 bw;
1975+ u8 gi;
1976+ u8 ltf;
1977+ /* sigB */
1978+ u8 mcs;
1979+ u8 dcm;
1980+ u8 cmprs;
1981+
1982+ u8 tx_power;
1983+ u8 ru[8];
1984+ u8 c26[2];
1985+ u8 ack_policy;
1986+
1987+ struct mt7915_tm_muru_dl_usr usr[16];
1988+};
1989+
1990+struct mt7915_tm_muru_ul_usr {
1991+ __le16 wlan_idx;
1992+ u8 ru_alloc;
1993+ u8 ru_idx;
1994+ u8 ldpc;
1995+ u8 nss;
1996+ u8 mcs;
1997+ u8 target_rssi;
1998+ __le32 trig_pkt_size;
1999+};
2000+
2001+struct mt7915_tm_muru_ul {
2002+ u8 user_num;
2003+
2004+ /* UL TX */
2005+ u8 trig_type;
2006+ __le16 trig_cnt;
2007+ __le16 trig_intv;
2008+ u8 bw;
2009+ u8 gi_ltf;
2010+ __le16 ul_len;
2011+ u8 pad;
2012+ u8 trig_ta[ETH_ALEN];
2013+ u8 ru[8];
2014+ u8 c26[2];
2015+
2016+ struct mt7915_tm_muru_ul_usr usr[16];
2017+ /* HE TB RX Debug */
2018+ __le32 rx_hetb_nonsf_en_bitmap;
2019+ __le32 rx_hetb_cfg[2];
2020+
2021+ /* DL TX */
2022+ u8 ba_type;
2023+};
2024+
2025+struct mt7915_tm_muru {
2026+ __le32 cfg_comm;
2027+ __le32 cfg_dl;
2028+ __le32 cfg_ul;
2029+
2030+ struct mt7915_tm_muru_comm comm;
2031+ struct mt7915_tm_muru_dl dl;
2032+ struct mt7915_tm_muru_ul ul;
2033+};
2034+
2035+#define MURU_PPDU_HE_MU BIT(3)
2036+
2037+/* Common Config */
2038+/* #define MURU_COMM_PPDU_FMT BIT(0) */
2039+/* #define MURU_COMM_SCH_TYPE BIT(1) */
2040+/* #define MURU_COMM_BAND BIT(2) */
2041+/* #define MURU_COMM_WMM BIT(3) */
2042+/* #define MURU_COMM_SPE_IDX BIT(4) */
2043+/* #define MURU_COMM_PROC_TYPE BIT(5) */
2044+/* #define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_BAND | \ */
2045+/* MURU_COMM_WMM | MURU_COMM_SPE_IDX) */
2046+/* DL Config */
2047+#define MURU_DL_BW BIT(0)
2048+#define MURU_DL_GI BIT(1)
2049+#define MURU_DL_TX_MODE BIT(2)
2050+#define MURU_DL_TONE_PLAN BIT(3)
2051+#define MURU_DL_USER_CNT BIT(4)
2052+#define MURU_DL_LTF BIT(5)
2053+#define MURU_DL_SIGB_MCS BIT(6)
2054+#define MURU_DL_SIGB_DCM BIT(7)
2055+#define MURU_DL_SIGB_CMPRS BIT(8)
2056+#define MURU_DL_ACK_POLICY BIT(9)
2057+#define MURU_DL_TXPOWER BIT(10)
2058+/* DL Per User Config */
2059+#define MURU_DL_USER_WLAN_ID BIT(16)
2060+#define MURU_DL_USER_COD BIT(17)
2061+#define MURU_DL_USER_MCS BIT(18)
2062+#define MURU_DL_USER_NSS BIT(19)
2063+#define MURU_DL_USER_RU_ALLOC BIT(20)
2064+#define MURU_DL_USER_MUMIMO_GRP BIT(21)
2065+#define MURU_DL_USER_MUMIMO_VHT BIT(22)
2066+#define MURU_DL_USER_ACK_POLICY BIT(23)
2067+#define MURU_DL_USER_MUMIMO_HE BIT(24)
2068+#define MURU_DL_USER_PWR_ALPHA BIT(25)
2069+#define MURU_DL_SET (GENMASK(7, 0) | GENMASK(20, 16) | BIT(25))
2070+
2071+#define MAX_PHASE_GROUP_NUM 9
2072+
2073+struct mt7915_tm_txbf_phase {
2074+ u8 status;
2075+ struct {
2076+ u8 r0_uh;
2077+ u8 r0_h;
2078+ u8 r0_m;
2079+ u8 r0_l;
2080+ u8 r0_ul;
2081+ u8 r1_uh;
2082+ u8 r1_h;
2083+ u8 r1_m;
2084+ u8 r1_l;
2085+ u8 r1_ul;
2086+ u8 r2_uh;
2087+ u8 r2_h;
2088+ u8 r2_m;
2089+ u8 r2_l;
2090+ u8 r2_ul;
2091+ u8 r3_uh;
2092+ u8 r3_h;
2093+ u8 r3_m;
2094+ u8 r3_l;
2095+ u8 r3_ul;
2096+ u8 r2_uh_sx2;
2097+ u8 r2_h_sx2;
2098+ u8 r2_m_sx2;
2099+ u8 r2_l_sx2;
2100+ u8 r2_ul_sx2;
2101+ u8 r3_uh_sx2;
2102+ u8 r3_h_sx2;
2103+ u8 r3_m_sx2;
2104+ u8 r3_l_sx2;
2105+ u8 r3_ul_sx2;
2106+ u8 m_t0_h;
2107+ u8 m_t1_h;
2108+ u8 m_t2_h;
2109+ u8 m_t2_h_sx2;
2110+ u8 r0_reserved;
2111+ u8 r1_reserved;
2112+ u8 r2_reserved;
2113+ u8 r3_reserved;
2114+ u8 r2_sx2_reserved;
2115+ u8 r3_sx2_reserved;
2116+ } phase;
2117+};
2118+
2119+struct mt7915_tm_pfmu_tag1 {
2120+ __le32 pfmu_idx:10;
2121+ __le32 ebf:1;
2122+ __le32 data_bw:2;
2123+ __le32 lm:2;
2124+ __le32 is_mu:1;
2125+ __le32 nr:3, nc:3;
2126+ __le32 codebook:2;
2127+ __le32 ngroup:2;
2128+ __le32 _rsv:2;
2129+ __le32 invalid_prof:1;
2130+ __le32 rmsd:3;
2131+
2132+ __le32 col_id1:6, row_id1:10;
2133+ __le32 col_id2:6, row_id2:10;
2134+ __le32 col_id3:6, row_id3:10;
2135+ __le32 col_id4:6, row_id4:10;
2136+
2137+ __le32 ru_start_id:7;
2138+ __le32 _rsv1:1;
2139+ __le32 ru_end_id:7;
2140+ __le32 _rsv2:1;
2141+ __le32 mob_cal_en:1;
2142+ __le32 _rsv3:15;
2143+
2144+ __le32 snr_sts0:8, snr_sts1:8, snr_sts2:8, snr_sts3:8;
2145+ __le32 snr_sts4:8, snr_sts5:8, snr_sts6:8, snr_sts7:8;
2146+
2147+ __le32 _rsv4;
2148+} __packed;
2149+
2150+struct mt7915_tm_pfmu_tag2 {
2151+ __le32 smart_ant:24;
2152+ __le32 se_idx:5;
2153+ __le32 _rsv:3;
2154+
2155+ __le32 _rsv1:8;
2156+ __le32 rmsd_thres:3;
2157+ __le32 _rsv2:5;
2158+ __le32 ibf_timeout:8;
2159+ __le32 _rsv3:8;
2160+
2161+ __le32 _rsv4:16;
2162+ __le32 ibf_data_bw:2;
2163+ __le32 ibf_nc:3;
2164+ __le32 ibf_nr:3;
2165+ __le32 ibf_ru:8;
2166+
2167+ __le32 mob_delta_t:8;
2168+ __le32 mob_lq_result:7;
2169+ __le32 _rsv5:1;
2170+ __le32 _rsv6:16;
2171+
2172+ __le32 _rsv7;
2173+} __packed;
2174+
2175+struct mt7915_tm_pfmu_tag {
2176+ struct mt7915_tm_pfmu_tag1 t1;
2177+ struct mt7915_tm_pfmu_tag2 t2;
2178+};
2179+
2180+struct mt7915_tm_pfmu_data {
2181+ __le16 subc_idx;
2182+ __le16 phi11;
2183+ __le16 phi21;
2184+ __le16 phi31;
2185+};
2186+
2187+struct mt7915_tm_ibf_cal_info {
2188+ u8 format_id;
2189+ u8 group_l_m_n;
2190+ u8 group;
2191+ bool sx2;
2192+ u8 status;
2193+ u8 cal_type;
2194+ u8 _rsv[2];
2195+ u8 buf[1000];
2196+} __packed;
2197+
2198+enum {
2199+ IBF_PHASE_CAL_UNSPEC,
2200+ IBF_PHASE_CAL_NORMAL,
2201+ IBF_PHASE_CAL_VERIFY,
2202+ IBF_PHASE_CAL_NORMAL_INSTRUMENT,
2203+ IBF_PHASE_CAL_VERIFY_INSTRUMENT,
2204+};
2205+
2206 #endif
2207diff --git a/testmode.c b/testmode.c
developer29344f12022-10-17 12:01:44 +08002208index 1d0d5d30..7a9ed543 100644
developer42b63282022-06-16 13:33:13 +08002209--- a/testmode.c
2210+++ b/testmode.c
developerd4975692022-07-15 18:30:03 +08002211@@ -27,28 +27,16 @@ const struct nla_policy mt76_tm_policy[NUM_MT76_TM_ATTRS] = {
developer42b63282022-06-16 13:33:13 +08002212 };
2213 EXPORT_SYMBOL_GPL(mt76_tm_policy);
2214
2215-void mt76_testmode_tx_pending(struct mt76_phy *phy)
2216+static void
2217+mt76_testmode_queue_tx(struct mt76_phy *phy, struct mt76_wcid *wcid,
developer3262bf82022-07-12 11:37:54 +08002218+ struct sk_buff *skb, struct mt76_queue *q, int qid,
2219+ u16 limit)
developer42b63282022-06-16 13:33:13 +08002220 {
2221 struct mt76_testmode_data *td = &phy->test;
2222 struct mt76_dev *dev = phy->dev;
2223- struct mt76_wcid *wcid = &dev->global_wcid;
2224- struct sk_buff *skb = td->tx_skb;
2225- struct mt76_queue *q;
2226- u16 tx_queued_limit;
2227- int qid;
2228-
2229- if (!skb || !td->tx_pending)
2230- return;
2231+ u16 count = limit;
2232
2233- qid = skb_get_queue_mapping(skb);
2234- q = phy->q_tx[qid];
2235-
2236- tx_queued_limit = td->tx_queued_limit ? td->tx_queued_limit : 1000;
2237-
2238- spin_lock_bh(&q->lock);
2239-
2240- while (td->tx_pending > 0 &&
2241- td->tx_queued - td->tx_done < tx_queued_limit &&
2242+ while (td->tx_pending > 0 && count &&
2243 q->queued < q->ndesc / 2) {
2244 int ret;
2245
developerd4975692022-07-15 18:30:03 +08002246@@ -57,13 +45,65 @@ void mt76_testmode_tx_pending(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002247 if (ret < 0)
2248 break;
2249
2250+ count--;
2251 td->tx_pending--;
2252 td->tx_queued++;
2253+
2254+ if (td->tx_rate_mode != MT76_TM_TX_MODE_HE_MU)
2255+ if (td->tx_queued - td->tx_done >= limit)
2256+ break;
2257 }
2258
2259 dev->queue_ops->kick(dev, q);
2260+}
2261+
2262+void mt76_testmode_tx_pending(struct mt76_phy *phy)
2263+{
2264+ struct mt76_testmode_data *td = &phy->test;
2265+ struct mt76_testmode_entry_data *ed;
2266+ struct mt76_queue *q;
2267+ int qid;
2268+ u16 tx_queued_limit;
2269+ u32 remain;
2270+ bool is_mu;
2271+
2272+ if (!td->tx_pending)
2273+ return;
2274+
2275+ /* tx_queued_limit = td->tx_queued_limit ?: 100; */
2276+ tx_queued_limit = 100;
2277+
2278+ if (!td->aid) {
2279+ qid = skb_get_queue_mapping(td->tx_skb);
2280+ q = phy->q_tx[qid];
2281+ spin_lock_bh(&q->lock);
2282+ mt76_testmode_queue_tx(phy, &phy->dev->global_wcid,
developer3262bf82022-07-12 11:37:54 +08002283+ td->tx_skb, q, qid, tx_queued_limit);
developer42b63282022-06-16 13:33:13 +08002284+ spin_unlock_bh(&q->lock);
2285+
2286+ return;
2287+ }
2288+
2289+ is_mu = td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU;
2290+ ed = mt76_testmode_entry_data(phy, td->cur_entry);
2291+ qid = skb_get_queue_mapping(ed->tx_skb);
2292+ q = phy->q_tx[qid];
2293+
2294+ spin_lock_bh(&q->lock);
2295+
2296+ remain = is_mu ? 1 : (td->tx_pending % td->tx_count) ?: td->tx_count;
2297+ if (remain < tx_queued_limit)
2298+ tx_queued_limit = remain;
2299+
developer3262bf82022-07-12 11:37:54 +08002300+ mt76_testmode_queue_tx(phy, td->cur_entry, ed->tx_skb, q, qid, tx_queued_limit);
developer42b63282022-06-16 13:33:13 +08002301+
2302+ if (td->tx_pending % td->tx_count == 0 || is_mu)
2303+ td->cur_entry = list_next_entry(td->cur_entry, list);
2304
2305 spin_unlock_bh(&q->lock);
2306+
2307+ if (is_mu && td->tx_pending)
2308+ mt76_worker_schedule(&phy->dev->tx_worker);
2309 }
2310
2311 static u32
developerd4975692022-07-15 18:30:03 +08002312@@ -89,15 +129,31 @@ mt76_testmode_max_mpdu_len(struct mt76_phy *phy, u8 tx_rate_mode)
developer42b63282022-06-16 13:33:13 +08002313 }
2314
2315 static void
2316-mt76_testmode_free_skb(struct mt76_phy *phy)
2317+mt76_testmode_free_skb(struct sk_buff **tx_skb)
2318+{
2319+ if (!(*tx_skb))
2320+ return;
2321+
2322+ dev_kfree_skb(*tx_skb);
2323+ *tx_skb = NULL;
2324+}
2325+
2326+static void
2327+mt76_testmode_free_skb_all(struct mt76_phy *phy)
2328 {
2329 struct mt76_testmode_data *td = &phy->test;
2330+ struct mt76_testmode_entry_data *ed = &td->ed;
2331+ struct mt76_wcid *wcid;
2332+
2333+ mt76_testmode_free_skb(&ed->tx_skb);
2334
2335- dev_kfree_skb(td->tx_skb);
2336- td->tx_skb = NULL;
2337+ mt76_tm_for_each_entry(phy, wcid, ed)
2338+ mt76_testmode_free_skb(&ed->tx_skb);
2339 }
2340
2341-int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
2342+static int
2343+mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len,
2344+ struct sk_buff **tx_skb, u8 (*addr)[ETH_ALEN])
2345 {
2346 #define MT_TXP_MAX_LEN 4095
2347 u16 fc = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_DATA |
developer4df64ba2022-09-01 14:44:55 +08002348@@ -118,7 +174,8 @@ int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
developer42b63282022-06-16 13:33:13 +08002349 nfrags = len / MT_TXP_MAX_LEN;
2350 head_len = nfrags ? MT_TXP_MAX_LEN : len;
2351
2352- if (len > IEEE80211_MAX_FRAME_LEN)
2353+ if (len > IEEE80211_MAX_FRAME_LEN ||
2354+ td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
2355 fc |= IEEE80211_STYPE_QOS_DATA;
2356
2357 head = alloc_skb(head_len, GFP_KERNEL);
developer4df64ba2022-09-01 14:44:55 +08002358@@ -127,9 +184,9 @@ int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
developer42b63282022-06-16 13:33:13 +08002359
developerd4975692022-07-15 18:30:03 +08002360 hdr = __skb_put_zero(head, sizeof(*hdr));
developer42b63282022-06-16 13:33:13 +08002361 hdr->frame_control = cpu_to_le16(fc);
2362- memcpy(hdr->addr1, td->addr[0], ETH_ALEN);
2363- memcpy(hdr->addr2, td->addr[1], ETH_ALEN);
2364- memcpy(hdr->addr3, td->addr[2], ETH_ALEN);
2365+ memcpy(hdr->addr1, addr[0], ETH_ALEN);
2366+ memcpy(hdr->addr2, addr[1], ETH_ALEN);
2367+ memcpy(hdr->addr3, addr[2], ETH_ALEN);
2368 skb_set_queue_mapping(head, IEEE80211_AC_BE);
developerd4975692022-07-15 18:30:03 +08002369 get_random_bytes(__skb_put(head, head_len - sizeof(*hdr)),
2370 head_len - sizeof(*hdr));
developer4df64ba2022-09-01 14:44:55 +08002371@@ -153,7 +210,7 @@ int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
developer42b63282022-06-16 13:33:13 +08002372
2373 frag = alloc_skb(frag_len, GFP_KERNEL);
2374 if (!frag) {
2375- mt76_testmode_free_skb(phy);
2376+ mt76_testmode_free_skb(tx_skb);
2377 dev_kfree_skb(head);
2378 return -ENOMEM;
2379 }
developer4df64ba2022-09-01 14:44:55 +08002380@@ -166,15 +223,14 @@ int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
developer42b63282022-06-16 13:33:13 +08002381 frag_tail = &(*frag_tail)->next;
2382 }
2383
2384- mt76_testmode_free_skb(phy);
2385- td->tx_skb = head;
2386+ mt76_testmode_free_skb(tx_skb);
2387+ *tx_skb = head;
2388
2389 return 0;
2390 }
2391-EXPORT_SYMBOL(mt76_testmode_alloc_skb);
2392
2393-static int
2394-mt76_testmode_tx_init(struct mt76_phy *phy)
2395+int mt76_testmode_init_skb(struct mt76_phy *phy, u32 len,
2396+ struct sk_buff **tx_skb, u8 (*addr)[ETH_ALEN])
2397 {
2398 struct mt76_testmode_data *td = &phy->test;
2399 struct ieee80211_tx_info *info;
developer4df64ba2022-09-01 14:44:55 +08002400@@ -182,7 +238,7 @@ mt76_testmode_tx_init(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002401 u8 max_nss = hweight8(phy->antenna_mask);
2402 int ret;
2403
2404- ret = mt76_testmode_alloc_skb(phy, td->tx_mpdu_len);
2405+ ret = mt76_testmode_alloc_skb(phy, len, tx_skb, addr);
2406 if (ret)
2407 return ret;
2408
developer4df64ba2022-09-01 14:44:55 +08002409@@ -192,7 +248,7 @@ mt76_testmode_tx_init(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002410 if (td->tx_antenna_mask)
2411 max_nss = min_t(u8, max_nss, hweight8(td->tx_antenna_mask));
2412
2413- info = IEEE80211_SKB_CB(td->tx_skb);
2414+ info = IEEE80211_SKB_CB(*tx_skb);
2415 rate = &info->control.rates[0];
2416 rate->count = 1;
2417 rate->idx = td->tx_rate_idx;
developer4df64ba2022-09-01 14:44:55 +08002418@@ -264,6 +320,25 @@ mt76_testmode_tx_init(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002419 out:
2420 return 0;
2421 }
2422+EXPORT_SYMBOL(mt76_testmode_init_skb);
2423+
2424+static int
2425+mt76_testmode_tx_init(struct mt76_phy *phy)
2426+{
2427+ struct mt76_testmode_entry_data *ed;
2428+ struct mt76_wcid *wcid;
2429+
2430+ mt76_tm_for_each_entry(phy, wcid, ed) {
2431+ int ret;
2432+
2433+ ret = mt76_testmode_init_skb(phy, ed->tx_mpdu_len,
2434+ &ed->tx_skb, ed->addr);
2435+ if (ret)
2436+ return ret;
2437+ }
2438+
2439+ return 0;
2440+}
2441
2442 static void
2443 mt76_testmode_tx_start(struct mt76_phy *phy)
developer4df64ba2022-09-01 14:44:55 +08002444@@ -274,6 +349,14 @@ mt76_testmode_tx_start(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002445 td->tx_queued = 0;
2446 td->tx_done = 0;
2447 td->tx_pending = td->tx_count;
2448+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
2449+ td->tx_pending = 1;
2450+ if (td->entry_num) {
2451+ td->tx_pending *= td->entry_num;
2452+ td->cur_entry = list_first_entry(&td->tm_entry_list,
2453+ struct mt76_wcid, list);
2454+ }
2455+
2456 mt76_worker_schedule(&dev->tx_worker);
2457 }
2458
developer4df64ba2022-09-01 14:44:55 +08002459@@ -292,7 +375,7 @@ mt76_testmode_tx_stop(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002460 wait_event_timeout(dev->tx_wait, td->tx_done == td->tx_queued,
2461 MT76_TM_TIMEOUT * HZ);
2462
2463- mt76_testmode_free_skb(phy);
2464+ mt76_testmode_free_skb_all(phy);
2465 }
2466
2467 static inline void
developer4df64ba2022-09-01 14:44:55 +08002468@@ -323,6 +406,8 @@ mt76_testmode_init_defaults(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002469 memcpy(td->addr[0], phy->macaddr, ETH_ALEN);
2470 memcpy(td->addr[1], phy->macaddr, ETH_ALEN);
2471 memcpy(td->addr[2], phy->macaddr, ETH_ALEN);
2472+
2473+ INIT_LIST_HEAD(&phy->test.tm_entry_list);
2474 }
2475
2476 static int
developer4df64ba2022-09-01 14:44:55 +08002477@@ -332,8 +417,12 @@ __mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state)
developer42b63282022-06-16 13:33:13 +08002478 struct mt76_dev *dev = phy->dev;
2479 int err;
2480
2481- if (prev_state == MT76_TM_STATE_TX_FRAMES)
2482+ if (prev_state == MT76_TM_STATE_TX_FRAMES) {
2483+ /* MU needs to clean hwq for free done event */
2484+ if (phy->test.tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
2485+ dev->test_ops->set_state(phy, MT76_TM_STATE_IDLE);
2486 mt76_testmode_tx_stop(phy);
2487+ }
2488
2489 if (state == MT76_TM_STATE_TX_FRAMES) {
2490 err = mt76_testmode_tx_init(phy);
developer4df64ba2022-09-01 14:44:55 +08002491@@ -403,6 +492,44 @@ mt76_tm_get_u8(struct nlattr *attr, u8 *dest, u8 min, u8 max)
developer42b63282022-06-16 13:33:13 +08002492 return 0;
2493 }
2494
2495+static int
2496+mt76_testmode_set_eeprom(struct mt76_phy *phy, struct nlattr **tb)
2497+{
2498+ struct mt76_dev *dev = phy->dev;
2499+ u8 action, val[MT76_TM_EEPROM_BLOCK_SIZE];
2500+ u32 offset = 0;
2501+ int err = -EINVAL;
2502+
2503+ if (!dev->test_ops->set_eeprom)
2504+ return -EOPNOTSUPP;
2505+
2506+ if (mt76_tm_get_u8(tb[MT76_TM_ATTR_EEPROM_ACTION], &action,
2507+ 0, MT76_TM_EEPROM_ACTION_MAX))
2508+ goto out;
2509+
2510+ if (tb[MT76_TM_ATTR_EEPROM_OFFSET]) {
2511+ struct nlattr *cur;
2512+ int rem, idx = 0;
2513+
2514+ offset = nla_get_u32(tb[MT76_TM_ATTR_EEPROM_OFFSET]);
2515+ if (!!(offset % MT76_TM_EEPROM_BLOCK_SIZE) ||
2516+ !tb[MT76_TM_ATTR_EEPROM_VAL])
2517+ goto out;
2518+
2519+ nla_for_each_nested(cur, tb[MT76_TM_ATTR_EEPROM_VAL], rem) {
2520+ if (nla_len(cur) != 1 || idx >= ARRAY_SIZE(val))
2521+ goto out;
2522+
2523+ val[idx++] = nla_get_u8(cur);
2524+ }
2525+ }
2526+
2527+ err = dev->test_ops->set_eeprom(phy, offset, val, action);
2528+
2529+out:
2530+ return err;
2531+}
2532+
2533 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2534 void *data, int len)
2535 {
developer4df64ba2022-09-01 14:44:55 +08002536@@ -426,6 +553,11 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +08002537
2538 mutex_lock(&dev->mutex);
2539
2540+ if (tb[MT76_TM_ATTR_EEPROM_ACTION]) {
2541+ err = mt76_testmode_set_eeprom(phy, tb);
2542+ goto out;
2543+ }
2544+
2545 if (tb[MT76_TM_ATTR_RESET]) {
2546 mt76_testmode_set_state(phy, MT76_TM_STATE_OFF);
2547 memset(td, 0, sizeof(*td));
developer27b55252022-09-05 19:09:45 +08002548@@ -452,7 +584,10 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +08002549 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_DUTY_CYCLE],
2550 &td->tx_duty_cycle, 0, 99) ||
2551 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_POWER_CONTROL],
2552- &td->tx_power_control, 0, 1))
2553+ &td->tx_power_control, 0, 1) ||
2554+ mt76_tm_get_u8(tb[MT76_TM_ATTR_AID], &td->aid, 0, 16) ||
2555+ mt76_tm_get_u8(tb[MT76_TM_ATTR_RU_ALLOC], &td->ru_alloc, 0, 0xff) ||
2556+ mt76_tm_get_u8(tb[MT76_TM_ATTR_RU_IDX], &td->ru_idx, 0, 68))
2557 goto out;
2558
2559 if (tb[MT76_TM_ATTR_TX_LENGTH]) {
developer27b55252022-09-05 19:09:45 +08002560@@ -484,8 +619,7 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +08002561
2562 if (tb[MT76_TM_ATTR_TX_POWER]) {
2563 struct nlattr *cur;
2564- int idx = 0;
2565- int rem;
2566+ int rem, idx = 0;
2567
2568 nla_for_each_nested(cur, tb[MT76_TM_ATTR_TX_POWER], rem) {
2569 if (nla_len(cur) != 1 ||
developer27b55252022-09-05 19:09:45 +08002570@@ -505,11 +639,45 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +08002571 if (nla_len(cur) != ETH_ALEN || idx >= 3)
2572 goto out;
2573
2574- memcpy(td->addr[idx], nla_data(cur), ETH_ALEN);
2575+ memcpy(td->addr[idx++], nla_data(cur), ETH_ALEN);
2576+ }
2577+ }
2578+
2579+ if (tb[MT76_TM_ATTR_CFG]) {
2580+ struct nlattr *cur;
2581+ int rem, idx = 0;
2582+
2583+ nla_for_each_nested(cur, tb[MT76_TM_ATTR_CFG], rem) {
2584+ if (nla_len(cur) != 1 || idx >= 2)
2585+ goto out;
2586+
2587+ if (idx == 0)
2588+ td->cfg.type = nla_get_u8(cur);
2589+ else
2590+ td->cfg.enable = nla_get_u8(cur);
2591 idx++;
2592 }
2593 }
2594
2595+ if (tb[MT76_TM_ATTR_TXBF_ACT]) {
2596+ struct nlattr *cur;
2597+ int rem, idx = 0;
2598+
2599+ if (!tb[MT76_TM_ATTR_TXBF_PARAM] ||
2600+ mt76_tm_get_u8(tb[MT76_TM_ATTR_TXBF_ACT], &td->txbf_act,
2601+ 0, MT76_TM_TXBF_ACT_MAX))
2602+ goto out;
2603+
2604+ memset(td->txbf_param, 0, sizeof(td->txbf_param));
2605+ nla_for_each_nested(cur, tb[MT76_TM_ATTR_TXBF_PARAM], rem) {
2606+ if (nla_len(cur) != 2 ||
2607+ idx >= ARRAY_SIZE(td->txbf_param))
2608+ goto out;
2609+
2610+ td->txbf_param[idx++] = nla_get_u16(cur);
2611+ }
2612+ }
2613+
2614 if (dev->test_ops->set_params) {
2615 err = dev->test_ops->set_params(phy, tb, state);
2616 if (err)
developer27b55252022-09-05 19:09:45 +08002617@@ -574,6 +742,7 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
developer42b63282022-06-16 13:33:13 +08002618 struct mt76_phy *phy = hw->priv;
2619 struct mt76_dev *dev = phy->dev;
2620 struct mt76_testmode_data *td = &phy->test;
2621+ struct mt76_testmode_entry_data *ed = &td->ed;
2622 struct nlattr *tb[NUM_MT76_TM_ATTRS] = {};
2623 int err = 0;
2624 void *a;
developer27b55252022-09-05 19:09:45 +08002625@@ -606,6 +775,19 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
developer42b63282022-06-16 13:33:13 +08002626 goto out;
2627 }
2628
2629+ if (tb[MT76_TM_ATTR_AID]) {
2630+ struct mt76_wcid *wcid;
2631+ u8 aid;
2632+
2633+ err = mt76_tm_get_u8(tb[MT76_TM_ATTR_AID], &aid, 1, 16);
2634+ if (err)
2635+ goto out;
2636+
2637+ mt76_tm_for_each_entry(phy, wcid, ed)
2638+ if (ed->aid == aid)
2639+ ed = mt76_testmode_entry_data(phy, wcid);
2640+ }
2641+
2642 mt76_testmode_init_defaults(phy);
2643
2644 err = -EMSGSIZE;
developer27b55252022-09-05 19:09:45 +08002645@@ -618,12 +800,8 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
developer42b63282022-06-16 13:33:13 +08002646 goto out;
2647
2648 if (nla_put_u32(msg, MT76_TM_ATTR_TX_COUNT, td->tx_count) ||
2649- nla_put_u32(msg, MT76_TM_ATTR_TX_LENGTH, td->tx_mpdu_len) ||
2650 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_MODE, td->tx_rate_mode) ||
2651- nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_NSS, td->tx_rate_nss) ||
2652- nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_IDX, td->tx_rate_idx) ||
2653 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_SGI, td->tx_rate_sgi) ||
2654- nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_LDPC, td->tx_rate_ldpc) ||
2655 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_STBC, td->tx_rate_stbc) ||
2656 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_LTF) &&
2657 nla_put_u8(msg, MT76_TM_ATTR_TX_LTF, td->tx_ltf)) ||
developer27b55252022-09-05 19:09:45 +08002658@@ -643,6 +821,15 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
developer42b63282022-06-16 13:33:13 +08002659 nla_put_u8(msg, MT76_TM_ATTR_FREQ_OFFSET, td->freq_offset)))
2660 goto out;
2661
2662+ if (nla_put_u32(msg, MT76_TM_ATTR_TX_LENGTH, ed->tx_mpdu_len) ||
2663+ nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_NSS, ed->tx_rate_nss) ||
2664+ nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_IDX, ed->tx_rate_idx) ||
2665+ nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_LDPC, ed->tx_rate_ldpc) ||
2666+ nla_put_u8(msg, MT76_TM_ATTR_AID, ed->aid) ||
2667+ nla_put_u8(msg, MT76_TM_ATTR_RU_ALLOC, ed->ru_alloc) ||
2668+ nla_put_u8(msg, MT76_TM_ATTR_RU_IDX, ed->ru_idx))
2669+ goto out;
2670+
2671 if (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_POWER)) {
2672 a = nla_nest_start(msg, MT76_TM_ATTR_TX_POWER);
2673 if (!a)
2674diff --git a/testmode.h b/testmode.h
developer29344f12022-10-17 12:01:44 +08002675index 89613266..57949f2b 100644
developer42b63282022-06-16 13:33:13 +08002676--- a/testmode.h
2677+++ b/testmode.h
2678@@ -6,6 +6,8 @@
2679 #define __MT76_TESTMODE_H
2680
2681 #define MT76_TM_TIMEOUT 10
2682+#define MT76_TM_MAX_ENTRY_NUM 16
2683+#define MT76_TM_EEPROM_BLOCK_SIZE 16
2684
2685 /**
2686 * enum mt76_testmode_attr - testmode attributes inside NL80211_ATTR_TESTDATA
2687@@ -47,6 +49,15 @@
2688 * @MT76_TM_ATTR_DRV_DATA: driver specific netlink attrs (nested)
2689 *
2690 * @MT76_TM_ATTR_MAC_ADDRS: array of nested MAC addresses (nested)
2691+ *
2692+ * @MT76_TM_ATTR_EEPROM_ACTION: eeprom setting actions
2693+ * (u8, see &enum mt76_testmode_eeprom_action)
2694+ * @MT76_TM_ATTR_EEPROM_OFFSET: offset of eeprom data block for writing (u32)
2695+ * @MT76_TM_ATTR_EEPROM_VAL: values for writing into a 16-byte data block
2696+ * (nested, u8 attrs)
2697+ *
2698+ * @MT76_TM_ATTR_CFG: config testmode rf feature (nested, see &mt76_testmode_cfg)
2699+ *
2700 */
2701 enum mt76_testmode_attr {
2702 MT76_TM_ATTR_UNSPEC,
2703@@ -84,6 +95,17 @@ enum mt76_testmode_attr {
2704 MT76_TM_ATTR_DRV_DATA,
2705
2706 MT76_TM_ATTR_MAC_ADDRS,
2707+ MT76_TM_ATTR_AID,
2708+ MT76_TM_ATTR_RU_ALLOC,
2709+ MT76_TM_ATTR_RU_IDX,
2710+
2711+ MT76_TM_ATTR_EEPROM_ACTION,
2712+ MT76_TM_ATTR_EEPROM_OFFSET,
2713+ MT76_TM_ATTR_EEPROM_VAL,
2714+
2715+ MT76_TM_ATTR_CFG,
2716+ MT76_TM_ATTR_TXBF_ACT,
2717+ MT76_TM_ATTR_TXBF_PARAM,
2718
2719 /* keep last */
2720 NUM_MT76_TM_ATTRS,
2721@@ -198,4 +220,57 @@ enum mt76_testmode_tx_mode {
2722
2723 extern const struct nla_policy mt76_tm_policy[NUM_MT76_TM_ATTRS];
2724
2725+/**
2726+ * enum mt76_testmode_eeprom_action - eeprom setting actions
2727+ *
2728+ * @MT76_TM_EEPROM_ACTION_UPDATE_DATA: update rf values to specific
2729+ * eeprom data block
2730+ * @MT76_TM_EEPROM_ACTION_UPDATE_BUFFER_MODE: send updated eeprom data to fw
2731+ * @MT76_TM_EEPROM_ACTION_WRITE_TO_EFUSE: write eeprom data back to efuse
2732+ */
2733+enum mt76_testmode_eeprom_action {
2734+ MT76_TM_EEPROM_ACTION_UPDATE_DATA,
2735+ MT76_TM_EEPROM_ACTION_UPDATE_BUFFER_MODE,
2736+ MT76_TM_EEPROM_ACTION_WRITE_TO_EFUSE,
2737+
2738+ /* keep last */
2739+ NUM_MT76_TM_EEPROM_ACTION,
2740+ MT76_TM_EEPROM_ACTION_MAX = NUM_MT76_TM_EEPROM_ACTION - 1,
2741+};
2742+
2743+/**
2744+ * enum mt76_testmode_cfg - packet tx phy mode
2745+ *
2746+ * @MT76_TM_EEPROM_ACTION_UPDATE_DATA: update rf values to specific
2747+ * eeprom data block
2748+ * @MT76_TM_EEPROM_ACTION_UPDATE_BUFFER_MODE: send updated eeprom data to fw
2749+ * @MT76_TM_EEPROM_ACTION_WRITE_TO_EFUSE: write eeprom data back to efuse
2750+ */
2751+enum mt76_testmode_cfg {
2752+ MT76_TM_CFG_TSSI,
2753+ MT76_TM_CFG_DPD,
2754+ MT76_TM_CFG_RATE_POWER_OFFSET,
2755+ MT76_TM_CFG_THERMAL_COMP,
2756+
2757+ /* keep last */
2758+ NUM_MT76_TM_CFG,
2759+ MT76_TM_CFG_MAX = NUM_MT76_TM_CFG - 1,
2760+};
2761+
2762+enum mt76_testmode_txbf_act {
2763+ MT76_TM_TXBF_ACT_INIT,
2764+ MT76_TM_TXBF_ACT_UPDATE_CH,
2765+ MT76_TM_TXBF_ACT_PHASE_COMP,
2766+ MT76_TM_TXBF_ACT_TX_PREP,
2767+ MT76_TM_TXBF_ACT_IBF_PROF_UPDATE,
2768+ MT76_TM_TXBF_ACT_EBF_PROF_UPDATE,
2769+ MT76_TM_TXBF_ACT_PHASE_CAL,
2770+ MT76_TM_TXBF_ACT_PROF_UPDATE_ALL,
2771+ MT76_TM_TXBF_ACT_E2P_UPDATE,
2772+
2773+ /* keep last */
2774+ NUM_MT76_TM_TXBF_ACT,
2775+ MT76_TM_TXBF_ACT_MAX = NUM_MT76_TM_TXBF_ACT - 1,
2776+};
2777+
2778 #endif
2779diff --git a/tools/fields.c b/tools/fields.c
developer29344f12022-10-17 12:01:44 +08002780index e3f69089..6e36ab27 100644
developer42b63282022-06-16 13:33:13 +08002781--- a/tools/fields.c
2782+++ b/tools/fields.c
2783@@ -10,6 +10,7 @@ static const char * const testmode_state[] = {
2784 [MT76_TM_STATE_IDLE] = "idle",
2785 [MT76_TM_STATE_TX_FRAMES] = "tx_frames",
2786 [MT76_TM_STATE_RX_FRAMES] = "rx_frames",
2787+ [MT76_TM_STATE_TX_CONT] = "tx_cont",
2788 };
2789
2790 static const char * const testmode_tx_mode[] = {
2791@@ -201,6 +202,63 @@ static void print_extra_stats(const struct tm_field *field, struct nlattr **tb)
2792 printf("%srx_per=%.02f%%\n", prefix, 100 * failed / total);
2793 }
2794
2795+static bool parse_mac(const struct tm_field *field, int idx,
2796+ struct nl_msg *msg, const char *val)
2797+{
2798+#define ETH_ALEN 6
2799+ bool ret = true;
2800+ char *str, *cur, *ap;
2801+ void *a;
2802+
2803+ ap = str = strdup(val);
2804+
2805+ a = nla_nest_start(msg, idx);
2806+
2807+ idx = 0;
2808+ while ((cur = strsep(&ap, ",")) != NULL) {
2809+ unsigned char addr[ETH_ALEN];
2810+ char *val, *tmp = cur;
2811+ int i = 0;
2812+
2813+ while ((val = strsep(&tmp, ":")) != NULL) {
2814+ if (i >= ETH_ALEN)
2815+ break;
2816+
2817+ addr[i++] = strtoul(val, NULL, 16);
2818+ }
2819+
2820+ nla_put(msg, idx, ETH_ALEN, addr);
2821+
2822+ idx++;
2823+ }
2824+
2825+ nla_nest_end(msg, a);
2826+
2827+ free(str);
2828+
2829+ return ret;
2830+}
2831+
2832+static void print_mac(const struct tm_field *field, struct nlattr *attr)
2833+{
2834+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
2835+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
2836+ unsigned char addr[3][6];
2837+ struct nlattr *cur;
2838+ int idx = 0;
2839+ int rem;
2840+
2841+ nla_for_each_nested(cur, attr, rem) {
2842+ if (nla_len(cur) != 6)
2843+ continue;
2844+ memcpy(addr[idx++], nla_data(cur), 6);
2845+ }
2846+
2847+ printf("" MACSTR "," MACSTR "," MACSTR "",
2848+ MAC2STR(addr[0]), MAC2STR(addr[1]), MAC2STR(addr[2]));
2849+
2850+ return;
2851+}
2852
2853 #define FIELD_GENERIC(_field, _name, ...) \
2854 [FIELD_NAME(_field)] = { \
2855@@ -250,6 +308,13 @@ static void print_extra_stats(const struct tm_field *field, struct nlattr **tb)
2856 ##__VA_ARGS__ \
2857 )
2858
2859+#define FIELD_MAC(_field, _name) \
2860+ [FIELD_NAME(_field)] = { \
2861+ .name = _name, \
2862+ .parse = parse_mac, \
2863+ .print = print_mac \
2864+ }
2865+
2866 #define FIELD_NAME(_field) MT76_TM_RX_ATTR_##_field
2867 static const struct tm_field rx_fields[NUM_MT76_TM_RX_ATTRS] = {
2868 FIELD_RO(s32, FREQ_OFFSET, "freq_offset"),
2869@@ -300,10 +365,18 @@ static const struct tm_field testdata_fields[NUM_MT76_TM_ATTRS] = {
2870 FIELD(u8, TX_RATE_LDPC, "tx_rate_ldpc"),
2871 FIELD(u8, TX_RATE_STBC, "tx_rate_stbc"),
2872 FIELD(u8, TX_LTF, "tx_ltf"),
2873+ FIELD(u8, TX_DUTY_CYCLE, "tx_duty_cycle"),
2874+ FIELD(u32, TX_IPG, "tx_ipg"),
2875+ FIELD(u32, TX_TIME, "tx_time"),
2876 FIELD(u8, TX_POWER_CONTROL, "tx_power_control"),
2877 FIELD_ARRAY(u8, TX_POWER, "tx_power"),
2878 FIELD(u8, TX_ANTENNA, "tx_antenna"),
2879+ FIELD(u8, TX_SPE_IDX, "tx_spe_idx"),
2880 FIELD(u32, FREQ_OFFSET, "freq_offset"),
2881+ FIELD(u8, AID, "aid"),
2882+ FIELD(u8, RU_ALLOC, "ru_alloc"),
2883+ FIELD(u8, RU_IDX, "ru_idx"),
2884+ FIELD_MAC(MAC_ADDRS, "mac_addrs"),
2885 FIELD_NESTED_RO(STATS, stats, "",
2886 .print_extra = print_extra_stats),
2887 };
2888@@ -322,9 +395,16 @@ static struct nla_policy testdata_policy[NUM_MT76_TM_ATTRS] = {
2889 [MT76_TM_ATTR_TX_RATE_LDPC] = { .type = NLA_U8 },
2890 [MT76_TM_ATTR_TX_RATE_STBC] = { .type = NLA_U8 },
2891 [MT76_TM_ATTR_TX_LTF] = { .type = NLA_U8 },
2892+ [MT76_TM_ATTR_TX_DUTY_CYCLE] = { .type = NLA_U8 },
2893+ [MT76_TM_ATTR_TX_IPG] = { .type = NLA_U32 },
2894+ [MT76_TM_ATTR_TX_TIME] = { .type = NLA_U32 },
2895 [MT76_TM_ATTR_TX_POWER_CONTROL] = { .type = NLA_U8 },
2896 [MT76_TM_ATTR_TX_ANTENNA] = { .type = NLA_U8 },
2897+ [MT76_TM_ATTR_TX_SPE_IDX] = { .type = NLA_U8 },
2898 [MT76_TM_ATTR_FREQ_OFFSET] = { .type = NLA_U32 },
2899+ [MT76_TM_ATTR_AID] = { .type = NLA_U8 },
2900+ [MT76_TM_ATTR_RU_ALLOC] = { .type = NLA_U8 },
2901+ [MT76_TM_ATTR_RU_IDX] = { .type = NLA_U8 },
2902 [MT76_TM_ATTR_STATS] = { .type = NLA_NESTED },
2903 };
2904
2905diff --git a/tx.c b/tx.c
developer29344f12022-10-17 12:01:44 +08002906index 65e2b7c1..8b33186b 100644
developer42b63282022-06-16 13:33:13 +08002907--- a/tx.c
2908+++ b/tx.c
2909@@ -245,8 +245,7 @@ void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid_idx, struct sk_buff *
2910 if (mt76_is_testmode_skb(dev, skb, &hw)) {
2911 struct mt76_phy *phy = hw->priv;
2912
2913- if (skb == phy->test.tx_skb)
2914- phy->test.tx_done++;
2915+ phy->test.tx_done++;
2916 if (phy->test.tx_queued == phy->test.tx_done)
2917 wake_up(&dev->tx_wait);
2918
2919--
developer2cbf2fb2022-11-16 12:20:48 +080029202.18.0
developer42b63282022-06-16 13:33:13 +08002921