blob: d021759b5c33026ca2318f7b813ad34673bf7fe9 [file] [log] [blame]
developer05f3b2b2024-08-19 19:17:34 +08001From 84de1f40cbb93804a270e3d70824ccf8e8e5f1e7 Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +08002From: "sujuan.chen" <sujuan.chen@mediatek.com>
3Date: Fri, 6 Oct 2023 14:01:41 +0800
developer05f3b2b2024-08-19 19:17:34 +08004Subject: [PATCH 066/199] mtk: mt76: change pcie0 R5 to pcie1 to get 6G ICS
developer66e89bc2024-04-23 14:50:01 +08005
developer66e89bc2024-04-23 14:50:01 +08006---
7 mt7996/dma.c | 4 ++++
8 mt7996/init.c | 6 ++----
9 mt7996/mmio.c | 5 ++++-
10 3 files changed, 10 insertions(+), 5 deletions(-)
11
12diff --git a/mt7996/dma.c b/mt7996/dma.c
developer05f3b2b2024-08-19 19:17:34 +080013index 759a58e8..5d85e9ea 100644
developer66e89bc2024-04-23 14:50:01 +080014--- a/mt7996/dma.c
15+++ b/mt7996/dma.c
16@@ -538,6 +538,10 @@ int mt7996_dma_init(struct mt7996_dev *dev)
17 if (mt7996_band_valid(dev, MT_BAND2)) {
18 /* rx data queue for mt7996 band2 */
19 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs;
20+ if (mtk_wed_device_active(wed_hif2) && mtk_wed_get_rx_capa(wed_hif2)) {
21+ dev->mt76.q_rx[MT_RXQ_BAND2].flags = MT_WED_Q_RX(0);
22+ dev->mt76.q_rx[MT_RXQ_BAND2].wed = wed_hif2;
23+ }
24 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2],
25 MT_RXQ_ID(MT_RXQ_BAND2),
26 MT7996_RX_RING_SIZE,
27diff --git a/mt7996/init.c b/mt7996/init.c
developer05f3b2b2024-08-19 19:17:34 +080028index 8b642ecc..6563974d 100644
developer66e89bc2024-04-23 14:50:01 +080029--- a/mt7996/init.c
30+++ b/mt7996/init.c
developer05f3b2b2024-08-19 19:17:34 +080031@@ -651,10 +651,8 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
developer66e89bc2024-04-23 14:50:01 +080032 goto error;
33
34 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) {
35- u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2;
36-
37- mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask);
38- mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask);
39+ mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT);
40+ mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, MT_INT_TX_RX_DONE_EXT);
41 }
42
43 return 0;
44diff --git a/mt7996/mmio.c b/mt7996/mmio.c
developer05f3b2b2024-08-19 19:17:34 +080045index 928a9663..7940621b 100644
developer66e89bc2024-04-23 14:50:01 +080046--- a/mt7996/mmio.c
47+++ b/mt7996/mmio.c
48@@ -527,12 +527,15 @@ static void mt7996_irq_tasklet(struct tasklet_struct *t)
49 dev->mt76.mmio.irqmask);
50 if (intr1 & MT_INT_RX_TXFREE_EXT)
51 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]);
52+
53+ if (intr1 & MT_INT_RX_DONE_BAND2_EXT)
54+ napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]);
55 }
56
57 if (mtk_wed_device_active(wed)) {
58 mtk_wed_device_irq_set_mask(wed, 0);
59 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
60- intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT);
61+ intr |= (intr1 & ~MT_INT_TX_RX_DONE_EXT);
62 } else {
63 mt76_wr(dev, MT_INT_MASK_CSR, 0);
64 if (dev->hif2)
65--
developer9237f442024-06-14 17:13:04 +0800662.18.0
developer66e89bc2024-04-23 14:50:01 +080067