| developer | 880c829 | 2022-07-11 11:52:59 +0800 | [diff] [blame] | 1 | #define atoi(x) strtoul(x, NULL,10) |
| 2 | |
| 3 | #define EXTEND_SETVID_PARAM 1 |
| 4 | #define SQA_VERIFY 1 |
| 5 | #define ETHCMD_DBG 1 |
| 6 | #define ACTIVED (1<<0) |
| 7 | #define SWITCH_MAX_PORT 7 |
| 8 | |
| 9 | #define GENERAL_TABLE 0 |
| 10 | #define COLLISION_TABLE 1 |
| 11 | |
| 12 | #define GSW_BASE 0x0 |
| 13 | #define GSW_ARL_BASE (GSW_BASE + 0x0000) |
| 14 | #define GSW_BMU_BASE (GSW_BASE + 0x1000) |
| 15 | #define GSW_PORT_BASE (GSW_BASE + 0x2000) |
| 16 | #define GSW_MAC_BASE (GSW_BASE + 0x3000) |
| 17 | #define GSW_MIB_BASE (GSW_BASE + 0x4000) |
| 18 | #define GSW_CFG_BASE (GSW_BASE + 0x7000) |
| 19 | |
| 20 | #define GSW_PCR(n) (GSW_PORT_BASE + (n)*0x100 + 0x04) |
| 21 | #define GSW_MFC (GSW_ARL_BASE + 0x10) |
| 22 | #define GSW_UPW(n) (GSW_PORT_BASE + (n)*0x100 + 0x40) |
| 23 | //#define GSW_PEM(n) (GSW_ARL_BASE + (n)*0x4 + 0x48) |
| 24 | #define GSW_PEM(n) (GSW_PORT_BASE + (n)*0x4 + 0x44) |
| 25 | |
| 26 | #define GSW_MMSCR0_Q(n) (GSW_BMU_BASE + (n)*0x8) |
| 27 | #define GSW_MMSCR1_Q(n) (GSW_BMU_BASE + (n)*0x8 + 0x04) |
| 28 | |
| 29 | #define GSW_PMCR(n) (GSW_MAC_BASE + (n)*0x100) |
| 30 | #define GSW_PMSR(n) (GSW_MAC_BASE + (n)*0x100 + 0x08) |
| 31 | #define GSW_PINT_EN(n) (GSW_MAC_BASE + (n)*0x100 + 0x10) |
| 32 | #define GSW_SMACCR0 (GSW_MAC_BASE + 0xe4) |
| 33 | #define GSW_SMACCR1 (GSW_MAC_BASE + 0xe8) |
| 34 | #define GSW_CKGCR (GSW_MAC_BASE + 0xf0) |
| 35 | |
| 36 | #define GSW_ESR(n) (GSW_MIB_BASE + (n)*0x100 + 0x00) |
| 37 | #define GSW_INTS(n) (GSW_MIB_BASE + (n)*0x100 + 0x04) |
| 38 | #define GSW_TGPC(n) (GSW_MIB_BASE + (n)*0x100 + 0x10) |
| 39 | #define GSW_TBOC(n) (GSW_MIB_BASE + (n)*0x100 + 0x14) |
| 40 | #define GSW_TGOC(n) (GSW_MIB_BASE + (n)*0x100 + 0x18) |
| 41 | #define GSW_TEPC(n) (GSW_MIB_BASE + (n)*0x100 + 0x1C) |
| 42 | #define GSW_RGPC(n) (GSW_MIB_BASE + (n)*0x100 + 0x20) |
| 43 | #define GSW_RBOC(n) (GSW_MIB_BASE + (n)*0x100 + 0x24) |
| 44 | #define GSW_RGOC(n) (GSW_MIB_BASE + (n)*0x100 + 0x28) |
| 45 | #define GSW_REPC1(n) (GSW_MIB_BASE + (n)*0x100 + 0x2C) |
| 46 | #define GSW_REPC2(n) (GSW_MIB_BASE + (n)*0x100 + 0x30) |
| 47 | #define GSW_MIBCNTEN (GSW_MIB_BASE + 0x800) |
| 48 | #define GSW_AECNT1 (GSW_MIB_BASE + 0x804) |
| 49 | #define GSW_AECNT2 (GSW_MIB_BASE + 0x808) |
| 50 | |
| 51 | #define GSW_CFG_PPSC (GSW_CFG_BASE + 0x0) |
| 52 | #define GSW_CFG_PIAC (GSW_CFG_BASE + 0x4) |
| 53 | #define GSW_CFG_GPC (GSW_CFG_BASE + 0x14) |
| 54 | |
| 55 | #define MAX_VID_VALUE (4095) |
| 56 | #define MAX_VLAN_RULE (16) |
| 57 | |
| 58 | |
| 59 | #define REG_MFC_ADDR (0x0010) |
| 60 | #define REG_ISC_ADDR (0x0018) |
| 61 | |
| 62 | #define REG_CFC_ADDR (0x0004) |
| 63 | #define REG_CFC_MIRROR_PORT_OFFT (16) |
| 64 | #define REG_CFC_MIRROR_PORT_LENG (3) |
| 65 | #define REG_CFC_MIRROR_PORT_RELMASK (0x00000007) |
| 66 | #define REG_CFC_MIRROR_PORT_MASK (REG_CFC_MIRROR_PORT_RELMASK << REG_CFC_MIRROR_PORT_OFFT) |
| 67 | #define REG_CFC_MIRROR_EN_OFFT (19) |
| 68 | #define REG_CFC_MIRROR_EN_LENG (1) |
| 69 | #define REG_CFC_MIRROR_EN_RELMASK (0x00000001) |
| 70 | #define REG_CFC_MIRROR_EN_MASK (REG_CFC_MIRROR_EN_RELMASK << REG_CFC_MIRROR_EN_OFFT) |
| 71 | |
| 72 | #define REG_ATA1_ADDR (0x0074) |
| 73 | #define REG_ATA2_ADDR (0x0078) |
| 74 | |
| 75 | #define REG_ATWD_ADDR (0x007C) |
| 76 | #define REG_ATWD_STATUS_OFFT (2) |
| 77 | #define REG_ATWD_STATUS_LENG (2) |
| 78 | #define REG_ATWD_STATUS_RELMASK (0x00000003) |
| 79 | #define REG_ATWD_STATUS_MASK (REG_ATWD_STATUS_RELMASK << REG_ATWD_STATUS_OFFT) |
| 80 | #define REG_ATWD_PORT_OFFT (4) |
| 81 | #define REG_ATWD_PORT_LENG (8) |
| 82 | #define REG_ATWD_PORT_RELMASK (0x000000FF) |
| 83 | #define REG_ATWD_PORT_MASK (REG_ATWD_PORT_RELMASK << REG_ATWD_PORT_OFFT) |
| 84 | #define REG_ATWD_LEAKY_EN_OFFT (12) |
| 85 | #define REG_ATWD_LEAKY_EN_LENG (1) |
| 86 | #define REG_ATWD_LEAKY_EN_RELMASK (0x00000001) |
| 87 | #define REG_ATWD_LEAKY_EN_MASK (REG_ATWD_LEAKY_EN_RELMASK << REG_ATWD_LEAKY_EN_OFFT) |
| 88 | #define REG_ATWD_EG_TAG_OFFT (13) |
| 89 | #define REG_ATWD_EG_TAG_LENG (3) |
| 90 | #define REG_ATWD_EG_TAG_RELMASK (0x00000007) |
| 91 | #define REG_ATWD_EG_TAG_MASK (REG_ATWD_EG_TAG_RELMASK << REG_ATWD_EG_TAG_OFFT) |
| 92 | #define REG_ATWD_USR_PRI_OFFT (16) |
| 93 | #define REG_ATWD_USR_PRI_LENG (3) |
| 94 | #define REG_ATWD_USR_PRI_RELMASK (0x00000007) |
| 95 | #define REG_ATWD_USR_PRI_MASK (REG_ATWD_USR_PRI_RELMASK << REG_ATWD_USR_PRI_OFFT) |
| 96 | #define REG_ATWD_SA_MIR_EN_OFFT (19) |
| 97 | #define REG_ATWD_SA_MIR_EN_LENG (1) |
| 98 | #define REG_ATWD_SA_MIR_EN_RELMASK (0x00000001) |
| 99 | #define REG_ATWD_SA_MIR_EN_MASK (REG_ATWD_SA_MIR_EN_RELMASK << REG_ATWD_SA_MIR_EN_OFFT) |
| 100 | #define REG_ATWD_SA_PORT_FW_OFFT (20) |
| 101 | #define REG_ATWD_SA_PORT_FW_LENG (3) |
| 102 | #define REG_ATWD_SA_PORT_FW_RELMASK (0x00000007) |
| 103 | #define REG_ATWD_SA_PORT_FW_MASK (REG_ATWD_SA_PORT_FW_RELMASK << REG_ATWD_SA_PORT_FW_OFFT) |
| 104 | |
| 105 | #define REG_ATC_ADDR (0x0080) |
| 106 | #define REG_ATC_AC_CMD_OFFT (0) |
| 107 | #define REG_ATC_AC_CMD_LENG (3) |
| 108 | #define REG_ATC_AC_CMD_RELMASK (0x00000007) |
| 109 | #define REG_ATC_AC_CMD_MASK (REG_ATC_AC_CMD_RELMASK << REG_ATC_AC_CMD_OFFT) |
| 110 | #define REG_ATC_AC_SAT_OFFT (4) |
| 111 | #define REG_ATC_AC_SAT_LENG (2) |
| 112 | #define REG_ATC_AC_SAT_RELMASK (0x00000003) |
| 113 | #define REG_ATC_AC_SAT_MASK (REG_ATC_AC_SAT_RELMASK << REG_ATC_AC_SAT_OFFT) |
| 114 | #define REG_ATC_AC_MAT_OFFT (8) |
| 115 | #define REG_ATC_AC_MAT_LENG (4) |
| 116 | #define REG_ATC_AC_MAT_RELMASK (0x0000000F) |
| 117 | #define REG_ATC_AC_MAT_MASK (REG_ATC_AC_MAT_RELMASK << REG_ATC_AC_MAT_OFFT) |
| 118 | #define REG_AT_SRCH_HIT_OFFT (13) |
| 119 | #define REG_AT_SRCH_HIT_RELMASK (0x00000001) |
| 120 | #define REG_AT_SRCH_HIT_MASK (REG_AT_SRCH_HIT_RELMASK << REG_AT_SRCH_HIT_OFFT) |
| 121 | #define REG_AT_SRCH_END_OFFT (14) |
| 122 | #define REG_AT_SRCH_END_RELMASK (0x00000001) |
| 123 | #define REG_AT_SRCH_END_MASK (REG_AT_SRCH_END_RELMASK << REG_AT_SRCH_END_OFFT) |
| 124 | #define REG_ATC_BUSY_OFFT (15) |
| 125 | #define REG_ATC_BUSY_LENG (1) |
| 126 | #define REG_ATC_BUSY_RELMASK (0x00000001) |
| 127 | #define REG_ATC_BUSY_MASK (REG_ATC_BUSY_RELMASK << REG_ATC_BUSY_OFFT) |
| 128 | #define REG_AT_ADDR_OFFT (16) |
| 129 | #define REG_AT_ADDR_LENG (12) |
| 130 | #define REG_AT_ADDR_RELMASK (0x00000FFF) |
| 131 | #define REG_AT_ADDR_MASK (REG_AT_ADDR_RELMASK << REG_AT_ADDR_OFFT) |
| 132 | |
| 133 | #define REG_TSRA1_ADDR (0x0084) |
| 134 | #define REG_TSRA2_ADDR (0x0088) |
| 135 | #define REG_ATRD_ADDR (0x008C) |
| 136 | |
| 137 | #define REG_VTCR_ADDR (0x0090) |
| 138 | #define REG_VTCR_VID_OFFT (0) |
| 139 | #define REG_VTCR_VID_LENG (12) |
| 140 | #define REG_VTCR_VID_RELMASK (0x00000FFF) |
| 141 | #define REG_VTCR_VID_MASK (REG_VTCR_VID_RELMASK << REG_VTCR_VID_OFFT) |
| 142 | #define REG_VTCR_FUNC_OFFT (12) |
| 143 | #define REG_VTCR_FUNC_LENG (4) |
| 144 | #define REG_VTCR_FUNC_RELMASK (0x0000000F) |
| 145 | #define REG_VTCR_FUNC_MASK (REG_VTCR_FUNC_RELMASK << REG_VTCR_FUNC_OFFT) |
| 146 | #define REG_VTCR_IDX_INVLD_OFFT (16) |
| 147 | #define REG_VTCR_IDX_INVLD_RELMASK (0x00000001) |
| 148 | #define REG_VTCR_IDX_INVLD_MASK (REG_VTCR_IDX_INVLD_RELMASK << REG_VTCR_IDX_INVLD_OFFT) |
| 149 | #define REG_VTCR_BUSY_OFFT (31) |
| 150 | #define REG_VTCR_BUSY_RELMASK (0x00000001) |
| 151 | #define REG_VTCR_BUSY_MASK (REG_VTCR_BUSY_RELMASK << REG_VTCR_BUSY_OFFT) |
| 152 | |
| 153 | #define REG_VAWD1_ADDR (0x0094) |
| 154 | #define REG_VAWD2_ADDR (0x0098) |
| 155 | #define REG_VLAN_ID_BASE (0x0100) |
| 156 | |
| developer | cc8110b | 2024-08-19 13:53:34 +0800 | [diff] [blame] | 157 | #define REG_CPGC_ADDR (0xB0) |
| developer | 880c829 | 2022-07-11 11:52:59 +0800 | [diff] [blame] | 158 | #define REG_CPCG_COL_EN_OFFT (0) |
| 159 | #define REG_CPCG_COL_EN_RELMASK (0x00000001) |
| 160 | #define REG_CPCG_COL_EN_MASK (REG_CPCG_COL_EN_RELMASK << REG_CPCG_COL_EN_OFFT) |
| 161 | #define REG_CPCG_COL_CLK_EN_OFFT (1) |
| 162 | #define REG_CPCG_COL_CLK_EN_RELMASK (0x00000001) |
| 163 | #define REG_CPCG_COL_CLK_EN_MASK (REG_CPCG_COL_CLK_EN_RELMASK << REG_CPCG_COL_CLK_EN_OFFT) |
| 164 | #define REG_CPCG_COL_RST_N_OFFT (2) |
| 165 | #define REG_CPCG_COL_RST_N_RELMASK (0x00000001) |
| 166 | #define REG_CPCG_COL_RST_N_MASK (REG_CPCG_COL_RST_N_RELMASK << REG_CPCG_COL_RST_N_OFFT) |
| 167 | |
| 168 | #define REG_GFCCR0_ADDR (0x1FE0) |
| 169 | #define REG_FC_EN_OFFT (31) |
| 170 | #define REG_FC_EN_RELMASK (0x00000001) |
| 171 | #define REG_FC_EN_MASK (REG_FC_EN_RELMASK << REG_FC_EN_OFFT) |
| 172 | |
| 173 | #define REG_PFC_CTRL_ADDR (0x30b0) |
| 174 | #define PFC_RX_COUNTER_L(n) (0x3030 + (n)*0x100) |
| 175 | #define PFC_RX_COUNTER_H(n) (0x3034 + (n)*0x100) |
| 176 | #define PFC_TX_COUNTER_L(n) (0x3040 + (n)*0x100) |
| 177 | #define PFC_TX_COUNTER_H(n) (0x3044 + (n)*0x100) |
| 178 | #define PMSR_P(n) (0x3008 + (n)*0x100) |
| 179 | |
| 180 | |
| 181 | #define REG_SSC_P0_ADDR (0x2000) |
| 182 | |
| 183 | #define REG_PCR_P0_ADDR (0x2004) |
| 184 | #define REG_PCR_VLAN_MIS_OFFT (2) |
| 185 | #define REG_PCR_VLAN_MIS_LENG (1) |
| 186 | #define REG_PCR_VLAN_MIS_RELMASK (0x00000001) |
| 187 | #define REG_PCR_VLAN_MIS_MASK (REG_PCR_VLAN_MIS_RELMASK << REG_PCR_VLAN_MIS_OFFT) |
| 188 | #define REG_PCR_ACL_MIR_OFFT (7) |
| 189 | #define REG_PCR_ACL_MIR_LENG (1) |
| 190 | #define REG_PCR_ACL_MIR_RELMASK (0x00000001) |
| 191 | #define REG_PCR_ACL_MIR_MASK (REG_PCR_ACL_MIR_RELMASK << REG_PCR_ACL_MIR_OFFT) |
| 192 | #define REG_PORT_RX_MIR_OFFT (8) |
| 193 | #define REG_PORT_RX_MIR_LENG (1) |
| 194 | #define REG_PORT_RX_MIR_RELMASK (0x00000001) |
| 195 | #define REG_PORT_RX_MIR_MASK (REG_PORT_RX_MIR_RELMASK << REG_PORT_RX_MIR_OFFT) |
| 196 | #define REG_PORT_TX_MIR_OFFT (9) |
| 197 | #define REG_PORT_TX_MIR_LENG (1) |
| 198 | #define REG_PORT_TX_MIR_RELMASK (0x00000001) |
| 199 | #define REG_PORT_TX_MIR_MASK (REG_PORT_TX_MIR_RELMASK << REG_PORT_TX_MIR_OFFT) |
| 200 | #define REG_PORT_ACL_EN_OFFT (10) |
| 201 | #define REG_PORT_ACL_EN_LENG (1) |
| 202 | #define REG_PORT_ACL_EN_RELMASK (0x00000001) |
| 203 | #define REG_PORT_ACL_EN_MASK (REG_PORT_ACL_EN_RELMASK << REG_PORT_ACL_EN_OFFT) |
| 204 | #define REG_PCR_EG_TAG_OFFT (28) |
| 205 | #define REG_PCR_EG_TAG_LENG (2) |
| 206 | #define REG_PCR_EG_TAG_RELMASK (0x00000003) |
| 207 | #define REG_PCR_EG_TAG_MASK (REG_PCR_EG_TAG_RELMASK << REG_PCR_EG_TAG_OFFT) |
| 208 | |
| 209 | #define REG_PIC_P0_ADDR (0x2008) |
| 210 | #define REG_PIC_IGMP_MIR_OFFT (19) |
| 211 | #define REG_PIC_IGMP_MIR_LENG (1) |
| 212 | #define REG_PIC_IGMP_MIR_RELMASK (0x00000001) |
| 213 | #define REG_PIC_IGMP_MIR_MASK (REG_PIC_IGMP_MIR_RELMASK << REG_PIC_IGMP_MIR_OFFT) |
| 214 | |
| 215 | #define REG_PSC_P0_ADDR (0x200C) |
| 216 | |
| 217 | #define REG_PVC_P0_ADDR (0x2010) |
| 218 | #define REG_PVC_ACC_FRM_OFFT (0) |
| 219 | #define REG_PVC_ACC_FRM_LENG (2) |
| 220 | #define REG_PVC_ACC_FRM_RELMASK (0x00000003) |
| 221 | #define REG_PVC_ACC_FRM_MASK (REG_PVC_ACC_FRM_RELMASK << REG_PVC_ACC_FRM_OFFT) |
| 222 | #define REG_PVC_EG_TAG_OFFT (8) |
| 223 | #define REG_PVC_EG_TAG_LENG (3) |
| 224 | #define REG_PVC_EG_TAG_RELMASK (0x00000007) |
| 225 | #define REG_PVC_EG_TAG_MASK (REG_PVC_EG_TAG_RELMASK << REG_PVC_EG_TAG_OFFT) |
| 226 | |
| 227 | #define REG_PPBV1_P0_ADDR (0x2014) |
| 228 | #define REG_PPBV2_P0_ADDR (0x2018) |
| 229 | #define REG_BSR_P0_ADDR (0x201C) |
| 230 | #define REG_STAG01_P0_ADDR (0x2020) |
| 231 | #define REG_STAG23_P0_ADDR (0x2024) |
| 232 | #define REG_STAG45_P0_ADDR (0x2028) |
| 233 | #define REG_STAG67_P0_ADDR (0x202C) |
| 234 | |
| 235 | #define REG_CMACCR_ADDR (0x30E0) |
| 236 | #define REG_MTCC_LMT_OFFT (9) |
| 237 | #define REG_MTCC_LMT_LENG (4) |
| 238 | #define REG_MTCC_LMT_RELMASK (0x0000000F) |
| 239 | #define REG_MTCC_LMT_MASK (REG_MTCC_LMT_RELMASK << REG_MTCC_LMT_OFFT) |
| 240 | |
| 241 | #define ETHCMD_ENABLE "enable" |
| 242 | #define ETHCMD_DISABLE "disable" |
| 243 | |
| 244 | #define HELP_VLAN_PVID "vlan pvid <port> <pvid>" |
| 245 | |
| 246 | #if defined(EXTEND_SETVID_PARAM) || defined(SQA_VERIFY) |
| 247 | #define HELP_VLAN_VID "vlan vid <index> <active:0|1> <vid> <portMap> <egtagPortMap>\n" \ |
| 248 | " <ivl_en> <fid> <stag>\n" |
| 249 | #else |
| 250 | #define HELP_VLAN_VID "vlan vid <index> <active:0|1> <vid> <portMap> <tagPortMap>\n" |
| 251 | #endif //SQA_VERIFY |
| 252 | |
| 253 | //#if defined(SQA_VERIFY) |
| 254 | |
| 255 | #define MT7530_UPW_REG_UPDATE 1 |
| 256 | |
| 257 | #define HELP_QOS_TYPE "qos type <rr:0|sp:1|wfq:2>\n" |
| 258 | #ifdef MT7530_UPW_REG_UPDATE |
| 259 | #define HELP_QOS_BASE "qos base <port-based:0|tag-based:1|dscp-based:2|acl-based:3|arl-based:4|stag-based:5>\n" |
| 260 | #else |
| 261 | #define HELP_QOS_BASE "qos base <port-based:0|tag-based:1|dscp-based:2|acl-based:3|arl-based:4>\n" |
| 262 | #endif |
| 263 | #define HELP_QOS_PRIO_QMAP "qos prio-qmap <prio:0~7> <queue:0~7>\n" |
| 264 | #define HELP_QOS_PRIO_TAGMAP "qos prio-tagmap <prio:0~7> <tag:0~7>\n" |
| 265 | #define HELP_QOS_PRIO_DSCPMAP "qos prio-dscpmap <prio:0~7> <dscp:0~63>\n" |
| 266 | //#define HELP_QOS_VPRI_QMAP "qos vprio-qmap <prio:0~7> <queue:0~7>\n" |
| 267 | #define HELP_QOS_PORT_PRIO "qos port-prio <port> <prio:0~7>\n" |
| 268 | #define HELP_QOS_PORT_WEIGHT "qos port-weight <port:0~7> <q0> <q1> <q2> <q3> <q4> <q5> <q6> <q7>\n" \ |
| 269 | " <qn>: the weight of queue n, range: 1~16\n" |
| 270 | #define HELP_QOS_DSCP_PRIO "qos dscp-prio <dscp:0~63> <prio:0~7> : for ingress\n" |
| 271 | |
| 272 | #define HELP_ARL_L2LEN_CHK "arl l2len-chk <active:0|1>\n" |
| 273 | |
| 274 | #define HELP_ARL_AGING "arl aging <active:0|1> <time:1~65536>\n" |
| 275 | |
| 276 | #define HELP_ARL_MAC_TBL_ADD "arl mactbl-add <MacAddr> <DestPortMap>\n"\ |
| 277 | " ** optional : <leaky_en:0|1> <eg_tag:0~7> <usr_pri:0~7> <sa_mir_en:0|1> <sa_port_fw:0~7>\n" |
| 278 | |
| 279 | #define HELP_ARL_DIP_TBL_ADD "arl diptbl-add <DIP> <DestPortMap> <leaky_en:0|1> <eg_tag:0~7> <usr_pri:0~7> <status:0~3>\n" |
| 280 | |
| 281 | #define HELP_ARL_SIP_TBL_ADD "arl siptbl-add <DIP> <SIP> <DestPortMap> <status:0~3>\n" |
| 282 | |
| 283 | #define HELP_ACL_SETPORTEN "acl enable <port> <port_enable:0|1>\n" |
| 284 | #define HELP_ACL_ACL_TBL_ADD "arl acltbl-add <tbl_idx:0~63/255> <vawd1> <vawd2>\n" |
| 285 | #define HELP_ACL_MASK_TBL_ADD "arl masktbl-add <tbl_idx:0~31/127> <vawd1> <vawd2>\n" |
| 286 | #define HELP_ACL_RULE_TBL_ADD "arl ruletbl-add <tbl_idx:0~31/127> <vawd1> <vawd2>\n" |
| 287 | #define HELP_ACL_RATE_TBL_ADD "arl ratetbl-add <tbl_idx:0~31> <vawd1> <vawd2>\n" |
| 288 | #define HELP_ACL_TRTCM_TBL_ADD "arl trTCMtbl-add <tbl_idx:0~31> <vawd1> <vawd2>\n" |
| 289 | |
| 290 | |
| 291 | #define HELP_VLAN_PORT_MODE "vlan port-mode <port> <mode:0~3>\n" \ |
| 292 | "<mode>: 0: port matrix mode\n" \ |
| 293 | " 1: fallback mode\n" \ |
| 294 | " 2: check mode\n" \ |
| 295 | " 3: security mode\n"\ |
| 296 | |
| 297 | #define HELP_VLAN_PORT_ATTR "vlan port-attr <port> <attr:0~3>\n" \ |
| 298 | "<attr>: 0: user port\n" \ |
| 299 | " 1: statck port\n" \ |
| 300 | " 2: translation port\n" \ |
| 301 | " 3: transparent port\n" |
| 302 | |
| 303 | #define HELP_VLAN_EGRESS_TAG_PVC "vlan eg-tag-pvc <port> <eg_tag:0~7>\n" \ |
| 304 | "<eg_tag>: 0: disable\n" \ |
| 305 | " 1: consistent\n" \ |
| 306 | " 2: reserved\n" \ |
| 307 | " 3: reserved\n" \ |
| 308 | " 4: untagged\n" \ |
| 309 | " 5: swap\n" \ |
| 310 | " 6: tagged\n" \ |
| 311 | " 7: stack\n" |
| 312 | |
| 313 | #define HELP_VLAN_EGRESS_TAG_PCR "vlan eg-tag-pcr <port> <eg_tag:0~3>\n" \ |
| 314 | "<eg_tag>: 0: untagged\n" \ |
| 315 | " 1: swap\n" \ |
| 316 | " 2: tagged\n" \ |
| 317 | " 3: stack\n" |
| 318 | |
| 319 | #define HELP_VLAN_ACC_FRM "vlan acc-frm <port> <acceptable_frame_type:0~3>\n" \ |
| 320 | "<type>: 0: admit all frames\n" \ |
| 321 | " 1: admit only vlan-taged frames\n" \ |
| 322 | " 2: admit only untagged or priority-tagged frames\n" \ |
| 323 | " 3: reserved\n" |
| 324 | |
| 325 | |
| 326 | #define HELP_SWITCH_RESET "switch software reset\n" |
| 327 | #define HELP_MACCTL_FC "macctl fc <enable:0|1>\n" |
| 328 | #define HELP_MIRROR_EN "mirror enable <mirror_en:0|1> <mirror_port: 0-6>\n" |
| 329 | #define HELP_MIRROR_PORTBASED "mirror port-based <port> <port_tx_mir:0|1> <port_rx_mir:0|1> <acl_mir:0|1> <vlan_mis:0|1> <igmp_mir:0|1>\n" |
| 330 | |
| 331 | #define HELP_PHY_AN_EN "phyctl an <port> <auto_negotiation_en:0|1>\n" |
| 332 | #define HELP_PHY_FC_EN "phyctl fc <port> <full_duplex_pause_capable:0|1>\n" |
| 333 | |
| 334 | #define HELP_STP "stp <port> <fid> <state>\n" \ |
| 335 | "<state>: 0: Disable/Discarding\n" \ |
| 336 | " 1: Blocking/Listening/Discarding\n" \ |
| 337 | " 2: Learning\n" \ |
| 338 | " 3: Forwarding\n" |
| developer | cc8110b | 2024-08-19 13:53:34 +0800 | [diff] [blame] | 339 | #define HELP_COLLISION_POOL_EN "collision-pool enable [enable 0|1]\n" |
| 340 | #define HELP_EEE_EN "eee [enable|disable] ([port|portMap])\n" |
| developer | 880c829 | 2022-07-11 11:52:59 +0800 | [diff] [blame] | 341 | |
| 342 | //#endif //SQA_VERIFY |