developer | 43a264f | 2024-03-26 14:09:54 +0800 | [diff] [blame^] | 1 | From bd6543b475fd9b98c45a486d242c6915a846aef2 Mon Sep 17 00:00:00 2001 |
| 2 | From: Henry Yen <henry.yen@mediatek.com> |
| 3 | Date: Wed, 6 Mar 2024 12:42:06 +0800 |
| 4 | Subject: [PATCH 1050/1051] wifi: mt76: mt7915: remove unnecessary register |
| 5 | settings |
| 6 | |
| 7 | Remove unnecessary register settings from the driver layer, |
| 8 | and let firmware take over the configuration control. |
| 9 | |
| 10 | Signed-off-by: Henry.Yen <henry.yen@mediatek.com> |
| 11 | --- |
| 12 | mt7915/init.c | 35 ----------------------------------- |
| 13 | mt7915/mac.c | 43 +------------------------------------------ |
| 14 | 2 files changed, 1 insertion(+), 77 deletions(-) |
| 15 | |
| 16 | diff --git a/mt7915/init.c b/mt7915/init.c |
| 17 | index f5daf024..b299eccc 100644 |
| 18 | --- a/mt7915/init.c |
| 19 | +++ b/mt7915/init.c |
| 20 | @@ -488,30 +488,6 @@ mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) |
| 21 | { |
| 22 | u32 mask, set; |
| 23 | |
| 24 | - mt76_rmw_field(dev, MT_TMAC_CTCR0(band), |
| 25 | - MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); |
| 26 | - mt76_set(dev, MT_TMAC_CTCR0(band), |
| 27 | - MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | |
| 28 | - MT_TMAC_CTCR0_INS_DDLMT_EN); |
| 29 | - |
| 30 | - mask = MT_MDP_RCFR0_MCU_RX_MGMT | |
| 31 | - MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | |
| 32 | - MT_MDP_RCFR0_MCU_RX_CTL_BAR; |
| 33 | - set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | |
| 34 | - FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | |
| 35 | - FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); |
| 36 | - mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); |
| 37 | - |
| 38 | - mask = MT_MDP_RCFR1_MCU_RX_BYPASS | |
| 39 | - MT_MDP_RCFR1_RX_DROPPED_UCAST | |
| 40 | - MT_MDP_RCFR1_RX_DROPPED_MCAST; |
| 41 | - set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | |
| 42 | - FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | |
| 43 | - FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); |
| 44 | - mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); |
| 45 | - |
| 46 | - mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); |
| 47 | - |
| 48 | /* mt7915: disable rx rate report by default due to hw issues */ |
| 49 | mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); |
| 50 | |
| 51 | @@ -614,23 +590,12 @@ mt7915_init_led_mux(struct mt7915_dev *dev) |
| 52 | void mt7915_mac_init(struct mt7915_dev *dev) |
| 53 | { |
| 54 | int i; |
| 55 | - u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; |
| 56 | - |
| 57 | - /* config pse qid6 wfdma port selection */ |
| 58 | - if (!is_mt7915(&dev->mt76) && dev->hif2) |
| 59 | - mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, |
| 60 | - MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); |
| 61 | - |
| 62 | - mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); |
| 63 | |
| 64 | if (!is_mt7915(&dev->mt76)) |
| 65 | mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); |
| 66 | else |
| 67 | mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY); |
| 68 | |
| 69 | - /* enable hardware de-agg */ |
| 70 | - mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); |
| 71 | - |
| 72 | for (i = 0; i < mt7915_wtbl_size(dev); i++) |
| 73 | mt7915_mac_wtbl_update(dev, i, |
| 74 | MT_WTBL_UPDATE_ADM_COUNT_CLEAR); |
| 75 | diff --git a/mt7915/mac.c b/mt7915/mac.c |
| 76 | index e9f50a38..c84b9573 100644 |
| 77 | --- a/mt7915/mac.c |
| 78 | +++ b/mt7915/mac.c |
| 79 | @@ -1202,61 +1202,20 @@ void mt7915_mac_reset_counters(struct mt7915_phy *phy) |
| 80 | |
| 81 | void mt7915_mac_set_timing(struct mt7915_phy *phy) |
| 82 | { |
| 83 | - s16 coverage_class = phy->coverage_class; |
| 84 | struct mt7915_dev *dev = phy->dev; |
| 85 | - struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); |
| 86 | - u32 val, reg_offset; |
| 87 | - u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | |
| 88 | - FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); |
| 89 | - u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | |
| 90 | - FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); |
| 91 | + u32 val; |
| 92 | u8 band = phy->mt76->band_idx; |
| 93 | - int eifs_ofdm = 360, sifs = 10, offset; |
| 94 | bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); |
| 95 | |
| 96 | if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) |
| 97 | return; |
| 98 | |
| 99 | - if (ext_phy) |
| 100 | - coverage_class = max_t(s16, dev->phy.coverage_class, |
| 101 | - ext_phy->coverage_class); |
| 102 | - |
| 103 | - mt76_set(dev, MT_ARB_SCR(band), |
| 104 | - MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); |
| 105 | - udelay(1); |
| 106 | - |
| 107 | - offset = 3 * coverage_class; |
| 108 | - reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | |
| 109 | - FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); |
| 110 | - |
| 111 | - if (!is_mt7915(&dev->mt76)) { |
| 112 | - if (!a_band) { |
| 113 | - mt76_wr(dev, MT_TMAC_ICR1(band), |
| 114 | - FIELD_PREP(MT_IFS_EIFS_CCK, 314)); |
| 115 | - eifs_ofdm = 78; |
| 116 | - } else { |
| 117 | - eifs_ofdm = 84; |
| 118 | - } |
| 119 | - } else if (a_band) { |
| 120 | - sifs = 16; |
| 121 | - } |
| 122 | - |
| 123 | - mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); |
| 124 | - mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); |
| 125 | - mt76_wr(dev, MT_TMAC_ICR0(band), |
| 126 | - FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | |
| 127 | - FIELD_PREP(MT_IFS_RIFS, 2) | |
| 128 | - FIELD_PREP(MT_IFS_SIFS, sifs) | |
| 129 | - FIELD_PREP(MT_IFS_SLOT, phy->slottime)); |
| 130 | - |
| 131 | if (phy->slottime < 20 || a_band) |
| 132 | val = MT7915_CFEND_RATE_DEFAULT; |
| 133 | else |
| 134 | val = MT7915_CFEND_RATE_11B; |
| 135 | |
| 136 | mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); |
| 137 | - mt76_clear(dev, MT_ARB_SCR(band), |
| 138 | - MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); |
| 139 | } |
| 140 | |
| 141 | void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) |
| 142 | -- |
| 143 | 2.18.0 |
| 144 | |