developer | 5dfa8b7 | 2022-11-03 11:33:07 +0800 | [diff] [blame] | 1 | /* |
| 2 | * switch_netlink.h: switch(netlink) set API |
| 3 | * |
| 4 | * Author: Sirui Zhao <Sirui.Zhao@mediatek.com> |
| 5 | */ |
| 6 | #ifndef MT753X_NETLINK_H |
| 7 | #define MT753X_NETLINK_H |
| 8 | |
| 9 | #define MT753X_GENL_NAME "mt753x" |
| 10 | #define MT753X_DSA_GENL_NAME "mt753x_dsa" |
| 11 | #define MT753X_GENL_VERSION 0X1 |
developer | e78dab5 | 2024-03-25 14:26:39 +0800 | [diff] [blame] | 12 | #define AN8855_GENL_NAME "an8855" |
| 13 | #define AN8855_DSA_GENL_NAME "an8855_dsa" |
developer | 5dfa8b7 | 2022-11-03 11:33:07 +0800 | [diff] [blame] | 14 | |
| 15 | /*add your cmd to here*/ |
| 16 | enum { |
developer | e78dab5 | 2024-03-25 14:26:39 +0800 | [diff] [blame] | 17 | MT753X_CMD_UNSPEC = 0, /*Reserved */ |
| 18 | MT753X_CMD_REQUEST, /*user->kernelrequest/get-response */ |
| 19 | MT753X_CMD_REPLY, /*kernel->user event */ |
developer | 5dfa8b7 | 2022-11-03 11:33:07 +0800 | [diff] [blame] | 20 | MT753X_CMD_READ, |
| 21 | MT753X_CMD_WRITE, |
| 22 | __MT753X_CMD_MAX, |
| 23 | }; |
| 24 | #define MT753X_CMD_MAX (__MT753X_CMD_MAX - 1) |
| 25 | |
| 26 | /*define attar types */ |
developer | e78dab5 | 2024-03-25 14:26:39 +0800 | [diff] [blame] | 27 | enum { |
developer | 5dfa8b7 | 2022-11-03 11:33:07 +0800 | [diff] [blame] | 28 | MT753X_ATTR_TYPE_UNSPEC = 0, |
developer | e78dab5 | 2024-03-25 14:26:39 +0800 | [diff] [blame] | 29 | MT753X_ATTR_TYPE_MESG, /*MT753X message */ |
developer | 5dfa8b7 | 2022-11-03 11:33:07 +0800 | [diff] [blame] | 30 | MT753X_ATTR_TYPE_PHY, |
| 31 | MT753X_ATTR_TYPE_PHY_DEV, |
| 32 | MT753X_ATTR_TYPE_REG, |
| 33 | MT753X_ATTR_TYPE_VAL, |
| 34 | MT753X_ATTR_TYPE_DEV_NAME, |
| 35 | MT753X_ATTR_TYPE_DEV_ID, |
| 36 | __MT753X_ATTR_TYPE_MAX, |
| 37 | }; |
| 38 | #define MT753X_ATTR_TYPE_MAX (__MT753X_ATTR_TYPE_MAX - 1) |
| 39 | |
| 40 | struct mt753x_attr { |
| 41 | int port_num; |
| 42 | int phy_dev; |
| 43 | int reg; |
| 44 | int value; |
| 45 | int type; |
| 46 | char op; |
| 47 | char *dev_info; |
| 48 | int dev_name; |
| 49 | int dev_id; |
| 50 | }; |
| 51 | |
developer | e78dab5 | 2024-03-25 14:26:39 +0800 | [diff] [blame] | 52 | extern int chip_name; |
| 53 | |
developer | 5dfa8b7 | 2022-11-03 11:33:07 +0800 | [diff] [blame] | 54 | int mt753x_netlink_init(const char *name); |
| 55 | void mt753x_netlink_free(void); |
| 56 | void mt753x_list_swdev(struct mt753x_attr *arg, int cmd); |
| 57 | int reg_read_netlink(struct mt753x_attr *arg, unsigned int offset, |
| 58 | unsigned int *value); |
| 59 | int reg_write_netlink(struct mt753x_attr *arg, unsigned int offset, |
| 60 | unsigned int value); |
| 61 | int phy_cl22_read_netlink(struct mt753x_attr *arg, unsigned int port_num, |
| 62 | unsigned int phy_addr, unsigned int *value); |
| 63 | int phy_cl22_write_netlink(struct mt753x_attr *arg, unsigned int port_num, |
| 64 | unsigned int phy_addr, unsigned int value); |
| 65 | int phy_cl45_read_netlink(struct mt753x_attr *arg, unsigned int port_num, |
| 66 | unsigned int phy_dev, unsigned int phy_addr, |
| 67 | unsigned int *value); |
| 68 | int phy_cl45_write_netlink(struct mt753x_attr *arg, unsigned int port_num, |
| 69 | unsigned int phy_dev, unsigned int phy_addr, |
| 70 | unsigned int value); |
| 71 | int phy_dump_netlink(struct mt753x_attr *arg, int phy_addr); |
| 72 | |
| 73 | #endif |