| developer | 05f3b2b | 2024-08-19 19:17:34 +0800 | [diff] [blame] | 1 | From 1d799d5548538dcf501f7fb99b1f529ef001b4c8 Mon Sep 17 00:00:00 2001 |
| 2 | From: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 3 | Date: Fri, 26 Jul 2024 09:27:45 +0800 |
| 4 | Subject: [PATCH 009/199] mtk: mt76: mt7996: fix rxd checksum offload offset |
| 5 | |
| 6 | Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 7 | --- |
| 8 | mt76_connac3_mac.h | 4 ++-- |
| 9 | mt7996/mac.c | 4 ++-- |
| 10 | 2 files changed, 4 insertions(+), 4 deletions(-) |
| 11 | |
| 12 | diff --git a/mt76_connac3_mac.h b/mt76_connac3_mac.h |
| 13 | index 3fc94bd7..db0c29e6 100644 |
| 14 | --- a/mt76_connac3_mac.h |
| 15 | +++ b/mt76_connac3_mac.h |
| 16 | @@ -28,8 +28,6 @@ enum { |
| 17 | #define MT_RXD0_MESH BIT(18) |
| 18 | #define MT_RXD0_MHCP BIT(19) |
| 19 | #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16) |
| 20 | -#define MT_RXD0_NORMAL_IP_SUM BIT(23) |
| 21 | -#define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) |
| 22 | |
| 23 | #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16) |
| 24 | #define MT_RXD0_SW_PKT_TYPE_MAP 0x380F |
| 25 | @@ -80,6 +78,8 @@ enum { |
| 26 | #define MT_RXD3_NORMAL_BEACON_UC BIT(21) |
| 27 | #define MT_RXD3_NORMAL_CO_ANT BIT(22) |
| 28 | #define MT_RXD3_NORMAL_FCS_ERR BIT(24) |
| 29 | +#define MT_RXD3_NORMAL_IP_SUM BIT(26) |
| 30 | +#define MT_RXD3_NORMAL_UDP_TCP_SUM BIT(27) |
| 31 | #define MT_RXD3_NORMAL_VLAN2ETH BIT(31) |
| 32 | |
| 33 | /* RXD DW4 */ |
| 34 | diff --git a/mt7996/mac.c b/mt7996/mac.c |
| 35 | index b3f9591f..109a74a9 100644 |
| 36 | --- a/mt7996/mac.c |
| 37 | +++ b/mt7996/mac.c |
| 38 | @@ -435,7 +435,7 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q, |
| 39 | u32 rxd2 = le32_to_cpu(rxd[2]); |
| 40 | u32 rxd3 = le32_to_cpu(rxd[3]); |
| 41 | u32 rxd4 = le32_to_cpu(rxd[4]); |
| 42 | - u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; |
| 43 | + u32 csum_mask = MT_RXD3_NORMAL_IP_SUM | MT_RXD3_NORMAL_UDP_TCP_SUM; |
| 44 | u32 csum_status = *(u32 *)skb->cb; |
| 45 | u32 mesh_mask = MT_RXD0_MESH | MT_RXD0_MHCP; |
| 46 | bool is_mesh = (rxd0 & mesh_mask) == mesh_mask; |
| 47 | @@ -497,7 +497,7 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q, |
| 48 | if (!sband->channels) |
| 49 | return -EINVAL; |
| 50 | |
| 51 | - if ((rxd0 & csum_mask) == csum_mask && |
| 52 | + if ((rxd3 & csum_mask) == csum_mask && |
| 53 | !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) |
| 54 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 55 | |
| 56 | -- |
| 57 | 2.18.0 |
| 58 | |