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developer05f3b2b2024-08-19 19:17:34 +08001From 184f146afaddb73c3fd0afc60338f5ed73d5b450 Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +08002From: Howard Hsu <howard-yh.hsu@mediatek.com>
3Date: Tue, 12 Mar 2024 09:07:52 +0800
developer05f3b2b2024-08-19 19:17:34 +08004Subject: [PATCH 004/199] mtk: mt76: mt7996: fix HE and EHT phy cap
developer66e89bc2024-04-23 14:50:01 +08005
developer66e89bc2024-04-23 14:50:01 +08006---
7 mt7996/init.c | 65 ++++++++++++++++++++++++++++++++++-----------------
8 1 file changed, 43 insertions(+), 22 deletions(-)
9
10diff --git a/mt7996/init.c b/mt7996/init.c
developer05f3b2b2024-08-19 19:17:34 +080011index 283df84f..a98dcb40 100644
developer66e89bc2024-04-23 14:50:01 +080012--- a/mt7996/init.c
13+++ b/mt7996/init.c
developer05f3b2b2024-08-19 19:17:34 +080014@@ -1011,8 +1011,6 @@ mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
developer66e89bc2024-04-23 14:50:01 +080015 return;
16
17 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
18- if (vif == NL80211_IFTYPE_AP)
19- elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
20
21 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
22 sts - 1) |
developer05f3b2b2024-08-19 19:17:34 +080023@@ -1020,6 +1018,11 @@ mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
developer66e89bc2024-04-23 14:50:01 +080024 sts - 1);
25 elem->phy_cap_info[5] |= c;
26
27+ if (vif != NL80211_IFTYPE_AP)
28+ return;
29+
30+ elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
31+
32 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
33 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
34 elem->phy_cap_info[6] |= c;
developer05f3b2b2024-08-19 19:17:34 +080035@@ -1179,7 +1182,6 @@ mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
developer66e89bc2024-04-23 14:50:01 +080036 IEEE80211_EHT_MAC_CAP0_OM_CONTROL;
37
38 eht_cap_elem->phy_cap_info[0] =
39- IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ |
40 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
41 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER |
42 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
developer05f3b2b2024-08-19 19:17:34 +080043@@ -1193,30 +1195,36 @@ mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
developer66e89bc2024-04-23 14:50:01 +080044 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)),
45 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
46 u8_encode_bits(val,
47- IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK) |
48- u8_encode_bits(val,
49- IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
50+ IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
51
52 eht_cap_elem->phy_cap_info[2] =
53 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK) |
54- u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK) |
55- u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK);
56+ u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK);
57+
58+ if (band == NL80211_BAND_6GHZ) {
59+ eht_cap_elem->phy_cap_info[0] |=
60+ IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
61+
62+ eht_cap_elem->phy_cap_info[1] |=
63+ u8_encode_bits(val,
64+ IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
65+
66+ eht_cap_elem->phy_cap_info[2] |=
67+ u8_encode_bits(sts - 1,
68+ IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK);
69+ }
70
71 eht_cap_elem->phy_cap_info[3] =
72 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
73 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
74 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
75- IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
76- IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
77- IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
78- IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK;
79+ IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK;
80
81 eht_cap_elem->phy_cap_info[4] =
82 u8_encode_bits(min_t(int, sts - 1, 2),
83 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
84
85 eht_cap_elem->phy_cap_info[5] =
86- IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK |
87 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US,
88 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) |
89 u8_encode_bits(u8_get_bits(0x11, GENMASK(1, 0)),
developer05f3b2b2024-08-19 19:17:34 +080090@@ -1230,14 +1238,6 @@ mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
developer66e89bc2024-04-23 14:50:01 +080091 IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK) |
92 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK);
93
94- eht_cap_elem->phy_cap_info[7] =
95- IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ |
96- IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ |
97- IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ |
98- IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ |
99- IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ |
100- IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ;
101-
102 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) |
103 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX);
104 #define SET_EHT_MAX_NSS(_bw, _val) do { \
developer05f3b2b2024-08-19 19:17:34 +0800105@@ -1248,8 +1248,29 @@ mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
developer66e89bc2024-04-23 14:50:01 +0800106
107 SET_EHT_MAX_NSS(80, val);
108 SET_EHT_MAX_NSS(160, val);
109- SET_EHT_MAX_NSS(320, val);
110+ if (band == NL80211_BAND_6GHZ)
111+ SET_EHT_MAX_NSS(320, val);
112 #undef SET_EHT_MAX_NSS
113+
114+ if (iftype != NL80211_IFTYPE_AP)
115+ return;
116+
117+ eht_cap_elem->phy_cap_info[3] |=
118+ IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
119+ IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
120+
121+ eht_cap_elem->phy_cap_info[7] =
122+ IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ |
123+ IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ |
124+ IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ |
125+ IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ;
126+
127+ if (band != NL80211_BAND_6GHZ)
128+ return;
129+
130+ eht_cap_elem->phy_cap_info[7] |=
131+ IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ |
132+ IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ;
133 }
134
135 static void
136--
developer9237f442024-06-14 17:13:04 +08001372.18.0
developer66e89bc2024-04-23 14:50:01 +0800138