developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame^] | 1 | From 567a6f7be24a7f87d550f1cf3e1f1796e1770b2a Mon Sep 17 00:00:00 2001 |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 2 | From: Shayne Chen <shayne.chen@mediatek.com> |
developer | 42b6328 | 2022-06-16 13:33:13 +0800 | [diff] [blame] | 3 | Date: Mon, 6 Jun 2022 19:46:26 +0800 |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 4 | Subject: [PATCH 1/3] mt76: mt7915: rework testmode init registers |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 5 | |
| 6 | --- |
| 7 | mt7915/mmio.c | 2 ++ |
| 8 | mt7915/regs.h | 16 +++++++++++++-- |
| 9 | mt7915/testmode.c | 52 ++++++++++++++++++++++++++++++++++------------- |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 10 | testmode.c | 3 +-- |
| 11 | 4 files changed, 55 insertions(+), 18 deletions(-) |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 12 | |
| 13 | diff --git a/mt7915/mmio.c b/mt7915/mmio.c |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame^] | 14 | index be1b8ea7..9c2c5086 100644 |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 15 | --- a/mt7915/mmio.c |
| 16 | +++ b/mt7915/mmio.c |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 17 | @@ -68,6 +68,7 @@ static const u32 mt7986_reg[] = { |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 18 | }; |
| 19 | |
| 20 | static const u32 mt7915_offs[] = { |
| 21 | + [TMAC_TCR2] = 0x05c, |
| 22 | [TMAC_CDTR] = 0x090, |
| 23 | [TMAC_ODTR] = 0x094, |
| 24 | [TMAC_ATCR] = 0x098, |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 25 | @@ -142,6 +143,7 @@ static const u32 mt7915_offs[] = { |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 26 | }; |
| 27 | |
| 28 | static const u32 mt7916_offs[] = { |
| 29 | + [TMAC_TCR2] = 0x004, |
| 30 | [TMAC_CDTR] = 0x0c8, |
| 31 | [TMAC_ODTR] = 0x0cc, |
| 32 | [TMAC_ATCR] = 0x00c, |
| 33 | diff --git a/mt7915/regs.h b/mt7915/regs.h |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame^] | 34 | index 5180dd93..2e445373 100644 |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 35 | --- a/mt7915/regs.h |
| 36 | +++ b/mt7915/regs.h |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 37 | @@ -32,6 +32,7 @@ enum reg_rev { |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 38 | }; |
| 39 | |
| 40 | enum offs_rev { |
| 41 | + TMAC_TCR2, |
| 42 | TMAC_CDTR, |
| 43 | TMAC_ODTR, |
| 44 | TMAC_ATCR, |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 45 | @@ -182,6 +183,12 @@ enum offs_rev { |
developer | 42b6328 | 2022-06-16 13:33:13 +0800 | [diff] [blame] | 46 | #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16) |
| 47 | #define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0) |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 48 | |
| 49 | +#define MT_MDP_TOP_DBG_WDT_CTRL MT_MDP(0x0d0) |
| 50 | +#define MT_MDP_TOP_DBG_WDT_CTRL_TDP_DIS_BLK BIT(7) |
| 51 | + |
| 52 | +#define MT_MDP_TOP_DBG_CTRL MT_MDP(0x0dc) |
| 53 | +#define MT_MDP_TOP_DBG_CTRL_ENQ_MODE BIT(30) |
| 54 | + |
| 55 | /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */ |
| 56 | #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) |
| 57 | #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 58 | @@ -190,6 +197,9 @@ enum offs_rev { |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 59 | #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) |
| 60 | #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) |
| 61 | |
| 62 | +#define MT_TMAC_TCR2(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TCR2)) |
| 63 | +#define MT_TMAC_TCR2_SCH_DET_DIS BIT(19) |
| 64 | + |
| 65 | #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR)) |
| 66 | #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR)) |
| 67 | #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 68 | @@ -461,8 +471,10 @@ enum offs_rev { |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 69 | #define MT_AGG_PCR0_VHT_PROT BIT(13) |
| 70 | #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) |
| 71 | |
| 72 | -#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) |
| 73 | -#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) |
| 74 | +#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) |
| 75 | +#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) |
| 76 | +#define MT_AGG_PCR1_RTS0_NUM_THRES_MT7916 GENMASK(29, 24) |
| 77 | +#define MT_AGG_PCR1_RTS0_LEN_THRES_MT7916 GENMASK(22, 0) |
| 78 | |
| 79 | #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0)) |
| 80 | #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) |
| 81 | diff --git a/mt7915/testmode.c b/mt7915/testmode.c |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame^] | 82 | index a979460f..819fafe4 100644 |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 83 | --- a/mt7915/testmode.c |
| 84 | +++ b/mt7915/testmode.c |
| 85 | @@ -30,7 +30,7 @@ struct reg_band { |
| 86 | { _list.band[0] = MT_##_reg(0, _idx); \ |
| 87 | _list.band[1] = MT_##_reg(1, _idx); } |
| 88 | |
| 89 | -#define TM_REG_MAX_ID 17 |
| 90 | +#define TM_REG_MAX_ID 20 |
| 91 | static struct reg_band reg_backup_list[TM_REG_MAX_ID]; |
| 92 | |
| 93 | |
developer | aace7f5 | 2022-06-24 13:40:42 +0800 | [diff] [blame] | 94 | @@ -335,7 +335,7 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy) |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 95 | { |
| 96 | int n_regs = ARRAY_SIZE(reg_backup_list); |
| 97 | struct mt7915_dev *dev = phy->dev; |
| 98 | - u32 *b = phy->test.reg_backup; |
| 99 | + u32 *b = phy->test.reg_backup, val; |
| 100 | int i; |
| 101 | |
| 102 | REG_BAND_IDX(reg_backup_list[0], AGG_PCR0, 0); |
developer | aace7f5 | 2022-06-24 13:40:42 +0800 | [diff] [blame] | 103 | @@ -347,18 +347,28 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy) |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 104 | REG_BAND(reg_backup_list[6], AGG_MRCR); |
| 105 | REG_BAND(reg_backup_list[7], TMAC_TFCR0); |
| 106 | REG_BAND(reg_backup_list[8], TMAC_TCR0); |
| 107 | - REG_BAND(reg_backup_list[9], AGG_ATCR1); |
| 108 | - REG_BAND(reg_backup_list[10], AGG_ATCR3); |
| 109 | - REG_BAND(reg_backup_list[11], TMAC_TRCR0); |
| 110 | - REG_BAND(reg_backup_list[12], TMAC_ICR0); |
| 111 | - REG_BAND_IDX(reg_backup_list[13], ARB_DRNGR0, 0); |
| 112 | - REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 1); |
| 113 | - REG_BAND(reg_backup_list[15], WF_RFCR); |
| 114 | - REG_BAND(reg_backup_list[16], WF_RFCR1); |
| 115 | + REG_BAND(reg_backup_list[9], TMAC_TCR2); |
| 116 | + REG_BAND(reg_backup_list[10], AGG_ATCR1); |
| 117 | + REG_BAND(reg_backup_list[11], AGG_ATCR3); |
| 118 | + REG_BAND(reg_backup_list[12], TMAC_TRCR0); |
| 119 | + REG_BAND(reg_backup_list[13], TMAC_ICR0); |
| 120 | + REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 0); |
| 121 | + REG_BAND_IDX(reg_backup_list[15], ARB_DRNGR0, 1); |
| 122 | + REG_BAND(reg_backup_list[16], WF_RFCR); |
| 123 | + REG_BAND(reg_backup_list[17], WF_RFCR1); |
| 124 | + |
| 125 | + if (is_mt7916(&dev->mt76)) { |
| 126 | + reg_backup_list[18].band[phy->band_idx] = MT_MDP_TOP_DBG_WDT_CTRL; |
| 127 | + reg_backup_list[19].band[phy->band_idx] = MT_MDP_TOP_DBG_CTRL; |
| 128 | + } |
| 129 | |
| 130 | if (phy->mt76->test.state == MT76_TM_STATE_OFF) { |
| 131 | - for (i = 0; i < n_regs; i++) |
| 132 | - mt76_wr(dev, reg_backup_list[i].band[phy->band_idx], b[i]); |
| 133 | + for (i = 0; i < n_regs; i++) { |
| 134 | + u8 reg = reg_backup_list[i].band[phy->band_idx]; |
| 135 | + |
| 136 | + if (reg) |
| 137 | + mt76_wr(dev, reg, b[i]); |
| 138 | + } |
| 139 | return; |
| 140 | } |
| 141 | |
developer | aace7f5 | 2022-06-24 13:40:42 +0800 | [diff] [blame] | 142 | @@ -378,8 +388,13 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy) |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 143 | MT_AGG_PCR0_BW40_PROT | MT_AGG_PCR0_BW80_PROT); |
| 144 | mt76_set(dev, MT_AGG_PCR0(phy->band_idx, 0), MT_AGG_PCR0_PTA_WIN_DIS); |
| 145 | |
| 146 | - mt76_wr(dev, MT_AGG_PCR0(phy->band_idx, 1), MT_AGG_PCR1_RTS0_NUM_THRES | |
| 147 | - MT_AGG_PCR1_RTS0_LEN_THRES); |
| 148 | + if (is_mt7915(&dev->mt76)) |
| 149 | + val = MT_AGG_PCR1_RTS0_NUM_THRES | MT_AGG_PCR1_RTS0_LEN_THRES; |
| 150 | + else |
| 151 | + val = MT_AGG_PCR1_RTS0_NUM_THRES_MT7916 | |
| 152 | + MT_AGG_PCR1_RTS0_LEN_THRES_MT7916; |
| 153 | + |
| 154 | + mt76_wr(dev, MT_AGG_PCR0(phy->band_idx, 1), val); |
| 155 | |
| 156 | mt76_clear(dev, MT_AGG_MRCR(phy->band_idx), MT_AGG_MRCR_BAR_CNT_LIMIT | |
| 157 | MT_AGG_MRCR_LAST_RTS_CTS_RN | MT_AGG_MRCR_RTS_FAIL_LIMIT | |
developer | aace7f5 | 2022-06-24 13:40:42 +0800 | [diff] [blame] | 158 | @@ -392,10 +407,19 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy) |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 159 | |
| 160 | mt76_wr(dev, MT_TMAC_TFCR0(phy->band_idx), 0); |
| 161 | mt76_clear(dev, MT_TMAC_TCR0(phy->band_idx), MT_TMAC_TCR0_TBTT_STOP_CTRL); |
| 162 | + mt76_set(dev, MT_TMAC_TCR2(phy->band_idx), MT_TMAC_TCR2_SCH_DET_DIS); |
| 163 | |
| 164 | /* config rx filter for testmode rx */ |
| 165 | mt76_wr(dev, MT_WF_RFCR(phy->band_idx), 0xcf70a); |
| 166 | mt76_wr(dev, MT_WF_RFCR1(phy->band_idx), 0); |
| 167 | + |
| 168 | + if (is_mt7916(&dev->mt76)) { |
| 169 | + /* enable MDP Tx block mode */ |
| 170 | + mt76_clear(dev, MT_MDP_TOP_DBG_WDT_CTRL, |
| 171 | + MT_MDP_TOP_DBG_WDT_CTRL_TDP_DIS_BLK); |
| 172 | + mt76_clear(dev, MT_MDP_TOP_DBG_CTRL, |
| 173 | + MT_MDP_TOP_DBG_CTRL_ENQ_MODE); |
| 174 | + } |
| 175 | } |
| 176 | |
| 177 | static void |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 178 | diff --git a/testmode.c b/testmode.c |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame^] | 179 | index 0accc71a..57cdfdf6 100644 |
developer | f131310 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 180 | --- a/testmode.c |
| 181 | +++ b/testmode.c |
| 182 | @@ -447,8 +447,7 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 183 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_LDPC], &td->tx_rate_ldpc, 0, 1) || |
| 184 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_STBC], &td->tx_rate_stbc, 0, 1) || |
| 185 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_LTF], &td->tx_ltf, 0, 2) || |
| 186 | - mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_ANTENNA], |
| 187 | - &td->tx_antenna_mask, 0, 0xff) || |
| 188 | + mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_ANTENNA], &td->tx_antenna_mask, 1, 0xff) || |
| 189 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_SPE_IDX], &td->tx_spe_idx, 0, 27) || |
| 190 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_DUTY_CYCLE], |
| 191 | &td->tx_duty_cycle, 0, 99) || |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 192 | -- |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame^] | 193 | 2.25.1 |
developer | ec4ebe4 | 2022-04-12 11:17:45 +0800 | [diff] [blame] | 194 | |