blob: e75b064d6511fa346c3a0e8f701f99f80490e452 [file] [log] [blame]
developerf1313102022-10-11 11:02:55 +08001From 66c81406b30b24a50be33f5434664191b7cf7ab0 Mon Sep 17 00:00:00 2001
developeraace7f52022-06-24 13:40:42 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Wed, 22 Jun 2022 10:39:47 +0800
developerf1313102022-10-11 11:02:55 +08004Subject: [PATCH 1001/1009] mt76: mt7915: add mtk internal debug tools for mt76
developer3fa816c2022-04-19 10:21:20 +08005
6---
developer9e5bcc52022-09-27 10:30:15 +08007 mt76_connac_mcu.h | 7 +
developer27b55252022-09-05 19:09:45 +08008 mt7915/Makefile | 2 +-
9 mt7915/debugfs.c | 73 +-
10 mt7915/mac.c | 14 +
11 mt7915/main.c | 4 +
developer9e5bcc52022-09-27 10:30:15 +080012 mt7915/mcu.c | 63 +
developer27b55252022-09-05 19:09:45 +080013 mt7915/mcu.h | 4 +
developer9e5bcc52022-09-27 10:30:15 +080014 mt7915/mt7915.h | 44 +
developer27b55252022-09-05 19:09:45 +080015 mt7915/mt7915_debug.h | 1350 +++++++++++++++++++
developer9e5bcc52022-09-27 10:30:15 +080016 mt7915/mtk_debugfs.c | 2925 +++++++++++++++++++++++++++++++++++++++++
developer27b55252022-09-05 19:09:45 +080017 mt7915/mtk_mcu.c | 51 +
18 tools/fwlog.c | 44 +-
developer9e5bcc52022-09-27 10:30:15 +080019 12 files changed, 4568 insertions(+), 13 deletions(-)
developer27b55252022-09-05 19:09:45 +080020 create mode 100644 mt7915/mt7915_debug.h
21 create mode 100644 mt7915/mtk_debugfs.c
22 create mode 100644 mt7915/mtk_mcu.c
developer3fa816c2022-04-19 10:21:20 +080023
24diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developerf1313102022-10-11 11:02:55 +080025index 3101721..06813f7 100644
developer3fa816c2022-04-19 10:21:20 +080026--- a/mt76_connac_mcu.h
27+++ b/mt76_connac_mcu.h
developer9e5bcc52022-09-27 10:30:15 +080028@@ -1104,6 +1104,7 @@ enum {
29 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
30 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
31 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
32+ MCU_EXT_CMD_MEC_CTRL = 0x1f,
33 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
34 MCU_EXT_CMD_THERMAL_PROT = 0x23,
35 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
36@@ -1127,6 +1128,12 @@ enum {
developer3fa816c2022-04-19 10:21:20 +080037 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
38 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
39 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
40+#ifdef MTK_DEBUG
41+ MCU_EXT_CMD_RED_ENABLE = 0x68,
42+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
43+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
44+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
45+#endif
46 MCU_EXT_CMD_TXDPD_CAL = 0x60,
47 MCU_EXT_CMD_CAL_CACHE = 0x67,
48 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
49diff --git a/mt7915/Makefile b/mt7915/Makefile
developerf1313102022-10-11 11:02:55 +080050index b794ceb..a3474e2 100644
developer3fa816c2022-04-19 10:21:20 +080051--- a/mt7915/Makefile
52+++ b/mt7915/Makefile
53@@ -3,7 +3,7 @@
54 obj-$(CONFIG_MT7915E) += mt7915e.o
55
56 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
57- debugfs.o mmio.o
58+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
59
60 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
61 mt7915e-$(CONFIG_MT7986_WMAC) += soc.o
62\ No newline at end of file
63diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
developerf1313102022-10-11 11:02:55 +080064index b95c81d..fd0c9d1 100644
developer3fa816c2022-04-19 10:21:20 +080065--- a/mt7915/debugfs.c
66+++ b/mt7915/debugfs.c
67@@ -8,6 +8,9 @@
68 #include "mac.h"
69
70 #define FW_BIN_LOG_MAGIC 0x44e98caf
71+#ifdef MTK_DEBUG
72+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
73+#endif
74
75 /** global debugfs **/
76
developerf32dabf2022-06-01 10:59:24 +080077@@ -448,6 +451,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080078 int ret;
79
developer42b63282022-06-16 13:33:13 +080080 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
developer3fa816c2022-04-19 10:21:20 +080081+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +080082+ dev->fw.debug_wm = val;
developer3fa816c2022-04-19 10:21:20 +080083+#endif
84
developer42b63282022-06-16 13:33:13 +080085 if (dev->fw.debug_bin)
developer3fa816c2022-04-19 10:21:20 +080086 val = 16;
developerf32dabf2022-06-01 10:59:24 +080087@@ -472,6 +478,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080088 if (ret)
developer42b63282022-06-16 13:33:13 +080089 goto out;
developer3fa816c2022-04-19 10:21:20 +080090 }
91+#ifdef MTK_DEBUG
92+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
93+#endif
94
95 /* WM CPU info record control */
96 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
developerf32dabf2022-06-01 10:59:24 +080097@@ -479,6 +488,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080098 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
99 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
100
101+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800102+ if (dev->fw.debug_bin & BIT(3))
developer3fa816c2022-04-19 10:21:20 +0800103+ /* use bit 7 to indicate v2 magic number */
developer42b63282022-06-16 13:33:13 +0800104+ dev->fw.debug_wm |= BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800105+#endif
106+
developer42b63282022-06-16 13:33:13 +0800107 out:
108 if (ret)
109 dev->fw.debug_wm = 0;
110@@ -491,7 +506,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
developer3fa816c2022-04-19 10:21:20 +0800111 {
112 struct mt7915_dev *dev = data;
113
developer42b63282022-06-16 13:33:13 +0800114- *val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800115+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800116+ *val = dev->fw.debug_wm & ~BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800117+#else
developer42b63282022-06-16 13:33:13 +0800118+ val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800119+#endif
120
121 return 0;
122 }
developer42b63282022-06-16 13:33:13 +0800123@@ -576,6 +595,17 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +0800124
125 relay_reset(dev->relay_fwlog);
126
127+#ifdef MTK_DEBUG
128+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
129+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
130+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
131+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
132+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
133+ if (!(val & GENMASK(3, 0)))
134+ return 0;
135+#endif
136+
developer42b63282022-06-16 13:33:13 +0800137+
138 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
developer3fa816c2022-04-19 10:21:20 +0800139 }
140
developer42b63282022-06-16 13:33:13 +0800141@@ -1038,6 +1068,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
developer3fa816c2022-04-19 10:21:20 +0800142 if (!ext_phy)
143 dev->debugfs_dir = dir;
144
145+#ifdef MTK_DEBUG
146+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
147+ mt7915_mtk_init_debugfs(phy, dir);
148+#endif
149+
150 return 0;
151 }
152
developer42b63282022-06-16 13:33:13 +0800153@@ -1078,17 +1113,53 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
developer3fa816c2022-04-19 10:21:20 +0800154 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
155 };
156
157+#ifdef MTK_DEBUG
158+ struct {
159+ __le32 magic;
160+ u8 version;
161+ u8 _rsv;
162+ __le16 serial_id;
163+ __le32 timestamp;
164+ __le16 msg_type;
165+ __le16 len;
166+ } hdr2 = {
167+ .version = 0x1,
168+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
169+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
170+ };
171+#endif
172+
173 if (!dev->relay_fwlog)
174 return;
175
176+#ifdef MTK_DEBUG
177+ /* old magic num */
developer42b63282022-06-16 13:33:13 +0800178+ if (!(dev->fw.debug_wm & BIT(7))) {
developer3fa816c2022-04-19 10:21:20 +0800179+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
180+ hdr.len = *(__le16 *)data;
181+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
182+ } else {
183+ hdr2.serial_id = dev->dbg.fwlog_seq++;
184+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
185+ hdr2.len = *(__le16 *)data;
186+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
187+ }
188+#else
189 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
190 hdr.len = *(__le16 *)data;
191 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
192+#endif
193 }
194
195 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
196 {
197+#ifdef MTK_DEBUG
198+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
199+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
200+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
201+#else
202 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
203+#endif
204 return false;
205
206 if (dev->relay_fwlog)
207diff --git a/mt7915/mac.c b/mt7915/mac.c
developerf1313102022-10-11 11:02:55 +0800208index 8ef5ddc..2ff90f7 100644
developer3fa816c2022-04-19 10:21:20 +0800209--- a/mt7915/mac.c
210+++ b/mt7915/mac.c
developeraace7f52022-06-24 13:40:42 +0800211@@ -239,6 +239,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
developer3fa816c2022-04-19 10:21:20 +0800212 __le16 fc = 0;
213 int idx;
214
215+#ifdef MTK_DEBUG
216+ if (dev->dbg.dump_rx_raw)
217+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
218+#endif
219 memset(status, 0, sizeof(*status));
220
221 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->band_idx) {
developeraace7f52022-06-24 13:40:42 +0800222@@ -421,6 +425,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
developer3fa816c2022-04-19 10:21:20 +0800223 }
224
225 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
226+#ifdef MTK_DEBUG
227+ if (dev->dbg.dump_rx_pkt)
228+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
229+#endif
230 if (hdr_trans && ieee80211_has_morefrags(fc)) {
developeraace7f52022-06-24 13:40:42 +0800231 struct ieee80211_vif *vif;
232 int err;
developerd4975692022-07-15 18:30:03 +0800233@@ -762,6 +770,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer3fa816c2022-04-19 10:21:20 +0800234 tx_info->buf[1].skip_unmap = true;
235 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
236
237+#ifdef MTK_DEBUG
238+ if (dev->dbg.dump_txd)
239+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
240+ if (dev->dbg.dump_tx_pkt)
241+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
242+#endif
243 return 0;
244 }
245
developeraace7f52022-06-24 13:40:42 +0800246diff --git a/mt7915/main.c b/mt7915/main.c
developerf1313102022-10-11 11:02:55 +0800247index 0dffe82..7913059 100644
developeraace7f52022-06-24 13:40:42 +0800248--- a/mt7915/main.c
249+++ b/mt7915/main.c
250@@ -62,7 +62,11 @@ static int mt7915_start(struct ieee80211_hw *hw)
251 if (ret)
252 goto out;
253
254+#ifdef MTK_DEBUG
255+ ret = mt7915_mcu_set_sku_en(phy, !dev->dbg.sku_disable);
256+#else
257 ret = mt7915_mcu_set_sku_en(phy, true);
258+#endif
259 if (ret)
260 goto out;
261
developer3fa816c2022-04-19 10:21:20 +0800262diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developerf1313102022-10-11 11:02:55 +0800263index 2f6d328..c710624 100644
developer3fa816c2022-04-19 10:21:20 +0800264--- a/mt7915/mcu.c
265+++ b/mt7915/mcu.c
developeraace7f52022-06-24 13:40:42 +0800266@@ -195,6 +195,11 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
267 else
268 qid = MT_MCUQ_WM;
developer3fa816c2022-04-19 10:21:20 +0800269
developer3fa816c2022-04-19 10:21:20 +0800270+#ifdef MTK_DEBUG
271+ if (dev->dbg.dump_mcu_pkt)
272+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
273+#endif
developeraace7f52022-06-24 13:40:42 +0800274+
275 return mt76_tx_queue_skb_raw(dev, mdev->q_mcu[qid], skb, 0);
276 }
277
developer33907d42022-09-19 14:33:58 +0800278@@ -3178,6 +3183,8 @@ int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable)
developeraace7f52022-06-24 13:40:42 +0800279 .sku_enable = enable,
280 };
developer3fa816c2022-04-19 10:21:20 +0800281
developeraace7f52022-06-24 13:40:42 +0800282+ pr_info("%s: enable = %d\n", __func__, enable);
283+
284 return mt76_mcu_send_msg(&dev->mt76,
285 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
286 sizeof(req), true);
developer33907d42022-09-19 14:33:58 +0800287@@ -3453,6 +3460,43 @@ int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
developer3fa816c2022-04-19 10:21:20 +0800288 &req, sizeof(req), true);
289 }
developer1eeb8e82022-05-03 14:10:10 +0800290
developer3fa816c2022-04-19 10:21:20 +0800291+#ifdef MTK_DEBUG
292+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
293+{
294+ struct {
295+ __le32 args[3];
296+ } req = {
297+ .args = {
298+ cpu_to_le32(a1),
299+ cpu_to_le32(a2),
300+ cpu_to_le32(a3),
301+ },
302+ };
303+
304+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
305+}
306+
307+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
308+{
309+#define RED_DISABLE 0
310+#define RED_BY_HOST_ENABLE 1
311+#define RED_BY_WA_ENABLE 2
312+ int ret;
313+ u32 red_type = enabled > 0 ? RED_BY_WA_ENABLE : RED_DISABLE;
314+ __le32 req = cpu_to_le32(red_type);
315+
316+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RED_ENABLE), &req,
317+ sizeof(req), false);
318+ if (ret < 0)
319+ return ret;
320+
321+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
322+ MCU_WA_PARAM_RED, enabled, 0, true);
323+
324+ return 0;
325+}
326+#endif
developer1eeb8e82022-05-03 14:10:10 +0800327+
328 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
329 {
330 struct {
developer9e5bcc52022-09-27 10:30:15 +0800331@@ -3481,3 +3525,22 @@ int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
332
333 return 0;
334 }
335+
336+#ifdef MTK_DEBUG
337+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable)
338+{
339+ struct {
340+ u16 action;
341+ u8 _rsv1[2];
342+ u16 wcid;
343+ u8 enable;
344+ u8 _rsv2[5];
345+ } __packed req = {
346+ .action = cpu_to_le16(1),
347+ .wcid = cpu_to_le16(wcid),
348+ .enable = enable,
349+ };
350+
351+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MEC_CTRL), &req, sizeof(req), true);
352+}
353+#endif
developer3fa816c2022-04-19 10:21:20 +0800354diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developerf1313102022-10-11 11:02:55 +0800355index ed94980..bfb822f 100644
developer3fa816c2022-04-19 10:21:20 +0800356--- a/mt7915/mcu.h
357+++ b/mt7915/mcu.h
developeraace7f52022-06-24 13:40:42 +0800358@@ -259,6 +259,10 @@ enum {
developer3fa816c2022-04-19 10:21:20 +0800359 MCU_WA_PARAM_PDMA_RX = 0x04,
360 MCU_WA_PARAM_CPU_UTIL = 0x0b,
361 MCU_WA_PARAM_RED = 0x0e,
362+#ifdef MTK_DEBUG
363+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
364+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
365+#endif
366 };
367
368 enum mcu_mmps_mode {
369diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerf1313102022-10-11 11:02:55 +0800370index fe6a6d3..c0dfe10 100644
developer3fa816c2022-04-19 10:21:20 +0800371--- a/mt7915/mt7915.h
372+++ b/mt7915/mt7915.h
373@@ -9,6 +9,7 @@
374 #include "../mt76_connac.h"
375 #include "regs.h"
376
377+#define MTK_DEBUG 1
378 #define MT7915_MAX_INTERFACES 19
developer3fa816c2022-04-19 10:21:20 +0800379 #define MT7915_WTBL_SIZE 288
developeraace7f52022-06-24 13:40:42 +0800380 #define MT7916_WTBL_SIZE 544
developer33907d42022-09-19 14:33:58 +0800381@@ -336,6 +337,29 @@ struct mt7915_dev {
developer3fa816c2022-04-19 10:21:20 +0800382 struct reset_control *rstc;
383 void __iomem *dcm;
384 void __iomem *sku;
385+
386+#ifdef MTK_DEBUG
387+ u16 wlan_idx;
388+ struct {
389+ u32 fixed_rate;
390+ u32 l1debugfs_reg;
391+ u32 l2debugfs_reg;
392+ u32 mac_reg;
393+ u32 fw_dbg_module;
394+ u8 fw_dbg_lv;
395+ u32 bcn_total_cnt[2];
396+ u16 fwlog_seq;
397+ bool dump_mcu_pkt;
398+ bool dump_txd;
399+ bool dump_tx_pkt;
400+ bool dump_rx_pkt;
401+ bool dump_rx_raw;
402+ u32 token_idx;
developeraace7f52022-06-24 13:40:42 +0800403+ u8 sku_disable;
404+ u8 muru_onoff;
developer3fa816c2022-04-19 10:21:20 +0800405+ } dbg;
406+ const struct mt7915_dbg_reg_desc *dbg_reg;
407+#endif
408 };
409
410 enum {
developerf1313102022-10-11 11:02:55 +0800411@@ -594,4 +618,24 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
412 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
413 bool pci, int *irq);
developer3fa816c2022-04-19 10:21:20 +0800414
415+#ifdef MTK_DEBUG
416+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
417+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
418+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
419+void mt7915_dump_tmac_info(u8 *tmac_info);
420+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
421+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
developer9e5bcc52022-09-27 10:30:15 +0800422+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable);
developer3fa816c2022-04-19 10:21:20 +0800423+
424+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
425+enum {
426+ PKT_BIN_DEBUG_MCU,
427+ PKT_BIN_DEBUG_TXD,
428+ PKT_BIN_DEBUG_TX,
429+ PKT_BIN_DEBUG_RX,
430+ PKT_BIN_DEBUG_RX_RAW,
431+};
432+
433+#endif
434+
435 #endif
436diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
437new file mode 100644
developerf1313102022-10-11 11:02:55 +0800438index 0000000..58ba2cd
developer3fa816c2022-04-19 10:21:20 +0800439--- /dev/null
440+++ b/mt7915/mt7915_debug.h
441@@ -0,0 +1,1350 @@
442+#ifndef __MT7915_DEBUG_H
443+#define __MT7915_DEBUG_H
444+
445+#ifdef MTK_DEBUG
446+
447+#define DBG_INVALID_BASE 0xffffffff
448+#define DBG_INVALID_OFFSET 0x0
449+
450+struct __dbg_map {
451+ u32 phys;
452+ u32 maps;
453+ u32 size;
454+};
455+
456+struct __dbg_reg {
457+ u32 base;
458+ u32 offs;
459+};
460+
461+struct __dbg_mask {
462+ u32 end;
463+ u32 start;
464+};
465+
466+enum dbg_base_rev {
467+ MT_DBG_WFDMA0_BASE,
468+ MT_DBG_WFDMA1_BASE,
469+ MT_DBG_WFDMA0_PCIE1_BASE,
470+ MT_DBG_WFDMA1_PCIE1_BASE,
471+ MT_DBG_WFDMA_EXT_CSR_BASE,
472+ MT_DBG_SWDEF_BASE,
473+ __MT_DBG_BASE_REV_MAX,
474+};
475+
476+enum dbg_reg_rev {
477+ DBG_INT_SOURCE_CSR,
478+ DBG_INT_MASK_CSR,
479+ DBG_INT1_SOURCE_CSR,
480+ DBG_INT1_MASK_CSR,
481+ DBG_TX_RING_BASE,
482+ DBG_RX_EVENT_RING_BASE,
483+ DBG_RX_STS_RING_BASE,
484+ DBG_RX_DATA_RING_BASE,
485+ DBG_DMA_ICSC_FR0,
486+ DBG_DMA_ICSC_FR1,
487+ DBG_TMAC_ICSCR0,
488+ DBG_RMAC_RXICSRPT,
489+ DBG_MIB_M0SDR0,
490+ DBG_MIB_M0SDR3,
491+ DBG_MIB_M0SDR4,
492+ DBG_MIB_M0SDR5,
493+ DBG_MIB_M0SDR7,
494+ DBG_MIB_M0SDR8,
495+ DBG_MIB_M0SDR9,
496+ DBG_MIB_M0SDR10,
497+ DBG_MIB_M0SDR11,
498+ DBG_MIB_M0SDR12,
499+ DBG_MIB_M0SDR14,
500+ DBG_MIB_M0SDR15,
501+ DBG_MIB_M0SDR16,
502+ DBG_MIB_M0SDR17,
503+ DBG_MIB_M0SDR18,
504+ DBG_MIB_M0SDR19,
505+ DBG_MIB_M0SDR20,
506+ DBG_MIB_M0SDR21,
507+ DBG_MIB_M0SDR22,
508+ DBG_MIB_M0SDR23,
509+ DBG_MIB_M0DR0,
510+ DBG_MIB_M0DR1,
511+ DBG_MIB_MUBF,
512+ DBG_MIB_M0DR6,
513+ DBG_MIB_M0DR7,
514+ DBG_MIB_M0DR8,
515+ DBG_MIB_M0DR9,
516+ DBG_MIB_M0DR10,
517+ DBG_MIB_M0DR11,
518+ DBG_MIB_M0DR12,
519+ DBG_WTBLON_WDUCR,
520+ DBG_UWTBL_WDUCR,
521+ DBG_PLE_DRR_TABLE_CTRL,
522+ DBG_PLE_DRR_TABLE_RDATA,
523+ DBG_PLE_PBUF_CTRL,
524+ DBG_PLE_QUEUE_EMPTY,
525+ DBG_PLE_FREEPG_CNT,
526+ DBG_PLE_FREEPG_HEAD_TAIL,
527+ DBG_PLE_PG_HIF_GROUP,
528+ DBG_PLE_HIF_PG_INFO,
529+ DBG_PLE_PG_HIF_TXCMD_GROUP,
530+ DBG_PLE_HIF_TXCMD_PG_INFO,
531+ DBG_PLE_PG_CPU_GROUP,
532+ DBG_PLE_CPU_PG_INFO,
533+ DBG_PLE_FL_QUE_CTRL,
534+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
535+ DBG_PLE_TXCMD_Q_EMPTY,
536+ DBG_PLE_AC_QEMPTY,
537+ DBG_PLE_AC_OFFSET,
538+ DBG_PLE_STATION_PAUSE,
539+ DBG_PLE_DIS_STA_MAP,
540+ DBG_PSE_PBUF_CTRL,
541+ DBG_PSE_FREEPG_CNT,
542+ DBG_PSE_FREEPG_HEAD_TAIL,
543+ DBG_PSE_HIF0_PG_INFO,
544+ DBG_PSE_PG_HIF1_GROUP,
545+ DBG_PSE_HIF1_PG_INFO,
546+ DBG_PSE_PG_CPU_GROUP,
547+ DBG_PSE_CPU_PG_INFO,
548+ DBG_PSE_PG_PLE_GROUP,
549+ DBG_PSE_PLE_PG_INFO,
550+ DBG_PSE_PG_LMAC0_GROUP,
551+ DBG_PSE_LMAC0_PG_INFO,
552+ DBG_PSE_PG_LMAC1_GROUP,
553+ DBG_PSE_LMAC1_PG_INFO,
554+ DBG_PSE_PG_LMAC2_GROUP,
555+ DBG_PSE_LMAC2_PG_INFO,
556+ DBG_PSE_PG_LMAC3_GROUP,
557+ DBG_PSE_LMAC3_PG_INFO,
558+ DBG_PSE_PG_MDP_GROUP,
559+ DBG_PSE_MDP_PG_INFO,
560+ DBG_PSE_PG_PLE1_GROUP,
561+ DBG_PSE_PLE1_PG_INFO,
562+ DBG_AGG_AALCR0,
563+ DBG_AGG_AALCR1,
564+ DBG_AGG_AALCR2,
565+ DBG_AGG_AALCR3,
566+ DBG_AGG_AALCR4,
567+ DBG_AGG_B0BRR0,
568+ DBG_AGG_B1BRR0,
569+ DBG_AGG_B2BRR0,
570+ DBG_AGG_B3BRR0,
571+ DBG_AGG_AWSCR0,
572+ DBG_AGG_PCR0,
573+ DBG_AGG_TTCR0,
574+ DBG_MIB_M0ARNG0,
575+ DBG_MIB_M0DR2,
576+ DBG_MIB_M0DR13,
577+ __MT_DBG_REG_REV_MAX,
578+};
579+
580+enum dbg_mask_rev {
581+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
582+ DBG_MIB_M0SDR14_AMPDU,
583+ DBG_MIB_M0SDR15_AMPDU_ACKED,
584+ DBG_MIB_RX_FCS_ERROR_COUNT,
585+ __MT_DBG_MASK_REV_MAX,
586+};
587+
588+enum dbg_bit_rev {
589+ __MT_DBG_BIT_REV_MAX,
590+};
591+
592+static const u32 mt7915_dbg_base[] = {
593+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
594+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
595+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
596+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
597+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
598+ [MT_DBG_SWDEF_BASE] = 0x41f200,
599+};
600+
601+static const u32 mt7916_dbg_base[] = {
602+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
603+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
604+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
605+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
606+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
607+ [MT_DBG_SWDEF_BASE] = 0x411400,
608+};
609+
610+static const u32 mt7986_dbg_base[] = {
611+ [MT_DBG_WFDMA0_BASE] = 0x24000,
612+ [MT_DBG_WFDMA1_BASE] = 0x25000,
613+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
614+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
615+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
616+ [MT_DBG_SWDEF_BASE] = 0x411400,
617+};
618+
619+/* mt7915 regs with different base and offset */
620+static const struct __dbg_reg mt7915_dbg_reg[] = {
621+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
622+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
623+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
624+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
625+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
626+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
627+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
628+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
629+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
630+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
631+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
632+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
633+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
634+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
635+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
636+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
637+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
638+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
639+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
640+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
641+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
642+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
643+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
644+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
645+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
646+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
647+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
648+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
649+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
650+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
651+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
652+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
653+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
654+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
655+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
656+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
657+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
658+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
659+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
660+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
661+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
662+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
663+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
664+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
665+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
666+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
667+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
668+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
669+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
670+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
671+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
672+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
673+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
674+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
675+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
676+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
677+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
678+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
679+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
680+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
681+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
682+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
683+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
developerf32dabf2022-06-01 10:59:24 +0800684+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
developer3fa816c2022-04-19 10:21:20 +0800685+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
686+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
687+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
688+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
689+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
690+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
691+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
692+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
693+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
694+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
695+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
696+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
697+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
698+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
699+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
700+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
701+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
702+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
703+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
704+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
705+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
706+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
707+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
708+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
709+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
710+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
711+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
712+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
713+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
714+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
715+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
716+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
717+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
718+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
719+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
720+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
721+};
722+
723+/* mt7986/mt7916 regs with different base and offset */
724+static const struct __dbg_reg mt7916_dbg_reg[] = {
725+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
726+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
727+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
728+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
729+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
730+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
731+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
732+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
733+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
734+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
735+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
736+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
737+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
738+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
739+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
740+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
741+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
742+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
743+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
744+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
745+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
746+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
747+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
748+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
749+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
750+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
751+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
752+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
753+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
754+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
755+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
756+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
757+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
758+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
759+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
760+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
761+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
762+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
763+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
764+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
765+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
766+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
767+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
768+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
769+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
770+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
771+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
772+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
773+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
774+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
775+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
776+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
777+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
778+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
779+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
780+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
781+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
782+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
developerf32dabf2022-06-01 10:59:24 +0800783+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x36c},
developer3fa816c2022-04-19 10:21:20 +0800784+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
785+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
786+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
787+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
788+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
789+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
790+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
791+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
792+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
793+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
794+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
795+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
796+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
797+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
798+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
799+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
800+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
801+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
802+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
803+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
804+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
805+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
806+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
807+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
808+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
809+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
810+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
811+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
812+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
813+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
814+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
815+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
816+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
817+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
818+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
819+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
820+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
821+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
822+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
823+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
824+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
825+};
826+
827+static const struct __dbg_mask mt7915_dbg_mask[] = {
828+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
829+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
830+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
831+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
832+};
833+
834+static const struct __dbg_mask mt7916_dbg_mask[] = {
835+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
836+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
837+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
838+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
839+};
840+
841+/* used to differentiate between generations */
842+struct mt7915_dbg_reg_desc {
843+ const u32 id;
844+ const u32 *base_rev;
845+ const struct __dbg_reg *reg_rev;
846+ const struct __dbg_mask *mask_rev;
847+};
848+
849+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
850+ { 0x7915,
851+ mt7915_dbg_base,
852+ mt7915_dbg_reg,
853+ mt7915_dbg_mask
854+ },
855+ { 0x7906,
856+ mt7916_dbg_base,
857+ mt7916_dbg_reg,
858+ mt7916_dbg_mask
859+ },
860+ { 0x7986,
861+ mt7986_dbg_base,
862+ mt7916_dbg_reg,
863+ mt7916_dbg_mask
864+ },
865+};
866+
867+struct bin_debug_hdr {
868+ __le32 magic_num;
869+ __le16 serial_id;
870+ __le16 msg_type;
871+ __le16 len;
872+ __le16 des_len; /* descriptor len for rxd */
873+} __packed;
874+
875+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
876+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
877+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
878+
879+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
880+ (_dev)->dbg_reg->mask_rev[(id)].start)
881+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
882+ __DBG_REG_OFFS((_dev), (id)))
883+
884+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
885+ dev->dbg_reg->mask_rev[(id)].start)
886+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
887+ __DBG_MASK(dev, (id)))
888+
889+
890+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
891+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
892+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
893+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
894+
895+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
896+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
897+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
898+
899+/* WFDMA COMMON */
900+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
901+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
902+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
903+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
904+
905+/* WFDMA0 */
906+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
907+
908+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
909+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
910+
911+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
912+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
913+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
914+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
915+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
916+
917+
918+/* WFDMA1 */
919+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
920+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
921+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
922+
923+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
924+
925+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
926+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
927+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
928+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
929+
930+/* WFDMA0 PCIE1 */
931+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
932+
933+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
934+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
935+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
936+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
937+
938+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
939+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
940+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
941+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
942+
943+/* WFDMA1 PCIE1 */
944+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
945+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
946+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
947+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
948+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
949+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
950+
951+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
952+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
953+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
954+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
955+
956+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
957+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
958+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
959+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
960+
961+
962+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
963+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
964+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
965+
966+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
967+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
968+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
969+
970+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
971+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
972+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
973+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
974+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
975+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
976+
977+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
978+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
979+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
980+
981+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
982+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
983+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
984+
985+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
986+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
987+
988+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
989+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
990+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
991+
992+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
993+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
994+
995+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
996+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
997+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
998+
999+
1000+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
1001+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
1002+
1003+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
1004+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
1005+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
1006+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
1007+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
1008+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
1009+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
1010+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
1011+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
1012+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
1013+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
1014+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
1015+
1016+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
1017+
1018+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
1019+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
1020+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
1021+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
1022+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
1023+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
1024+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
1025+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
1026+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
1027+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
1028+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
1029+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
1030+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
1031+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
1032+
1033+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
1034+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
1035+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
1036+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
1037+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
1038+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
1039+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
1040+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
1041+
1042+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
1043+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
1044+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
1045+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
1046+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
1047+
1048+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
1049+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
1050+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
1051+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
1052+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
1053+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
1054+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
1055+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
1056+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
1057+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
1058+
1059+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
1060+
1061+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
1062+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
1063+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
1064+
developerf1313102022-10-11 11:02:55 +08001065+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_UWTBL_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
developer3fa816c2022-04-19 10:21:20 +08001066+
1067+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
1068+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
1069+
1070+
1071+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
1072+#define MT_DBG_WTBL_BASE 0x820D8000
1073+
1074+/* PLE related CRs. */
1075+#define MT_DBG_PLE_BASE 0x820C0000
1076+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
1077+
1078+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
1079+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
1080+
1081+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
1082+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
1083+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
1084+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
1085+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
1086+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
1087+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
1088+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
1089+
1090+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
1091+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
1092+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
1093+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
1094+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
1095+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
1096+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
1097+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
1098+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
1099+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
1100+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
1101+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
1102+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
1103+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
1104+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
1105+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
1106+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
1107+
1108+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
1109+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
1110+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1111+
1112+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1113+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1114+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1115+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1116+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
1117+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
1118+
1119+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
1120+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
1121+
1122+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
1123+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
1124+
1125+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1126+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1127+
1128+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1129+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1130+
1131+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1132+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1133+
1134+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1135+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1136+
1137+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
1138+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
1139+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
1140+
1141+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
1142+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
1143+
1144+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
1145+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
1146+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
1147+
1148+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
1149+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
1150+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
1151+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1152+
1153+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1154+
1155+/* pseinfo related CRs. */
1156+#define MT_DBG_PSE_BASE 0x820C8000
1157+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1158+
developerf32dabf2022-06-01 10:59:24 +08001159+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1160+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PSE(0x0b0)
1161+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1162+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1163+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PSE(0x110)
1164+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1165+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1166+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1167+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1168+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1169+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1170+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1171+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1172+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1173+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1174+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1175+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1176+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1177+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1178+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1179+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1180+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1181+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1182+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
developer3fa816c2022-04-19 10:21:20 +08001183+
1184+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1185+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1186+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1187+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1188+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1189+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1190+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1191+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1192+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1193+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1194+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1195+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1196+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1197+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1198+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1199+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1200+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1201+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1202+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1203+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1204+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1205+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1206+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1207+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1208+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1209+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1210+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1211+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1212+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1213+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1214+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1215+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1216+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1217+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1218+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1219+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1220+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1221+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1222+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1223+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1224+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1225+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1226+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1227+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1228+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1229+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1230+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1231+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1232+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1233+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1234+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1235+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1236+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1237+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1238+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1239+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1240+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1241+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1242+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1243+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1244+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1245+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1246+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1247+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1248+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1249+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1250+
1251+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1252+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1253+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1254+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1255+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1256+
1257+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1258+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1259+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1260+
1261+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1262+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1263+
1264+
1265+/* AGG */
1266+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1267+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1268+
1269+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1270+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1271+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1272+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1273+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1274+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1275+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1276+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1277+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1278+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1279+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1280+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1281+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1282+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1283+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1284+
1285+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1286+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1287+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1288+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1289+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1290+
1291+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1292+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1293+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1294+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1295+
1296+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1297+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1298+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1299+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1300+
1301+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1302+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1303+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1304+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1305+
1306+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1307+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1308+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1309+
1310+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1311+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1312+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1313+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1314+
1315+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1316+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1317+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1318+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1319+
1320+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1321+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1322+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1323+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1324+
1325+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1326+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1327+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1328+
1329+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1330+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1331+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1332+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1333+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1334+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1335+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1336+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1337+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1338+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1339+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1340+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1341+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1342+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1343+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1344+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1345+
1346+/* mt7915 host DMA*/
1347+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1348+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1349+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1350+
1351+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1352+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1353+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1354+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1355+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1356+
1357+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1358+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1359+
1360+/* mt7986 host DMA */
1361+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1362+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1363+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1364+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1365+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1366+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1367+
1368+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1369+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1370+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1371+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1372+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1373+
1374+/* MCU DMA */
1375+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1376+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1377+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1378+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1379+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1380+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1381+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1382+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1383+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1384+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1385+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1386+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1387+
1388+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1389+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1390+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1391+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1392+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1393+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1394+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1395+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1396+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1397+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1398+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1399+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1400+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1401+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1402+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1403+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1404+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1405+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1406+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1407+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1408+
1409+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1410+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1411+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1412+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1413+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1414+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1415+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1416+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1417+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1418+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1419+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1420+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1421+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1422+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1423+
1424+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1425+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1426+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1427+/* mt7986 add */
1428+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1429+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1430+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1431+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1432+
1433+
1434+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1435+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1436+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1437+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1438+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1439+
1440+/* mt7986 add */
1441+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1442+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1443+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1444+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1445+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1446+
1447+/* MEM DMA */
1448+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1449+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1450+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1451+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1452+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1453+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1454+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1455+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1456+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1457+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1458+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1459+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1460+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1461+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1462+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1463+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1464+
1465+enum resource_attr {
1466+ HIF_TX_DATA,
1467+ HIF_TX_CMD,
1468+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1469+ HIF_TX_FWDL,
1470+ HIF_RX_DATA,
1471+ HIF_RX_EVENT,
1472+ RING_ATTR_NUM
1473+};
1474+
1475+struct hif_pci_tx_ring_desc {
1476+ u32 hw_int_mask;
1477+ u16 ring_size;
1478+ enum resource_attr ring_attr;
1479+ u8 band_idx;
1480+ char *const ring_info;
1481+};
1482+
1483+struct hif_pci_rx_ring_desc {
1484+ u32 hw_desc_base;
1485+ u32 hw_int_mask;
1486+ u16 ring_size;
1487+ enum resource_attr ring_attr;
1488+ u16 max_rx_process_cnt;
1489+ u16 max_sw_read_idx_inc;
1490+ char *const ring_info;
1491+};
1492+
1493+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1494+ {
1495+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1496+ .ring_size = 128,
1497+ .ring_attr = HIF_TX_FWDL,
1498+ .ring_info = "FWDL"
1499+ },
1500+ {
1501+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1502+ .ring_size = 256,
1503+ .ring_attr = HIF_TX_CMD_WM,
1504+ .ring_info = "cmd to WM"
1505+ },
1506+ {
1507+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1508+ .ring_size = 2048,
1509+ .ring_attr = HIF_TX_DATA,
1510+ .ring_info = "band0 TXD"
1511+ },
1512+ {
1513+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1514+ .ring_size = 2048,
1515+ .ring_attr = HIF_TX_DATA,
1516+ .ring_info = "band1 TXD"
1517+ },
1518+ {
1519+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1520+ .ring_size = 256,
1521+ .ring_attr = HIF_TX_CMD,
1522+ .ring_info = "cmd to WA"
1523+ }
1524+};
1525+
1526+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1527+ {
1528+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1529+ .ring_size = 1536,
1530+ .ring_attr = HIF_RX_DATA,
1531+ .ring_info = "band0 RX data"
1532+ },
1533+ {
1534+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1535+ .ring_size = 1536,
1536+ .ring_attr = HIF_RX_DATA,
1537+ .ring_info = "band1 RX data"
1538+ },
1539+ {
1540+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1541+ .ring_size = 512,
1542+ .ring_attr = HIF_RX_EVENT,
1543+ .ring_info = "event from WM"
1544+ },
1545+ {
1546+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1547+ .ring_size = 1024,
1548+ .ring_attr = HIF_RX_EVENT,
1549+ .ring_info = "event from WA band0"
1550+ },
1551+ {
1552+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1553+ .ring_size = 512,
1554+ .ring_attr = HIF_RX_EVENT,
1555+ .ring_info = "event from WA band1"
1556+ }
1557+};
1558+
1559+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1560+ {
1561+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1562+ .ring_size = 128,
1563+ .ring_attr = HIF_TX_FWDL,
1564+ .ring_info = "FWDL"
1565+ },
1566+ {
1567+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1568+ .ring_size = 256,
1569+ .ring_attr = HIF_TX_CMD_WM,
1570+ .ring_info = "cmd to WM"
1571+ },
1572+ {
1573+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1574+ .ring_size = 2048,
1575+ .ring_attr = HIF_TX_DATA,
1576+ .ring_info = "band0 TXD"
1577+ },
1578+ {
1579+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1580+ .ring_size = 2048,
1581+ .ring_attr = HIF_TX_DATA,
1582+ .ring_info = "band1 TXD"
1583+ },
1584+ {
1585+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1586+ .ring_size = 256,
1587+ .ring_attr = HIF_TX_CMD,
1588+ .ring_info = "cmd to WA"
1589+ }
1590+};
1591+
1592+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1593+ {
1594+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1595+ .ring_size = 1536,
1596+ .ring_attr = HIF_RX_DATA,
1597+ .ring_info = "band0 RX data"
1598+ },
1599+ {
1600+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1601+ .ring_size = 1536,
1602+ .ring_attr = HIF_RX_DATA,
1603+ .ring_info = "band1 RX data"
1604+ },
1605+ {
1606+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1607+ .ring_size = 512,
1608+ .ring_attr = HIF_RX_EVENT,
1609+ .ring_info = "event from WM"
1610+ },
1611+ {
1612+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1613+ .ring_size = 512,
1614+ .ring_attr = HIF_RX_EVENT,
1615+ .ring_info = "event from WA"
1616+ },
1617+ {
1618+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1619+ .ring_size = 1024,
1620+ .ring_attr = HIF_RX_EVENT,
1621+ .ring_info = "STS WA band0"
1622+ },
1623+ {
1624+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1625+ .ring_size = 512,
1626+ .ring_attr = HIF_RX_EVENT,
1627+ .ring_info = "STS WA band1"
1628+ },
1629+};
1630+
1631+/* mibinfo related CRs. */
1632+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1633+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1634+
1635+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1636+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1637+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1638+
1639+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1640+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1641+
1642+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1643+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1644+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1645+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1646+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1647+
1648+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1649+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1650+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1651+
1652+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1653+
1654+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1655+
1656+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1657+
1658+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1659+
1660+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1661+
1662+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1663+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1664+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1665+
1666+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1667+
1668+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1669+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1670+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1671+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1672+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1673+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1674+
1675+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1676+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1677+
1678+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1679+
1680+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1681+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1682+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1683+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1684+
1685+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1686+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1687+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1688+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1689+
1690+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1691+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1692+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1693+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1694+
1695+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1696+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1697+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1698+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1699+
1700+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1701+
1702+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1703+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1704+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1705+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1706+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1707+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1708+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1709+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1710+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1711+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1712+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1713+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1714+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1715+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1716+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1717+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1718+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1719+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1720+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1721+
1722+
1723+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1724+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1725+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1726+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1727+
1728+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1729+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1730+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1731+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1732+
1733+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1734+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1735+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1736+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1737+
1738+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1739+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1740+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1741+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1742+
1743+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1744+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1745+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1746+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1747+
1748+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1749+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1750+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1751+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1752+
1753+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1754+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1755+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1756+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1757+
1758+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1759+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1760+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1761+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1762+
1763+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1764+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1765+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1766+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1767+
1768+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1769+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1770+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1771+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1772+
1773+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1774+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1775+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1776+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1777+/* TXD */
1778+
1779+#define MT_TXD1_ETYP BIT(15)
1780+#define MT_TXD1_VLAN BIT(14)
1781+#define MT_TXD1_RMVL BIT(13)
1782+#define MT_TXD1_AMS BIT(13)
1783+#define MT_TXD1_EOSP BIT(12)
1784+#define MT_TXD1_MRD BIT(11)
1785+
1786+#define MT_TXD7_CTXD BIT(26)
1787+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1788+#define MT_TXD7_TAT GENMASK(9, 0)
1789+
1790+#endif
1791+#endif
1792diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1793new file mode 100644
developerf1313102022-10-11 11:02:55 +08001794index 0000000..747a901
developer3fa816c2022-04-19 10:21:20 +08001795--- /dev/null
1796+++ b/mt7915/mtk_debugfs.c
developer9e5bcc52022-09-27 10:30:15 +08001797@@ -0,0 +1,2925 @@
developer3fa816c2022-04-19 10:21:20 +08001798+#include<linux/inet.h>
1799+#include "mt7915.h"
1800+#include "mt7915_debug.h"
1801+#include "mac.h"
1802+#include "mcu.h"
1803+
1804+#ifdef MTK_DEBUG
1805+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1806+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1807+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1808+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1809+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1810+
1811+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1812+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1813+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1814+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1815+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1816+
1817+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1818+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1819+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1820+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1821+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1822+
1823+enum mt7915_wtbl_type {
1824+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1825+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1826+ WTBL_TYPE_KEY, /* Key Table */
1827+ MAX_NUM_WTBL_TYPE
1828+};
1829+
1830+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1831+ enum mt7915_wtbl_type type, u16 start_dw,
1832+ u16 len, void *buf)
1833+{
1834+ u32 *dest_cpy = (u32 *)buf;
1835+ u32 size_dw = len;
1836+ u32 src = 0;
1837+
1838+ if (!buf)
1839+ return 0xFF;
1840+
1841+ if (type == WTBL_TYPE_LMAC) {
1842+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1843+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1844+ src = LWTBL_IDX2BASE(idx, start_dw);
1845+ } else if (type == WTBL_TYPE_UMAC) {
1846+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1847+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1848+ src = UWTBL_IDX2BASE(idx, start_dw);
1849+ } else if (type == WTBL_TYPE_KEY) {
1850+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1851+ MT_UWTBL_TOP_WDUCR_TARGET |
1852+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1853+ src = KEYTBL_IDX2BASE(idx, start_dw);
1854+ }
1855+
1856+ while (size_dw--) {
1857+ *dest_cpy++ = mt76_rr(dev, src);
1858+ src += 4;
1859+ };
1860+
1861+ return 0;
1862+}
1863+
1864+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1865+ enum mt7915_wtbl_type type, u16 start_dw,
1866+ u32 val)
1867+{
1868+ u32 addr = 0;
1869+
1870+ if (type == WTBL_TYPE_LMAC) {
1871+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1872+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1873+ addr = LWTBL_IDX2BASE(idx, start_dw);
1874+ } else if (type == WTBL_TYPE_UMAC) {
1875+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1876+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1877+ addr = UWTBL_IDX2BASE(idx, start_dw);
1878+ } else if (type == WTBL_TYPE_KEY) {
1879+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1880+ MT_UWTBL_TOP_WDUCR_TARGET |
1881+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1882+ addr = KEYTBL_IDX2BASE(idx, start_dw);
1883+ }
1884+
1885+ mt76_wr(dev, addr, val);
1886+
1887+ return 0;
1888+}
1889+
1890+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
1891+{
1892+ struct bin_debug_hdr *hdr;
1893+ char *buf;
1894+
1895+ if (len > 1500 - sizeof(*hdr))
1896+ len = 1500 - sizeof(*hdr);
1897+
1898+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
1899+ if (!buf)
1900+ return;
1901+
1902+ hdr = (struct bin_debug_hdr *)buf;
1903+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
1904+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
1905+ hdr->msg_type = cpu_to_le16(type);
1906+ hdr->len = cpu_to_le16(len);
1907+ hdr->des_len = cpu_to_le16(des_len);
1908+
1909+ memcpy(buf + sizeof(*hdr), data, len);
1910+
1911+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
1912+}
1913+
1914+static int
1915+mt7915_fw_debug_module_set(void *data, u64 module)
1916+{
1917+ struct mt7915_dev *dev = data;
1918+
1919+ dev->dbg.fw_dbg_module = module;
1920+ return 0;
1921+}
1922+
1923+static int
1924+mt7915_fw_debug_module_get(void *data, u64 *module)
1925+{
1926+ struct mt7915_dev *dev = data;
1927+
1928+ *module = dev->dbg.fw_dbg_module;
1929+ return 0;
1930+}
1931+
1932+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
1933+ mt7915_fw_debug_module_set, "%lld\n");
1934+
1935+static int
1936+mt7915_fw_debug_level_set(void *data, u64 level)
1937+{
1938+ struct mt7915_dev *dev = data;
1939+
1940+ dev->dbg.fw_dbg_lv = level;
1941+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
1942+ return 0;
1943+}
1944+
1945+static int
1946+mt7915_fw_debug_level_get(void *data, u64 *level)
1947+{
1948+ struct mt7915_dev *dev = data;
1949+
1950+ *level = dev->dbg.fw_dbg_lv;
1951+ return 0;
1952+}
1953+
1954+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
1955+ mt7915_fw_debug_level_set, "%lld\n");
1956+
1957+#define MAX_TX_MODE 12
1958+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
1959+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
1960+ "HE_TRIG", "HE_MU", "N/A"};
1961+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
1962+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
1963+ "N/A"};
1964+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
1965+ "48M", "54M", "N/A"};
1966+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
1967+ "20/40/80/160/80+80MHz"};
1968+
1969+static char *hw_rate_ofdm_str(u16 ofdm_idx)
1970+{
1971+ switch (ofdm_idx) {
1972+ case 11: /* 6M */
1973+ return HW_TX_RATE_OFDM_STR[0];
1974+
1975+ case 15: /* 9M */
1976+ return HW_TX_RATE_OFDM_STR[1];
1977+
1978+ case 10: /* 12M */
1979+ return HW_TX_RATE_OFDM_STR[2];
1980+
1981+ case 14: /* 18M */
1982+ return HW_TX_RATE_OFDM_STR[3];
1983+
1984+ case 9: /* 24M */
1985+ return HW_TX_RATE_OFDM_STR[4];
1986+
1987+ case 13: /* 36M */
1988+ return HW_TX_RATE_OFDM_STR[5];
1989+
1990+ case 8: /* 48M */
1991+ return HW_TX_RATE_OFDM_STR[6];
1992+
1993+ case 12: /* 54M */
1994+ return HW_TX_RATE_OFDM_STR[7];
1995+
1996+ default:
1997+ return HW_TX_RATE_OFDM_STR[8];
1998+ }
1999+}
2000+
2001+static char *hw_rate_str(u8 mode, u16 rate_idx)
2002+{
2003+ if (mode == 0)
2004+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
2005+ else if (mode == 1)
2006+ return hw_rate_ofdm_str(rate_idx);
2007+ else
2008+ return "MCS";
2009+}
2010+
2011+static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
2012+{
2013+ u16 txmode, mcs, nss, stbc;
2014+
2015+ txmode = FIELD_GET(GENMASK(9, 6), txrate);
2016+ mcs = FIELD_GET(GENMASK(5, 0), txrate);
2017+ nss = FIELD_GET(GENMASK(12, 10), txrate);
2018+ stbc = FIELD_GET(BIT(13), txrate);
2019+
2020+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
2021+ rate_idx + 1, txrate,
2022+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
2023+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
2024+}
2025+
2026+#define LWTBL_LEN_IN_DW 32
2027+#define UWTBL_LEN_IN_DW 8
2028+#define ONE_KEY_ENTRY_LEN_IN_DW 8
developerf32dabf2022-06-01 10:59:24 +08002029+static int mt7915_sta_info(struct seq_file *s, void *data)
2030+{
2031+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2032+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2033+ u16 i = 0;
2034+
2035+ for (i=0; i < mt7915_wtbl_size(dev); i++) {
2036+ mt7915_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
2037+ LWTBL_LEN_IN_DW, lwtbl);
2038+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1])
2039+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
2040+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2041+ }
2042+
2043+ return 0;
2044+}
2045+
developer3fa816c2022-04-19 10:21:20 +08002046+static int mt7915_wtbl_read(struct seq_file *s, void *data)
2047+{
2048+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2049+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2050+ int x;
2051+ u32 *addr = 0;
2052+ u32 dw_value = 0;
2053+
2054+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
2055+ LWTBL_LEN_IN_DW, lwtbl);
2056+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2057+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2058+ MT_DBG_WTBLON_TOP_WDUCR,
2059+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2060+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
2061+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
2062+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2063+ x,
2064+ lwtbl[x * 4 + 3],
2065+ lwtbl[x * 4 + 2],
2066+ lwtbl[x * 4 + 1],
2067+ lwtbl[x * 4]);
2068+ }
2069+
2070+ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
2071+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2072+
2073+ // DW0, DW1
2074+ seq_printf(s, "LWTBL DW 0/1\n\t");
2075+ addr = (u32 *)&(lwtbl[0]);
2076+ dw_value = *addr;
2077+ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2078+ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
2079+ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
2080+ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
2081+ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2082+ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2083+ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
2084+ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
2085+ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
2086+
2087+ // DW2
2088+ seq_printf(s, "LWTBL DW 2\n\t");
2089+ addr = (u32 *)&(lwtbl[2*4]);
2090+ dw_value = *addr;
2091+ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2092+ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
2093+ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
2094+ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
2095+ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
2096+ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
2097+ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2098+ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
2099+ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
2100+ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2101+ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2102+ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
2103+ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
2104+ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
2105+ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
2106+
2107+ // DW3
2108+ seq_printf(s, "LWTBL DW 3\n\t");
2109+ addr = (u32 *)&(lwtbl[3*4]);
2110+ dw_value = *addr;
2111+ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
2112+ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
2113+ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
2114+ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
2115+ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
2116+ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2117+ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2118+ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
2119+ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
2120+ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
2121+ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
2122+ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
2123+ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
2124+
2125+ // DW4
2126+ seq_printf(s, "LWTBL DW 4\n\t");
2127+ addr = (u32 *)&(lwtbl[4*4]);
2128+ dw_value = *addr;
2129+ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2130+ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
2131+ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
2132+ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
2133+ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2134+ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
2135+ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
2136+ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
2137+ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
2138+ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
2139+ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
2140+ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
2141+ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
2142+ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
2143+ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
2144+ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
2145+
2146+ // DW5
2147+ seq_printf(s, "LWTBL DW 5\n\t");
2148+ addr = (u32 *)&(lwtbl[5*4]);
2149+ dw_value = *addr;
2150+ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2151+ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
2152+ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
2153+ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
2154+ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
2155+ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
2156+ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
2157+ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2158+ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2159+ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2160+ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2161+ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2162+ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
2163+ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
2164+ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
2165+ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
2166+ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
2167+ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
2168+
2169+ // DW6
2170+ seq_printf(s, "LWTBL DW 6\n\t");
2171+ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
2172+ addr = (u32 *)&(lwtbl[6*4]);
2173+ dw_value = *addr;
2174+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
2175+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
2176+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
2177+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
2178+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
2179+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
2180+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
2181+ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
2182+
2183+ // DW7
2184+ seq_printf(s, "LWTBL DW 7\n\t");
2185+ addr = (u32 *)&(lwtbl[7*4]);
2186+ dw_value = *addr;
2187+ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2188+ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
2189+ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
2190+ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
2191+ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
2192+ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
2193+ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
2194+ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
2195+ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
2196+ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2197+ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
2198+ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
2199+ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
2200+ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2201+ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2202+ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
2203+ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
2204+ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
2205+
2206+ // DW8
2207+ seq_printf(s, "LWTBL DW 8\n\t");
2208+ addr = (u32 *)&(lwtbl[8*4]);
2209+ dw_value = *addr;
2210+ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
2211+ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
2212+ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
2213+ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
2214+ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
2215+ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
2216+
2217+ // DW9
2218+ seq_printf(s, "LWTBL DW 9\n\t");
2219+ addr = (u32 *)&(lwtbl[9*4]);
2220+ dw_value = *addr;
2221+ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
2222+ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
2223+ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
2224+ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
2225+ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
2226+ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
2227+ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
2228+ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
2229+ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
2230+ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
2231+
2232+ // DW10
2233+ seq_printf(s, "LWTBL DW 10\n");
2234+ addr = (u32 *)&(lwtbl[10*4]);
2235+ dw_value = *addr;
2236+ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
2237+ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
2238+ // DW11
2239+ seq_printf(s, "LWTBL DW 11\n");
2240+ addr = (u32 *)&(lwtbl[11*4]);
2241+ dw_value = *addr;
2242+ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
2243+ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
2244+ // DW12
2245+ seq_printf(s, "LWTBL DW 12\n");
2246+ addr = (u32 *)&(lwtbl[12*4]);
2247+ dw_value = *addr;
2248+ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
2249+ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
2250+ // DW13
2251+ seq_printf(s, "LWTBL DW 13\n");
2252+ addr = (u32 *)&(lwtbl[13*4]);
2253+ dw_value = *addr;
2254+ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
2255+ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
2256+
2257+ //DW28
2258+ seq_printf(s, "LWTBL DW 28\n\t");
2259+ addr = (u32 *)&(lwtbl[28*4]);
2260+ dw_value = *addr;
2261+ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2262+ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
2263+
2264+ //DW29
2265+ seq_printf(s, "LWTBL DW 29\n");
2266+ addr = (u32 *)&(lwtbl[29*4]);
2267+ dw_value = *addr;
2268+ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
2269+ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
2270+ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
2271+ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
2272+ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
2273+
2274+ //DW30
2275+ seq_printf(s, "LWTBL DW 30\n\t");
2276+ addr = (u32 *)&(lwtbl[30*4]);
2277+ dw_value = *addr;
2278+ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2279+ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2280+ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2281+ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2282+
2283+ //DW31
2284+ seq_printf(s, "LWTBL DW 31\n\t");
2285+ addr = (u32 *)&(lwtbl[31*4]);
2286+ dw_value = *addr;
2287+ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2288+ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2289+ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2290+ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2291+
2292+ return 0;
2293+}
2294+
2295+static int mt7915_uwtbl_read(struct seq_file *s, void *data)
2296+{
2297+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2298+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
2299+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
2300+ int x;
2301+ u32 *addr = 0;
2302+ u32 dw_value = 0;
2303+ u32 amsdu_len = 0;
2304+ u32 u2SN = 0;
2305+ u16 keyloc0, keyloc1;
2306+
2307+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
2308+ UWTBL_LEN_IN_DW, uwtbl);
2309+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2310+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2311+ MT_DBG_WTBLON_TOP_WDUCR,
2312+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2313+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
2314+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
2315+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2316+ x,
2317+ uwtbl[x * 4 + 3],
2318+ uwtbl[x * 4 + 2],
2319+ uwtbl[x * 4 + 1],
2320+ uwtbl[x * 4]);
2321+ }
2322+
2323+ /* UMAC WTBL DW 0 */
2324+ seq_printf(s, "\nUWTBL PN\n\t");
2325+ addr = (u32 *)&(uwtbl[0]);
2326+ dw_value = *addr;
2327+ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2328+ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2329+ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2330+ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
2331+
2332+ addr = (u32 *)&(uwtbl[1 * 4]);
2333+ dw_value = *addr;
2334+ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2335+ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
2336+
2337+ /* UMAC WTBL DW SN part */
2338+ seq_printf(s, "\nUWTBL SN\n");
2339+ addr = (u32 *)&(uwtbl[2 * 4]);
2340+ dw_value = *addr;
2341+ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
2342+ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
2343+
2344+ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
2345+ addr = (u32 *)&(uwtbl[3 * 4]);
2346+ dw_value = *addr;
2347+ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
2348+ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
2349+ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
2350+ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2351+
2352+ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
2353+ addr = (u32 *)&(uwtbl[4 * 4]);
2354+ dw_value = *addr;
2355+ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
2356+ seq_printf(s, "TID5_SN:%u\n", u2SN);
2357+ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
2358+ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
2359+
2360+ addr = (u32 *)&(uwtbl[1 * 4]);
2361+ dw_value = *addr;
2362+ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2363+
2364+ /* UMAC WTBL DW 0 */
2365+ seq_printf(s, "\nUWTBL others\n");
2366+
2367+ addr = (u32 *)&(uwtbl[5 * 4]);
2368+ dw_value = *addr;
2369+ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
2370+ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
2371+ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
2372+ FIELD_GET(GENMASK(10, 0), dw_value),
2373+ FIELD_GET(GENMASK(26, 16), dw_value));
2374+ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
2375+ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
2376+
2377+ addr = (u32 *)&(uwtbl[6*4]);
2378+ dw_value = *addr;
2379+ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
2380+
2381+ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
2382+ if (amsdu_len == 0)
2383+ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
2384+ else if (amsdu_len == 1)
2385+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2386+ 1,
2387+ 255,
2388+ amsdu_len);
2389+ else
2390+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2391+ 256 * (amsdu_len - 1),
2392+ 256 * (amsdu_len - 1) + 255,
2393+ amsdu_len
2394+ );
2395+ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
2396+ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
2397+ FIELD_GET(GENMASK(8, 6), dw_value));
2398+
2399+ /* Parse KEY link */
2400+ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
2401+ if(keyloc0 != GENMASK(10, 0)) {
2402+ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
2403+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2404+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2405+ MT_DBG_WTBLON_TOP_WDUCR,
2406+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2407+ KEYTBL_IDX2BASE(keyloc0, 0));
2408+
2409+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2410+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2411+ x,
2412+ keytbl[x * 4 + 3],
2413+ keytbl[x * 4 + 2],
2414+ keytbl[x * 4 + 1],
2415+ keytbl[x * 4]);
2416+ }
2417+ }
2418+
2419+ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
2420+ if(keyloc1 != GENMASK(26, 16)) {
2421+ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
2422+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2423+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2424+ MT_DBG_WTBLON_TOP_WDUCR,
2425+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2426+ KEYTBL_IDX2BASE(keyloc1, 0));
2427+
2428+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2429+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2430+ x,
2431+ keytbl[x * 4 + 3],
2432+ keytbl[x * 4 + 2],
2433+ keytbl[x * 4 + 1],
2434+ keytbl[x * 4]);
2435+ }
2436+ }
2437+ return 0;
2438+}
2439+
2440+static void
2441+dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2442+{
2443+ u32 base, cnt, cidx, didx, queue_cnt;
2444+
2445+ base= mt76_rr(dev, ring_base);
2446+ cnt = mt76_rr(dev, ring_base + 4);
2447+ cidx = mt76_rr(dev, ring_base + 8);
2448+ didx = mt76_rr(dev, ring_base + 12);
2449+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2450+
2451+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2452+}
2453+
2454+static void
2455+dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2456+{
2457+ u32 base, cnt, cidx, didx, queue_cnt;
2458+
2459+ base= mt76_rr(dev, ring_base);
2460+ cnt = mt76_rr(dev, ring_base + 4);
2461+ cidx = mt76_rr(dev, ring_base + 8);
2462+ didx = mt76_rr(dev, ring_base + 12);
2463+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2464+
2465+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2466+}
2467+
2468+static void
2469+mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2470+{
2471+ u32 sys_ctrl[10] = {};
2472+
2473+ /* HOST DMA */
2474+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2475+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2476+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2477+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2478+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
2479+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
2480+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2481+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
2482+ seq_printf(s, "HOST_DMA Configuration\n");
2483+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2484+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2485+ seq_printf(s, "%10s %10x %10x\n",
2486+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2487+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2488+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2489+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2490+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2491+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2492+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2493+
2494+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2495+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2496+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2497+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2498+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2499+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2500+
2501+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT1_SOURCE_CSR);
2502+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT1_MASK_CSR);
2503+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR);
2504+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR);
2505+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR);
2506+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR);
2507+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_GLO_CFG);
2508+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_GLO_CFG);
2509+ seq_printf(s, "%10s %10x %10x\n",
2510+ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
2511+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2512+ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2513+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2514+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2515+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2516+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2517+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2518+ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2519+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2520+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2521+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2522+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2523+
2524+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2525+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2526+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2527+ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2528+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2529+
2530+ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
2531+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2532+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2533+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_WFDMA0_PCIE1_RX1_CTRL0);
2534+
2535+ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
2536+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2537+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2538+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2539+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
2540+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2541+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2542+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2543+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_EVENT_RING_CTRL(0));
2544+ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
2545+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2546+
2547+ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
2548+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2549+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2550+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA1_PCIE1_TX19_CTRL0);
2551+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_WFDMA1_PCIE1_RX2_CTRL0);
2552+}
2553+
2554+static void
2555+mt7915_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2556+{
2557+ u32 sys_ctrl[9] = {};
2558+
2559+ /* MCU DMA information */
2560+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2561+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2562+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2563+
2564+ sys_ctrl[3] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
2565+ sys_ctrl[4] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
2566+ sys_ctrl[5] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
2567+ sys_ctrl[6] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
2568+ sys_ctrl[7] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
2569+ sys_ctrl[8] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
2570+
2571+ seq_printf(s, "MCU_DMA Configuration\n");
2572+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2573+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2574+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2575+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2576+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2577+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2578+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2579+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2580+
2581+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2582+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
2583+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2584+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2585+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2586+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2587+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2588+ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
2589+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2590+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2591+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2592+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2593+
2594+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2595+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2596+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2597+ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2598+ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2599+ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2600+ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2601+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2602+ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2603+ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2604+ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2605+
2606+ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
2607+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2608+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2609+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
2610+ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
2611+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
2612+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
2613+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
2614+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
2615+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
2616+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
2617+
2618+ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
2619+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2620+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2621+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
2622+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2623+}
2624+
2625+static void
2626+mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2627+{
2628+ u32 sys_ctrl[5] = {};
2629+
2630+ /* HOST DMA */
2631+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2632+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2633+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2634+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2635+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2636+
2637+ seq_printf(s, "HOST_DMA Configuration\n");
2638+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2639+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2640+ seq_printf(s, "%10s %10x %10x\n",
2641+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2642+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2643+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[4],
2644+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK, sys_ctrl[4]),
2645+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK, sys_ctrl[4]),
2646+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK, sys_ctrl[4]),
2647+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK, sys_ctrl[4]));
2648+
2649+
2650+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2651+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2652+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2653+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2654+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
2655+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2656+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2657+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2658+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2659+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
2660+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2661+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
2662+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2663+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2664+}
2665+
2666+static void
2667+mt7986_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2668+{
2669+ u32 sys_ctrl[3] = {};
2670+
2671+ /* MCU DMA information */
2672+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2673+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2674+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2675+
2676+ seq_printf(s, "MCU_DMA Configuration\n");
2677+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2678+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2679+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2680+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2681+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2682+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2683+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2684+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2685+
2686+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2687+ seq_printf(s, "%22s %10s %10s %10s %10s %10s\n",
2688+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2689+ dump_dma_tx_ring_info(s, dev, "T0:Event (WM2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2690+ dump_dma_tx_ring_info(s, dev, "T1:Event (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2691+ dump_dma_tx_ring_info(s, dev, "T2:TxDone (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2692+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1 (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2693+ dump_dma_tx_ring_info(s, dev, "T4:TXD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2694+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2695+ dump_dma_tx_ring_info(s, dev, "T6:TXD (WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2696+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2697+ dump_dma_rx_ring_info(s, dev, "R1:Cmd (H2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2698+ dump_dma_rx_ring_info(s, dev, "R2:TXD (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2699+ dump_dma_rx_ring_info(s, dev, "R3:TXD1 (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2700+ dump_dma_rx_ring_info(s, dev, "R4:Cmd (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2701+ dump_dma_rx_ring_info(s, dev, "R5:Data (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2702+ dump_dma_rx_ring_info(s, dev, "R6:TxDone/STS (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2703+ dump_dma_rx_ring_info(s, dev, "R7:RPT (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2704+ dump_dma_rx_ring_info(s, dev, "R8:TxDone/STS (MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2705+ dump_dma_rx_ring_info(s, dev, "R9:Data1 (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2706+
2707+}
2708+
2709+static void
2710+mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2711+{
2712+ u32 sys_ctrl[10] = {};
2713+
2714+ if(is_mt7915(&dev->mt76)) {
2715+ mt7915_show_host_dma_info(s, dev);
2716+ mt7915_show_mcu_dma_info(s, dev);
2717+ } else {
2718+ mt7986_show_host_dma_info(s, dev);
2719+ mt7986_show_mcu_dma_info(s, dev);
2720+ }
2721+
2722+ /* MEM DMA information */
2723+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
2724+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
2725+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
2726+
2727+ seq_printf(s, "MEM_DMA Configuration\n");
2728+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2729+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2730+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2731+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2732+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2733+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2734+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2735+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2736+
2737+ seq_printf(s, "MEM_DMA Ring Configuration\n");
2738+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2739+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2740+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
2741+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
2742+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
2743+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
2744+}
2745+
2746+static int mt7915_trinfo_read(struct seq_file *s, void *data)
2747+{
2748+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2749+ const struct hif_pci_tx_ring_desc *tx_ring_layout;
2750+ const struct hif_pci_rx_ring_desc *rx_ring_layout;
2751+ u32 tx_ring_num, rx_ring_num;
2752+ u32 tbase[5], tcnt[5];
2753+ u32 tcidx[5], tdidx[5];
2754+ u32 rbase[6], rcnt[6];
2755+ u32 rcidx[6], rdidx[6];
2756+ int idx;
2757+
2758+ if(is_mt7915(&dev->mt76)) {
2759+ tx_ring_layout = &mt7915_tx_ring_layout[0];
2760+ rx_ring_layout = &mt7915_rx_ring_layout[0];
2761+ tx_ring_num = ARRAY_SIZE(mt7915_tx_ring_layout);
2762+ rx_ring_num = ARRAY_SIZE(mt7915_rx_ring_layout);
2763+ } else {
2764+ tx_ring_layout = &mt7986_tx_ring_layout[0];
2765+ rx_ring_layout = &mt7986_rx_ring_layout[0];
2766+ tx_ring_num = ARRAY_SIZE(mt7986_tx_ring_layout);
2767+ rx_ring_num = ARRAY_SIZE(mt7986_rx_ring_layout);
2768+ }
2769+
2770+ for (idx = 0; idx < tx_ring_num; idx++) {
2771+ tbase[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx));
2772+ tcnt[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x04);
2773+ tcidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x08);
2774+ tdidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x0c);
2775+ }
2776+
2777+ for (idx = 0; idx < rx_ring_num; idx++) {
2778+ if (idx < 2) {
2779+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx));
2780+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x04);
2781+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x08);
2782+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x0c);
2783+ } else {
2784+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2));
2785+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x04);
2786+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x08);
2787+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x0c);
2788+ }
2789+ }
2790+
2791+ seq_printf(s, "=================================================\n");
2792+ seq_printf(s, "TxRing Configuration\n");
2793+ seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n",
2794+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2795+ "QCnt");
2796+ for (idx = 0; idx < tx_ring_num; idx++) {
2797+ u32 queue_cnt;
2798+
2799+ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
2800+ (tcidx[idx] - tdidx[idx]) :
2801+ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
2802+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2803+ idx, tx_ring_layout[idx].ring_info,
2804+ MT_DBG_TX_RING_CTRL(idx), tbase[idx],
2805+ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
2806+ }
2807+
2808+ seq_printf(s, "RxRing Configuration\n");
2809+ seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n",
2810+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2811+ "QCnt");
2812+
2813+ for (idx = 0; idx < rx_ring_num; idx++) {
2814+ u32 queue_cnt;
2815+
2816+ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
2817+ (rdidx[idx] - rcidx[idx] - 1) :
2818+ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
2819+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2820+ idx, rx_ring_layout[idx].ring_info,
2821+ (idx < 2) ? MT_DBG_RX_DATA_RING_CTRL(idx): MT_DBG_RX_EVENT_RING_CTRL(idx - 2),
2822+ rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
2823+ }
2824+
2825+ mt7915_show_dma_info(s, dev);
2826+ return 0;
2827+}
2828+
2829+static int mt7915_drr_info(struct seq_file *s, void *data)
2830+{
2831+#define DL_AC_START 0x00
2832+#define DL_AC_END 0x0F
2833+#define UL_AC_START 0x10
2834+#define UL_AC_END 0x1F
2835+
2836+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2837+ u32 drr_sta_status[16];
2838+ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
2839+ bool is_show = false;
2840+ int idx, sta_line = 0, sta_no = 0, max_sta_line = (mt7915_wtbl_size(dev) + 31) / 32;
2841+ seq_printf(s, "DRR Table STA Info:\n");
2842+
2843+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2844+ is_show = true;
2845+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2846+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2847+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2848+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2849+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2850+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2851+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2852+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2853+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2854+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2855+
2856+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2857+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2858+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2859+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2860+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2861+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2862+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2863+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2864+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2865+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2866+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2867+ }
2868+ if (!is_mt7915(&dev->mt76))
2869+ max_sta_line = 8;
2870+
2871+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2872+ if (drr_sta_status[sta_line] > 0) {
2873+ for (sta_no = 0; sta_no < 32; sta_no++) {
2874+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2875+ if (is_show) {
2876+ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
2877+ is_show = false;
2878+ }
2879+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2880+ }
2881+ }
2882+ }
2883+ }
2884+ }
2885+
2886+ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
2887+ is_show = true;
2888+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2889+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2890+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2891+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2892+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2893+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2894+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2895+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2896+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2897+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2898+
2899+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2900+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2901+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2902+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2903+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2904+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2905+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2906+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2907+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2908+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2909+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2910+ }
2911+
2912+ if (!is_mt7915(&dev->mt76))
2913+ max_sta_line = 8;
2914+
2915+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2916+ if (drr_sta_status[sta_line] > 0) {
2917+ for (sta_no = 0; sta_no < 32; sta_no++) {
2918+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2919+ if (is_show) {
2920+ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
2921+ is_show = false;
2922+ }
2923+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2924+ }
2925+ }
2926+ }
2927+ }
2928+ }
2929+
2930+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2931+ drr_ctrl_def_val = 0x80420000;
2932+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2933+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2934+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2935+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2936+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2937+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2938+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2939+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2940+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2941+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2942+
2943+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2944+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
2945+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2946+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2947+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2948+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2949+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2950+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2951+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2952+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2953+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2954+ }
2955+
2956+ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
2957+ if (!is_mt7915(&dev->mt76))
2958+ max_sta_line = 8;
2959+
2960+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2961+ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
2962+
2963+ if ((sta_line % 4) == 3)
2964+ seq_printf(s, "\n");
2965+ }
2966+ }
2967+
2968+ return 0;
2969+}
2970+
developerf32dabf2022-06-01 10:59:24 +08002971+#define CR_NUM_OF_AC 17
developer3fa816c2022-04-19 10:21:20 +08002972+
2973+typedef enum _ENUM_UMAC_PORT_T {
2974+ ENUM_UMAC_HIF_PORT_0 = 0,
2975+ ENUM_UMAC_CPU_PORT_1 = 1,
2976+ ENUM_UMAC_LMAC_PORT_2 = 2,
2977+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
2978+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
2979+} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
2980+
2981+/* N9 MCU QUEUE LIST */
2982+typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
2983+ ENUM_UMAC_CTX_Q_0 = 0,
2984+ ENUM_UMAC_CTX_Q_1 = 1,
2985+ ENUM_UMAC_CTX_Q_2 = 2,
2986+ ENUM_UMAC_CTX_Q_3 = 3,
2987+ ENUM_UMAC_CRX = 0,
2988+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
2989+} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
2990+
2991+/* LMAC PLE TX QUEUE LIST */
2992+typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
2993+ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
2994+ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
2995+ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
2996+ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
2997+
2998+ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
2999+ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
3000+ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
3001+ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
3002+
3003+ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
3004+ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
3005+ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
3006+ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
3007+
3008+ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
3009+ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
3010+ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
3011+ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
3012+
3013+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
3014+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
3015+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
3016+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
3017+
3018+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
3019+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
3020+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
3021+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
3022+ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
3023+ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
3024+ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
3025+ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
3026+
3027+} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
3028+
3029+typedef struct _EMPTY_QUEUE_INFO_T {
3030+ char *QueueName;
3031+ u32 Portid;
3032+ u32 Queueid;
3033+} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
3034+
3035+static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
3036+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3037+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3038+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3039+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3040+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3041+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
3042+ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
3043+ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
3044+ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
3045+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
3046+ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
3047+ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
3048+ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
3049+ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
3050+ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
3051+ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
3052+ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
3053+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3054+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
3055+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
3056+ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
3057+};
3058+
3059+static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
3060+ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
3061+ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
3062+ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
3063+ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
3064+ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
3065+ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
3066+ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
3067+ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
3068+ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
3069+ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
3070+ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
3071+ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
3072+ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
3073+ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
3074+ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
3075+ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
3076+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
3077+ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
3078+ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
3079+ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
3080+ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
3081+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
3082+ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
3083+ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
3084+ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
3085+ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
3086+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3087+};
3088+
3089+
3090+
3091+static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
3092+static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
3093+ u32 *sta_pause, u32 *dis_sta_map,
3094+ u32 dumptxd)
3095+{
3096+ int i, j;
3097+ u32 total_nonempty_cnt = 0;
3098+ u32 ac_num = 9, all_ac_num;
3099+
3100+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003101+ if (!is_mt7915(&dev->mt76))
3102+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003103+
3104+ all_ac_num = ac_num * 4;
3105+
3106+ for (j = 0; j < all_ac_num; j++) { /* show AC Q info */
3107+ for (i = 0; i < 32; i++) {
3108+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
developerf32dabf2022-06-01 10:59:24 +08003109+ u32 hfid, tfid, pktcnt, ac_n = j / ac_num, ctrl = 0;
developer3fa816c2022-04-19 10:21:20 +08003110+ u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0};
3111+ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
3112+ u32 wmmidx = 0;
3113+ struct mt7915_sta *msta;
3114+ struct mt76_wcid *wcid;
3115+ struct ieee80211_sta *sta = NULL;
3116+
3117+ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
3118+ sta = wcid_to_sta(wcid);
3119+ if (!sta) {
3120+ printk("ERROR!! no found STA wcid=%d\n", sta_num);
developerf32dabf2022-06-01 10:59:24 +08003121+ continue;
developer3fa816c2022-04-19 10:21:20 +08003122+ }
3123+ msta = container_of(wcid, struct mt7915_sta, wcid);
3124+ wmmidx = msta->vif->mt76.wmm_idx;
3125+
developerf32dabf2022-06-01 10:59:24 +08003126+ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_n);
developer3fa816c2022-04-19 10:21:20 +08003127+
3128+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3129+ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
developerf32dabf2022-06-01 10:59:24 +08003130+ fl_que_ctrl[0] |= (ac_n << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
developer3fa816c2022-04-19 10:21:20 +08003131+ fl_que_ctrl[0] |= sta_num;
3132+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3133+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3134+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3135+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3136+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3137+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3138+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
3139+ tfid, hfid, pktcnt);
3140+
3141+ if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1)
3142+ ctrl = 2;
3143+
3144+ if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1)
3145+ ctrl = 1;
3146+
3147+ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
3148+ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
3149+
3150+ total_nonempty_cnt++;
3151+
3152+ // TODO
3153+ //if (pktcnt > 0 && dumptxd > 0)
3154+ // ShowTXDInfo(pAd, hfid);
3155+ }
3156+ }
3157+ }
3158+
3159+ return total_nonempty_cnt;
3160+}
3161+
3162+static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
3163+{
3164+ int i;
3165+
3166+ seq_printf(s, "Nonempty TXCMD Q info:\n");
developerf32dabf2022-06-01 10:59:24 +08003167+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003168+ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
3169+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3170+
3171+ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
3172+ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
3173+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3174+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
3175+ MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3176+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
3177+ MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3178+ } else
3179+ continue;
3180+
3181+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3182+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3183+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3184+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3185+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3186+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3187+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3188+ tfid, hfid, pktcnt);
3189+ }
3190+ }
3191+}
3192+
3193+static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
3194+{
3195+ int i;
3196+ int cr_num = 9, all_cr_num;
3197+ u32 ac , index;
3198+
3199+ /* TDO: cr_num = 16 for mt7986 */
developer3fa816c2022-04-19 10:21:20 +08003200+ if(!is_mt7915(&dev->mt76))
developerf32dabf2022-06-01 10:59:24 +08003201+ cr_num = 17;
3202+
developer3fa816c2022-04-19 10:21:20 +08003203+ all_cr_num = cr_num * 4;
3204+
3205+ ple_stat[0] = mt76_rr(dev, MT_DBG_PLE_QUEUE_EMPTY);
3206+
3207+ for(i = 0; i < all_cr_num; i++) {
3208+ ac = i / cr_num;
3209+ index = i % cr_num;
3210+ ple_stat[i + 1] =
3211+ mt76_rr(dev, MT_DBG_PLE_AC_QEMPTY(ac, index));
3212+
3213+ }
3214+}
3215+
3216+static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
3217+{
3218+ int i;
developerf32dabf2022-06-01 10:59:24 +08003219+ u32 ac_num = 9;
3220+
3221+ /* TDO: ac_num = 16 for mt7986 */
3222+ if (!is_mt7915(&dev->mt76))
3223+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003224+
developerf32dabf2022-06-01 10:59:24 +08003225+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003226+ dis_sta_map[i] = mt76_rr(dev, MT_DBG_PLE_DIS_STA_MAP(i));
3227+ }
3228+}
3229+
3230+static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
3231+{
3232+ int i;
developerf32dabf2022-06-01 10:59:24 +08003233+ u32 ac_num = 9;
developer3fa816c2022-04-19 10:21:20 +08003234+
developerf32dabf2022-06-01 10:59:24 +08003235+ /* TDO: ac_num = 16 for mt7986 */
3236+ if (!is_mt7915(&dev->mt76))
3237+ ac_num = 17;
3238+
3239+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003240+ sta_pause[i] = mt76_rr(dev, MT_DBG_PLE_STATION_PAUSE(i));
3241+ }
3242+}
3243+
3244+static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3245+{
3246+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3247+ u32 ple_buf_ctrl, pg_sz, pg_num;
developerf32dabf2022-06-01 10:59:24 +08003248+ u32 ple_stat[70] = {0}, pg_flow_ctrl[8] = {0};
developer3fa816c2022-04-19 10:21:20 +08003249+ u32 ple_native_txcmd_stat;
3250+ u32 ple_txcmd_stat;
3251+ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
3252+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
3253+ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
3254+ int i, j;
3255+ u32 ac_num = 9, all_ac_num;
3256+
3257+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003258+ if (!is_mt7915(&dev->mt76))
3259+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003260+
3261+ all_ac_num = ac_num * 4;
3262+
3263+ ple_buf_ctrl = mt76_rr(dev, MT_DBG_PLE_PBUF_CTRL_ADDR);
3264+ chip_get_ple_acq_stat(dev, ple_stat);
3265+ ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY);
3266+ ple_native_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY);
3267+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT);
3268+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL);
3269+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP);
3270+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO);
3271+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP);
3272+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO);
3273+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP);
3274+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO);
3275+ chip_get_dis_sta_map(dev, dis_sta_map);
3276+ chip_get_sta_pause(dev, sta_pause);
3277+
3278+ seq_printf(s, "PLE Configuration Info:\n");
3279+ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
3280+ MT_DBG_PLE_PBUF_CTRL_ADDR, ple_buf_ctrl);
3281+
3282+ pg_sz = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK, ple_buf_ctrl);
3283+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
3284+ pg_sz, (pg_sz == 1 ? 128 : 64));
3285+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 2KB)\n",
3286+ FIELD_GET(MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK, ple_buf_ctrl));
3287+
3288+ pg_num = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, ple_buf_ctrl);
3289+ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
3290+
3291+ /* Page Flow Control */
3292+ seq_printf(s, "PLE Page Flow Control:\n");
3293+ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
3294+ MT_DBG_PLE_FREEPG_CNT, pg_flow_ctrl[0]);
3295+ fpg_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3296+
3297+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3298+ ffa_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3299+
3300+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3301+ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
3302+ MT_DBG_PLE_FREEPG_HEAD_TAIL, pg_flow_ctrl[1]);
3303+
3304+ fpg_head = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3305+ fpg_tail = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3306+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3307+ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
3308+ MT_DBG_PLE_PG_HIF_GROUP, pg_flow_ctrl[2]);
3309+ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
3310+ MT_DBG_PLE_HIF_PG_INFO, pg_flow_ctrl[3]);
3311+
3312+ hif_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3313+ hif_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3314+ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
3315+
3316+ rpg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK, pg_flow_ctrl[3]);
3317+ upg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK, pg_flow_ctrl[3]);
3318+ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
3319+
3320+ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
3321+ MT_DBG_PLE_PG_HIF_TXCMD_GROUP, pg_flow_ctrl[6]);
3322+ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
3323+ MT_DBG_PLE_HIF_TXCMD_PG_INFO, pg_flow_ctrl[7]);
3324+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
developerf32dabf2022-06-01 10:59:24 +08003325+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
developer3fa816c2022-04-19 10:21:20 +08003326+ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3327+
3328+ rpg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK, pg_flow_ctrl[7]);
3329+ upg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK, pg_flow_ctrl[7]);
3330+ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3331+
developerf32dabf2022-06-01 10:59:24 +08003332+ seq_printf(s, "\tReserved page counter of CPU group(0x%x): 0x%08x\n",
3333+ MT_DBG_PLE_PG_CPU_GROUP, pg_flow_ctrl[4]);
3334+ seq_printf(s, "\tCPU group page status(0x%x): 0x%08x\n",
3335+ MT_DBG_PLE_CPU_PG_INFO, pg_flow_ctrl[5]);
developer3fa816c2022-04-19 10:21:20 +08003336+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3337+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3338+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3339+
3340+ rpg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[5]);
3341+ upg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[5]);
3342+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3343+
3344+ if ((ple_stat[0] & MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
3345+ for (j = 0; j < all_ac_num; j++) {
3346+ if (j % ac_num == 0) {
3347+ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / ac_num);
3348+ }
3349+
developerf32dabf2022-06-01 10:59:24 +08003350+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003351+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3352+ seq_printf(s, "%d ", i + (j % ac_num) * 32);
3353+ }
3354+ }
3355+ }
3356+
3357+ seq_printf(s, "\n");
3358+ }
3359+
3360+ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
3361+
3362+ seq_printf(s, "Nonempty Q info:\n");
3363+
developerf32dabf2022-06-01 10:59:24 +08003364+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003365+ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
3366+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3367+
3368+ if (ple_queue_empty_info[i].QueueName != NULL) {
3369+ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
3370+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3371+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3372+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3373+ } else
3374+ continue;
3375+
3376+ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
3377+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
3378+ /* band0 set TGID 0, bit31 = 0 */
3379+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0);
3380+ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
3381+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
3382+ /* band1 set TGID 1, bit31 = 1 */
3383+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000);
3384+
3385+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3386+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3387+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3388+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3389+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3390+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3391+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3392+ tfid, hfid, pktcnt);
3393+
3394+ /* TODO */
3395+ //if (pktcnt > 0 && dumptxd > 0)
3396+ // ShowTXDInfo(pAd, hfid);
3397+ }
3398+ }
3399+
3400+ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
3401+ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
3402+
3403+ return 0;
3404+}
3405+
3406+typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3407+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3408+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3409+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3410+} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3411+
3412+static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3413+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3414+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3415+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3416+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3417+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3418+ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3419+ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3420+ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3421+ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3422+ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3423+ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3424+ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3425+ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3426+ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3427+ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3428+ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3429+ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3430+ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3431+ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3432+ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3433+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3434+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3435+};
3436+
3437+static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3438+{
3439+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3440+ u32 pse_buf_ctrl, pg_sz, pg_num;
3441+ u32 pse_stat, pg_flow_ctrl[22] = {0};
3442+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3443+ u32 max_q, min_q, rsv_pg, used_pg;
3444+ int i;
3445+
3446+ pse_buf_ctrl = mt76_rr(dev, MT_DBG_PSE_PBUF_CTRL);
3447+ pse_stat = mt76_rr(dev, MT_DBG_PSE_QUEUE_EMPTY);
3448+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PSE_FREEPG_CNT);
3449+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FREEPG_HEAD_TAIL);
3450+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_PG_HIF0_GROUP);
3451+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PSE_HIF0_PG_INFO);
3452+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PSE_PG_HIF1_GROUP);
3453+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PSE_HIF1_PG_INFO);
3454+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PSE_PG_CPU_GROUP);
3455+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PSE_CPU_PG_INFO);
3456+ pg_flow_ctrl[8] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC0_GROUP);
3457+ pg_flow_ctrl[9] = mt76_rr(dev, MT_DBG_PSE_LMAC0_PG_INFO);
3458+ pg_flow_ctrl[10] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC1_GROUP);
3459+ pg_flow_ctrl[11] = mt76_rr(dev, MT_DBG_PSE_LMAC1_PG_INFO);
3460+ pg_flow_ctrl[12] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC2_GROUP);
3461+ pg_flow_ctrl[13] = mt76_rr(dev, MT_DBG_PSE_LMAC2_PG_INFO);
3462+ pg_flow_ctrl[14] = mt76_rr(dev, MT_DBG_PSE_PG_PLE_GROUP);
3463+ pg_flow_ctrl[15] = mt76_rr(dev, MT_DBG_PSE_PLE_PG_INFO);
3464+ pg_flow_ctrl[16] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC3_GROUP);
3465+ pg_flow_ctrl[17] = mt76_rr(dev, MT_DBG_PSE_LMAC3_PG_INFO);
3466+ pg_flow_ctrl[18] = mt76_rr(dev, MT_DBG_PSE_PG_MDP_GROUP);
3467+ pg_flow_ctrl[19] = mt76_rr(dev, MT_DBG_PSE_MDP_PG_INFO);
3468+ pg_flow_ctrl[20] = mt76_rr(dev, MT_DBG_PSE_PG_PLE1_GROUP);
3469+ pg_flow_ctrl[21] = mt76_rr(dev,MT_DBG_PSE_PLE1_PG_INFO);
3470+
3471+ /* Configuration Info */
3472+ seq_printf(s, "PSE Configuration Info:\n");
3473+ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3474+ pg_sz = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK, pse_buf_ctrl);
3475+
3476+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3477+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 64KB)\n",
3478+ FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK, pse_buf_ctrl));
3479+ pg_num = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, pse_buf_ctrl);
3480+
3481+ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3482+
3483+ /* Page Flow Control */
3484+ seq_printf(s, "PSE Page Flow Control:\n");
3485+ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3486+ fpg_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3487+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3488+
3489+ ffa_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3490+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3491+
3492+ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3493+ fpg_head = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3494+
3495+ fpg_tail = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3496+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3497+ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3498+ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3499+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3500+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3501+ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3502+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK, pg_flow_ctrl[3]);;
3503+ used_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK, pg_flow_ctrl[3]);
3504+ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3505+ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3506+ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3507+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3508+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3509+ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3510+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK, pg_flow_ctrl[5]);
3511+ used_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK, pg_flow_ctrl[5]);
3512+
3513+ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3514+ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3515+ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3516+ min_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3517+ max_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
3518+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3519+ rsv_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[7]);
3520+ used_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[7]);
3521+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3522+ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3523+ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3524+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK, pg_flow_ctrl[8]);
3525+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK, pg_flow_ctrl[8]);
3526+ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3527+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK, pg_flow_ctrl[9]);
3528+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK, pg_flow_ctrl[9]);
3529+ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3530+ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3531+ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3532+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK, pg_flow_ctrl[10]);
3533+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK, pg_flow_ctrl[10]);
3534+ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3535+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK, pg_flow_ctrl[11]);
3536+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK, pg_flow_ctrl[11]);
3537+ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3538+ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3539+ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3540+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK, pg_flow_ctrl[12]);
3541+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK, pg_flow_ctrl[12]);
3542+ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3543+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK, pg_flow_ctrl[13]);
3544+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK, pg_flow_ctrl[13]);
3545+ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3546+
3547+ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3548+ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3549+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK, pg_flow_ctrl[16]);
3550+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK, pg_flow_ctrl[16]);
3551+ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3552+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK, pg_flow_ctrl[17]);
3553+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK, pg_flow_ctrl[17]);
3554+ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3555+
3556+ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3557+ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3558+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[14]);
3559+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[14]);
3560+ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3561+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[15]);
3562+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[15]);
3563+ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3564+
3565+ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3566+ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3567+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[20]);
3568+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[20]);
3569+ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3570+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[21]);
3571+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[21]);
3572+ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3573+
3574+ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3575+ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3576+ min_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK, pg_flow_ctrl[18]);
3577+ max_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK, pg_flow_ctrl[18]);
3578+ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3579+ rsv_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK, pg_flow_ctrl[19]);
3580+ used_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK, pg_flow_ctrl[19]);
3581+ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3582+
3583+ /* Queue Empty Status */
3584+ seq_printf(s, "PSE Queue Empty Status:\n");
3585+ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3586+ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%ld/%ld/%ld/%ld\n",
3587+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK, pse_stat),
3588+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK, pse_stat),
3589+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK, pse_stat),
3590+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK, pse_stat));
3591+
3592+ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%ld/%ld/%ld/%ld/%ld/%ld\n",
3593+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK, pse_stat),
3594+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK, pse_stat),
3595+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK, pse_stat),
3596+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK, pse_stat),
3597+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK, pse_stat),
3598+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK, pse_stat));
3599+
3600+ seq_printf(s, "\t\tLMAC TX Q empty=%ld\n",
3601+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK, pse_stat));
3602+ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%ld/%ld\n",
3603+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK, pse_stat),
3604+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK, pse_stat));
3605+ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%ld/%ld\n",
3606+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK, pse_stat),
3607+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT, pse_stat));
3608+ seq_printf(s, "\t\tSFD PARK Q empty=%ld\n",
3609+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK, pse_stat));
3610+ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%ld/%ld\n",
3611+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK, pse_stat),
3612+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK, pse_stat));
3613+ seq_printf(s, "\t\tRLS Q empty=%ld\n",
3614+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK, pse_stat));
3615+ seq_printf(s, "Nonempty Q info:\n");
3616+
3617+ for (i = 0; i < 31; i++) {
3618+ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3619+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3620+
3621+ if (pse_queue_empty_info[i].QueueName != NULL) {
3622+ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3623+ fl_que_ctrl[0] |= MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK;
3624+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3625+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3626+ } else
3627+ continue;
3628+
3629+ fl_que_ctrl[0] |= (0x1 << 31);
3630+
3631+ mt76_wr(dev, MT_DBG_PSE_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3632+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_2_ADDR);
3633+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_3_ADDR);
3634+
3635+ hfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK, fl_que_ctrl[1]);
3636+ tfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK, fl_que_ctrl[1]);
3637+ pktcnt = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK, fl_que_ctrl[2]);
3638+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3639+ tfid, hfid, pktcnt);
3640+ }
3641+ }
3642+
3643+ return 0;
3644+}
3645+
3646+static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3647+{
3648+#define BSS_NUM 4
3649+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3650+ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
3651+ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
3652+ u32 mbxsdr[BSS_NUM][7];
3653+ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
3654+ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
3655+ u32 mu_cnt[5];
3656+ u32 ampdu_cnt[3];
3657+ unsigned long per;
3658+
3659+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3660+ seq_printf(s, "===============================\n");
3661+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SCR0(band_idx));
3662+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3663+ if (is_mt7915(&dev->mt76)) {
3664+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0PBSCR(band_idx));
3665+ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
3666+ }
3667+
3668+ msdr6 = mt76_rr(dev, MT_DBG_MIB_M0SDR6(band_idx));
3669+ msdr7 = mt76_rr(dev, MT_DBG_MIB_M0SDR7(band_idx));
3670+ msdr8 = mt76_rr(dev, MT_DBG_MIB_M0SDR8(band_idx));
3671+ msdr9 = mt76_rr(dev, MT_DBG_MIB_M0SDR9(band_idx));
3672+ msdr10 = mt76_rr(dev, MT_DBG_MIB_M0SDR10(band_idx));
3673+ msdr16 = mt76_rr(dev, MT_DBG_MIB_M0SDR16(band_idx));
3674+ msdr17 = mt76_rr(dev, MT_DBG_MIB_M0SDR17(band_idx));
3675+ msdr18 = mt76_rr(dev, MT_DBG_MIB_M0SDR18(band_idx));
3676+ msdr19 = mt76_rr(dev, MT_DBG_MIB_M0SDR19(band_idx));
3677+ msdr20 = mt76_rr(dev, MT_DBG_MIB_M0SDR20(band_idx));
3678+ msdr21 = mt76_rr(dev, MT_DBG_MIB_M0SDR21(band_idx));
3679+ ampdu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_M0SDR12(band_idx));
3680+ ampdu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0SDR14(band_idx));
3681+ ampdu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0SDR15(band_idx));
3682+ ampdu_cnt[1] &= MT_DBG_MIB_M0SDR14_AMPDU_MASK;
3683+ ampdu_cnt[2] &= MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK;
3684+
3685+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3686+ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3687+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3688+ seq_printf(s, "\tRx_MDRDY_CNT=0x%lx\n", msdr10 & MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK);
3689+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
3690+ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
3691+ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
3692+ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
3693+ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
3694+ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
3695+ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3696+
3697+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3698+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR0(band_idx));
3699+ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
3700+ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
3701+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3702+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR0(band_idx));
3703+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
3704+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
3705+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR1(band_idx));
3706+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
3707+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
3708+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3709+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3710+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3711+ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3712+ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
3713+
3714+ seq_printf(s, "===MU Related Counters===\n");
3715+ mu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_MUBF(band_idx));
3716+ mu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0DR8(band_idx));
3717+ mu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0DR9(band_idx));
3718+ mu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR10(band_idx));
3719+ mu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3720+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
3721+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3722+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3723+ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
3724+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3725+
3726+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3727+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
3728+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
3729+
3730+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR3(band_idx));
3731+ seq_printf(s, "\tRxFCSErrCnt=0x%lx\n", __DBG_FIELD_GET(DBG_MIB_RX_FCS_ERROR_COUNT, mac_val));
3732+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR4(band_idx));
3733+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
3734+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR11(band_idx));
3735+ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
3736+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR5(band_idx));
3737+ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
3738+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR22(band_idx));
3739+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3740+ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
3741+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR23(band_idx));
3742+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3743+
3744+ if (is_mt7915(&dev->mt76)) {
3745+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;//check
3746+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3747+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3748+
3749+ for (idx = 0; idx < BSS_NUM; idx++) {
3750+ btcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
3751+ btbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
3752+ brcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
3753+ brbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
3754+ btdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
3755+ brdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
3756+ }
3757+
3758+ for (idx = 0; idx < BSS_NUM; idx++) {
3759+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3760+ idx, btcr[idx], btdcr[idx], btbcr[idx],
3761+ brcr[idx], brdcr[idx], brbcr[idx]);
3762+ }
3763+
3764+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3765+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3766+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3767+
3768+ for (idx = 0; idx < BSS_NUM; idx++) {
3769+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
3770+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
3771+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
3772+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
3773+ }
3774+
3775+ for (idx = 0; idx < BSS_NUM; idx++) {
3776+ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
3777+ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
3778+ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
3779+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
3780+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
3781+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
3782+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
3783+ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
3784+ }
3785+
3786+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
3787+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3788+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3789+
3790+ for (idx = 0; idx < 16; idx++) {
3791+ mbtcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
3792+ mbtbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
3793+ mbrcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
3794+ mbrbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
3795+ }
3796+
3797+ for (idx = 0; idx < 16; idx++) {
3798+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3799+ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
3800+ }
3801+ return 0;
3802+ } else {
3803+ u32 btocr[BSS_NUM], mbtocr[16],mbrocr[16], brocr[BSS_NUM];
3804+ u8 bss_nums = BSS_NUM;
3805+
3806+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3807+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3808+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3809+
3810+ for (idx = 0; idx < BSS_NUM; idx++) {
3811+ btocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (idx >> 1) * 4));
3812+ btdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + (idx >> 1) * 4));
3813+ btbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (idx * 4)));
3814+ brocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (idx >> 1) * 4));
3815+ brdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRDCR_ADDR + band_offset + (idx >> 1) * 4));
3816+ brbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (idx * 4)));
3817+
3818+ if ((idx % 2) == 0) {
3819+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3820+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT);
3821+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3822+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT);
3823+ } else {
3824+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3825+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT);
3826+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3827+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT);
3828+ }
3829+ }
3830+
3831+ for (idx = 0; idx < BSS_NUM; idx++) {
3832+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3833+ idx, btocr[idx], btdcr[idx], btbcr[idx], brocr[idx], brdcr[idx], brbcr[idx]);
3834+ }
3835+
3836+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3837+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3838+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3839+
3840+ for (idx = 0; idx < BSS_NUM; idx++) {
3841+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR0_ADDR + band_offset + ((idx >> 1) * 4));
3842+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR1_ADDR + band_offset + ((idx >> 1) * 4));
3843+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR2_ADDR + band_offset + ((idx >> 1) * 4));
3844+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR3_ADDR + band_offset + ((idx >> 1) * 4));
3845+ mbxsdr[idx][4] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR4_ADDR + band_offset + ((idx >> 1) * 4));
3846+ mbxsdr[idx][5] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR5_ADDR + band_offset + ((idx >> 1) * 4));
3847+ mbxsdr[idx][6] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR6_ADDR + band_offset + ((idx >> 1) * 4));
3848+
3849+ if ((idx % 2) == 0) {
3850+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT);
3851+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT);
3852+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT);
3853+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT);
3854+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT);
3855+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT);
3856+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT);
3857+ } else {
3858+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT);
3859+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT);
3860+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT);
3861+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT);
3862+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT);
3863+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT);
3864+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT);
3865+ }
3866+ }
3867+
3868+ for (idx = 0; idx < BSS_NUM; idx++) {
3869+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3870+ idx,
3871+ mbxsdr[idx][0], mbxsdr[idx][1], mbxsdr[idx][2], mbxsdr[idx][3],
3872+ mbxsdr[idx][4], mbxsdr[idx][5], mbxsdr[idx][6]);
3873+ }
3874+
3875+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3876+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3877+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3878+
3879+ for (idx = 0; idx < 16; idx++) {
3880+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3881+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3882+ mbrocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3883+ mbrbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3884+
3885+ if ((idx % 2) == 0) {
3886+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3887+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3888+ } else {
3889+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3890+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3891+ }
3892+ }
3893+
3894+ for (idx = 0; idx < 16; idx++) {
3895+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3896+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3897+ }
3898+ }
3899+
3900+ seq_printf(s, "===Dummy delimiter insertion result===\n");
3901+ mac_val0 = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3902+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR6(band_idx));
3903+ mac_val1 = mt76_rr(dev, MT_DBG_MIB_M0DR7(band_idx));
3904+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3905+ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
3906+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
3907+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
3908+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
3909+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
3910+
3911+ return 0;
3912+}
3913+
3914+static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
3915+{
3916+ mt7915_mibinfo_read_per_band(s, 0);
3917+ return 0;
3918+}
3919+
3920+static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
3921+{
3922+ mt7915_mibinfo_read_per_band(s, 1);
3923+ return 0;
3924+}
3925+
3926+static int mt7915_token_read(struct seq_file *s, void *data)
3927+{
3928+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3929+ int id, count = 0;
3930+ struct mt76_txwi_cache *txwi;
3931+
3932+ seq_printf(s, "Cut through token:\n");
3933+ spin_lock_bh(&dev->mt76.token_lock);
3934+ idr_for_each_entry(&dev->mt76.token, txwi, id) {
3935+ seq_printf(s, "%4d ", id);
3936+ count++;
3937+ if (count % 8 == 0)
3938+ seq_printf(s, "\n");
3939+ }
3940+ spin_unlock_bh(&dev->mt76.token_lock);
3941+ seq_printf(s, "\n");
3942+
3943+ return 0;
3944+}
3945+
3946+struct txd_l {
3947+ u32 txd_0;
3948+ u32 txd_1;
3949+ u32 txd_2;
3950+ u32 txd_3;
3951+ u32 txd_4;
3952+ u32 txd_5;
3953+ u32 txd_6;
3954+ u32 txd_7;
3955+} __packed;
3956+
3957+char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
3958+char *hdr_fmt_str[] = {
3959+ "Non-80211-Frame",
3960+ "Command-Frame",
3961+ "Normal-80211-Frame",
3962+ "enhanced-80211-Frame",
3963+};
3964+/* TMAC_TXD_1.hdr_format */
3965+#define TMI_HDR_FT_NON_80211 0x0
3966+#define TMI_HDR_FT_CMD 0x1
3967+#define TMI_HDR_FT_NOR_80211 0x2
3968+#define TMI_HDR_FT_ENH_80211 0x3
3969+
3970+void mt7915_dump_tmac_info(u8 *tmac_info)
3971+{
3972+ struct txd_l *txd = (struct txd_l *)tmac_info;
3973+
3974+ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
3975+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
3976+
3977+ printk("TMAC_TXD Fields:\n");
3978+ printk("\tTMAC_TXD_0:\n");
3979+
3980+ /* DW0 */
3981+ /* TX Byte Count [15:0] */
3982+ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
3983+
3984+ /* PKT_FT: Packet Format [24:23] */
3985+ printk("\t\tpkt_ft = %ld(%s)\n",
3986+ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
3987+ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
3988+
3989+ /* Q_IDX [31:25] */
3990+ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
3991+
3992+ printk("\tTMAC_TXD_1:\n");
3993+
3994+ /* DW1 */
3995+ /* WLAN Indec [9:0] */
3996+ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
3997+
3998+ /* VTA [10] */
3999+ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
4000+
4001+ /* HF: Header Format [17:16] */
4002+ printk("\t\tHdrFmt = %ld(%s)\n",
4003+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
4004+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
4005+ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
4006+
4007+ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
4008+ case TMI_HDR_FT_NON_80211:
4009+ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
4010+ printk("\t\t\tMRD = %d, EOSP = %d,\
4011+ RMVL = %d, VLAN = %d, ETYP = %d\n",
4012+ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
4013+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4014+ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
4015+ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
4016+ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
4017+ break;
4018+ case TMI_HDR_FT_NOR_80211:
4019+ /* HEADER_LENGTH [15:11] */
4020+ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
4021+ break;
4022+
4023+ case TMI_HDR_FT_ENH_80211:
4024+ /* EOSP [12], AMS [13] */
4025+ printk("\t\t\tEOSP = %d, AMS = %d\n",
4026+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4027+ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
4028+ break;
4029+ }
4030+
4031+ /* Header Padding [19:18] */
4032+ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
4033+
4034+ /* TID [22:20] */
4035+ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
4036+
4037+
4038+ /* UtxB/AMSDU_C/AMSDU [23] */
4039+ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
4040+
4041+ /* OM [29:24] */
4042+ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
4043+
4044+
4045+ /* TGID [30] */
4046+ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
4047+
4048+
4049+ /* FT [31] */
4050+ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
4051+
4052+ printk("\tTMAC_TXD_2:\n");
4053+ /* DW2 */
4054+ /* Subtype [3:0] */
4055+ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
4056+
4057+ /* Type[5:4] */
4058+ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
4059+
4060+ /* NDP [6] */
4061+ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
4062+
4063+ /* NDPA [7] */
4064+ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
4065+
4066+ /* SD [8] */
4067+ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
4068+
4069+ /* RTS [9] */
4070+ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
4071+
4072+ /* BM [10] */
4073+ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
4074+
4075+ /* B [11] */
4076+ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
4077+
4078+ /* DU [12] */
4079+ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
4080+
4081+ /* HE [13] */
4082+ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
4083+
4084+ /* FRAG [15:14] */
4085+ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
4086+
4087+
4088+ /* Remaining Life Time [23:16]*/
4089+ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
4090+ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
4091+
4092+ /* Power Offset [29:24] */
4093+ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
4094+
4095+ /* FRM [30] */
4096+ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
4097+
4098+ /* FR[31] */
4099+ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
4100+
4101+
4102+ printk("\tTMAC_TXD_3:\n");
4103+
4104+ /* DW3 */
4105+ /* NA [0] */
4106+ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
4107+
4108+ /* PF [1] */
4109+ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
4110+
4111+ /* EMRD [2] */
4112+ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
4113+
4114+ /* EEOSP [3] */
4115+ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
4116+
4117+ /* DAS [4] */
4118+ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
4119+
4120+ /* TM [5] */
4121+ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
4122+
4123+ /* TX Count [10:6] */
4124+ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
4125+
4126+ /* Remaining TX Count [15:11] */
4127+ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
4128+
4129+ /* SN [27:16] */
4130+ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
4131+
4132+ /* BA_DIS [28] */
4133+ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
4134+
4135+ /* Power Management [29] */
4136+ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
4137+
4138+ /* PN_VLD [30] */
4139+ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
4140+
4141+ /* SN_VLD [31] */
4142+ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
4143+
4144+
4145+ /* DW4 */
4146+ printk("\tTMAC_TXD_4:\n");
4147+
4148+ /* PN_LOW [31:0] */
4149+ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
4150+
4151+
4152+ /* DW5 */
4153+ printk("\tTMAC_TXD_5:\n");
4154+
4155+ /* PID [7:0] */
4156+ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
4157+
4158+ /* TXSFM [8] */
4159+ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
4160+
4161+ /* TXS2M [9] */
4162+ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
4163+
4164+ /* TXS2H [10] */
4165+ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
4166+
4167+ /* ADD_BA [14] */
4168+ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
4169+
4170+ /* MD [15] */
4171+ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
4172+
4173+ /* PN_HIGH [31:16] */
4174+ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
4175+
4176+ /* DW6 */
4177+ printk("\tTMAC_TXD_6:\n");
4178+
4179+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4180+ /* Fixed BandWidth mode [2:0] */
4181+ printk("\t\tbw = %ld\n", FIELD_GET(MT_TXD6_BW, txd->txd_6));
4182+
4183+ /* DYN_BW [3] */
4184+ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
4185+
4186+ /* ANT_ID [7:4] */
4187+ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
4188+
4189+ /* SPE_IDX_SEL [10] */
4190+ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
4191+
4192+ /* LDPC [11] */
4193+ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
4194+
4195+ /* HELTF Type[13:12] */
4196+ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
4197+
4198+ /* GI Type [15:14] */
4199+ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
4200+
4201+ /* Rate to be Fixed [29:16] */
4202+ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4203+ }
4204+
4205+ /* TXEBF [30] */
4206+ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4207+
4208+ /* TXIBF [31] */
4209+ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4210+
4211+ /* DW7 */
4212+ printk("\tTMAC_TXD_7:\n");
4213+
4214+ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4215+ /* SW Tx Time [9:0] */
4216+ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4217+ } else {
4218+ /* TXD Arrival Time [9:0] */
4219+ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4220+ }
4221+
4222+ /* HW_AMSDU_CAP [10] */
4223+ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4224+
4225+ /* SPE_IDX [15:11] */
4226+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4227+ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4228+ }
4229+
4230+ /* PSE_FID [27:16] */
4231+ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4232+
4233+ /* Subtype [19:16] */
4234+ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4235+
4236+ /* Type [21:20] */
4237+ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4238+
4239+ /* CTXD_CNT [25:23] */
4240+ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4241+
4242+ /* CTXD [26] */
4243+ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4244+
4245+ /* I [28] */
4246+ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4247+
4248+ /* UT [29] */
4249+ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4250+
4251+ /* TXDLEN [31:30] */
4252+ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4253+}
4254+
4255+
4256+static int mt7915_token_txd_read(struct seq_file *s, void *data)
4257+{
4258+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4259+ struct mt76_txwi_cache *t;
4260+ u8* txwi;
4261+
4262+ seq_printf(s, "\n");
4263+ spin_lock_bh(&dev->mt76.token_lock);
4264+
4265+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4266+
4267+ spin_unlock_bh(&dev->mt76.token_lock);
4268+ if (t != NULL) {
4269+ struct mt76_dev *mdev = &dev->mt76;
4270+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4271+ mt7915_dump_tmac_info((u8*) txwi);
4272+ seq_printf(s, "\n");
4273+ printk("[SKB]\n");
4274+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4275+ seq_printf(s, "\n");
4276+ }
4277+ return 0;
4278+}
4279+
4280+static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
4281+{
4282+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4283+ u32 ple_stat[8] = {0}, total_amsdu = 0;
4284+ u8 i;
4285+
4286+ for (i = 0; i < 8; i++)
4287+ ple_stat[i] = mt76_rr(dev, MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(i));
4288+
4289+ seq_printf(s, "TXD counter status of MSDU:\n");
4290+
4291+ for (i = 0; i < 8; i++)
4292+ total_amsdu += ple_stat[i];
4293+
4294+ for (i = 0; i < 8; i++) {
4295+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i + 1, ple_stat[i]);
4296+ if (total_amsdu != 0)
4297+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
4298+ else
4299+ seq_printf(s, "\n");
4300+ }
4301+
4302+ return 0;
4303+
4304+}
4305+
4306+static int mt7915_agginfo_read_per_band(struct seq_file *s, int band_idx)
4307+{
4308+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4309+ u32 value, idx, agg_rang_sel[15], ampdu_cnt[11], total_ampdu = 0;
4310+
4311+ seq_printf(s, "Band %d AGG Status\n", band_idx);
4312+ seq_printf(s, "===============================\n");
4313+ value = mt76_rr(dev, MT_DBG_AGG_AALCR0(band_idx));
4314+ seq_printf(s, "AC00 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4315+ seq_printf(s, "AC01 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4316+ seq_printf(s, "AC02 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4317+ seq_printf(s, "AC03 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4318+
4319+ value = mt76_rr(dev, MT_DBG_AGG_AALCR1(band_idx));
4320+ seq_printf(s, "AC10 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4321+ seq_printf(s, "AC11 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4322+ seq_printf(s, "AC12 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4323+ seq_printf(s, "AC13 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4324+
4325+ value = mt76_rr(dev, MT_DBG_AGG_AALCR2(band_idx));
4326+ seq_printf(s, "AC20 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4327+ seq_printf(s, "AC21 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4328+ seq_printf(s, "AC22 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4329+ seq_printf(s, "AC23 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4330+
4331+ value = mt76_rr(dev, MT_DBG_AGG_AALCR3(band_idx));
4332+ seq_printf(s, "AC30 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4333+ seq_printf(s, "AC31 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4334+ seq_printf(s, "AC32 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4335+ seq_printf(s, "AC33 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4336+
4337+ value = mt76_rr(dev, MT_DBG_AGG_AALCR4(band_idx));
4338+ seq_printf(s, "ALTX Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK, value));
4339+
4340+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 0));
4341+ seq_printf(s, "Winsize0 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE0_MASK, value));
4342+ seq_printf(s, "Winsize1 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE1_MASK, value));
4343+ seq_printf(s, "Winsize2 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE2_MASK, value));
4344+ seq_printf(s, "Winsize3 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE3_MASK, value));
4345+
4346+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 1));
4347+ seq_printf(s, "Winsize4 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE4_MASK, value));
4348+ seq_printf(s, "Winsize5 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE5_MASK, value));
4349+ seq_printf(s, "Winsize6 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE6_MASK, value));
4350+ seq_printf(s, "Winsize7 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE7_MASK, value));
4351+
4352+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 2));
4353+ seq_printf(s, "Winsize8 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE8_MASK, value));
4354+ seq_printf(s, "Winsize9 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE9_MASK, value));
4355+ seq_printf(s, "WinsizeA limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEA_MASK, value));
4356+ seq_printf(s, "WinsizeB limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEB_MASK, value));
4357+
4358+
4359+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 3));
4360+ seq_printf(s, "WinsizeC limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEC_MASK, value));
4361+ seq_printf(s, "WinsizeD limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZED_MASK, value));
4362+ seq_printf(s, "WinsizeE limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEE_MASK, value));
4363+
4364+ seq_printf(s, "===AMPDU Related Counters===\n");
4365+
4366+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 0));
4367+ agg_rang_sel[0] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK, value);
4368+ agg_rang_sel[1] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK, value);
4369+ agg_rang_sel[2] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK, value);
4370+ agg_rang_sel[3] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK, value);
4371+
4372+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 1));
4373+ agg_rang_sel[4] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK, value);
4374+ agg_rang_sel[5] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK, value);
4375+ agg_rang_sel[6] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK, value);
4376+ agg_rang_sel[7] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK, value);
4377+
4378+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 2));
4379+ agg_rang_sel[8] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK, value);
4380+ agg_rang_sel[9] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK, value);
4381+ agg_rang_sel[10] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK, value);
4382+ agg_rang_sel[11] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK, value);
4383+
4384+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 3));
4385+ agg_rang_sel[12] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK, value);
4386+ agg_rang_sel[13] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK, value);
4387+ agg_rang_sel[14] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK, value);
4388+
4389+ /* Need to add 1 after read from AGG_RANG_SEL CR */
4390+ for (idx = 0; idx < 15; idx++)
4391+ agg_rang_sel[idx]++;
4392+
4393+ ampdu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 0));
4394+ ampdu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 1));
4395+ ampdu_cnt[5] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 2));
4396+ ampdu_cnt[6] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 3));
4397+ ampdu_cnt[7] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 0));
4398+ ampdu_cnt[8] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 1));
4399+ ampdu_cnt[9] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 2));
4400+ ampdu_cnt[10] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 3));
4401+
4402+ seq_printf(s, "\tTx Agg Range: \t%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d\n",
4403+ agg_rang_sel[0],
4404+ agg_rang_sel[0] + 1, agg_rang_sel[1],
4405+ agg_rang_sel[1] + 1, agg_rang_sel[2],
4406+ agg_rang_sel[2] + 1, agg_rang_sel[3],
4407+ agg_rang_sel[3] + 1, agg_rang_sel[4],
4408+ agg_rang_sel[4] + 1, agg_rang_sel[5],
4409+ agg_rang_sel[5] + 1, agg_rang_sel[6],
4410+ agg_rang_sel[6] + 1, agg_rang_sel[7]);
4411+
4412+#define BIT_0_to_15_MASK 0x0000FFFF
4413+#define BIT_15_to_31_MASK 0xFFFF0000
4414+#define SHFIT_16_BIT 16
4415+
4416+ for (idx = 3; idx < 11; idx++)
4417+ total_ampdu = total_ampdu + (ampdu_cnt[idx] & BIT_0_to_15_MASK) + ((ampdu_cnt[idx] & BIT_15_to_31_MASK) >> SHFIT_16_BIT);
4418+
4419+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4420+ (ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK,
4421+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]),
4422+ (ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK,
4423+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]),
4424+ (ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK,
4425+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]),
4426+ (ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK,
4427+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]));
4428+
4429+ if (total_ampdu != 0) {
4430+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4431+ ((ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4432+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]) * 100 / total_ampdu,
4433+ ((ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4434+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]) * 100 / total_ampdu,
4435+ ((ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4436+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]) * 100 / total_ampdu,
4437+ ((ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4438+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]) * 100 / total_ampdu);
4439+ }
4440+
4441+ seq_printf(s, "\t\t\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~256\n",
4442+ agg_rang_sel[7] + 1, agg_rang_sel[8],
4443+ agg_rang_sel[8] + 1, agg_rang_sel[9],
4444+ agg_rang_sel[9] + 1, agg_rang_sel[10],
4445+ agg_rang_sel[10] + 1, agg_rang_sel[11],
4446+ agg_rang_sel[11] + 1, agg_rang_sel[12],
4447+ agg_rang_sel[12] + 1, agg_rang_sel[13],
4448+ agg_rang_sel[13] + 1, agg_rang_sel[14],
4449+ agg_rang_sel[14] + 1);
4450+
4451+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4452+ (ampdu_cnt[7]) & MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK,
4453+ FIELD_GET(MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK, ampdu_cnt[7]),
4454+ (ampdu_cnt[8]) & MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK,
4455+ FIELD_GET(MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK, ampdu_cnt[8]),
4456+ (ampdu_cnt[9]) & MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK,
4457+ FIELD_GET(MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK, ampdu_cnt[9]),
4458+ (ampdu_cnt[10]) & MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK,
4459+ FIELD_GET(MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK, ampdu_cnt[10]));
4460+
4461+ if (total_ampdu != 0) {
4462+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4463+ ((ampdu_cnt[7]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4464+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[7]) * 100 / total_ampdu,
4465+ ((ampdu_cnt[8]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4466+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[8]) * 100 / total_ampdu,
4467+ ((ampdu_cnt[9]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4468+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[9]) * 100 / total_ampdu,
4469+ ((ampdu_cnt[10]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4470+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[10]) * 100 / total_ampdu);
4471+ }
4472+
4473+ return 0;
4474+}
4475+
4476+static int mt7915_agginfo_read_band0(struct seq_file *s, void *data)
4477+{
4478+ mt7915_agginfo_read_per_band(s, 0);
4479+ return 0;
4480+}
4481+
4482+static int mt7915_agginfo_read_band1(struct seq_file *s, void *data)
4483+{
4484+ mt7915_agginfo_read_per_band(s, 1);
4485+ return 0;
4486+}
4487+
4488+/*usage: <en> <num> <len>
4489+ en: BIT(16) 0: sw amsdu 1: hw amsdu
4490+ num: GENMASK(15, 8) range 1-8
4491+ len: GENMASK(7, 0) unit: 256 bytes */
4492+static int mt7915_sta_tx_amsdu_set(void *data, u64 tx_amsdu)
4493+{
4494+/* UWTBL DW 6 */
4495+#define WTBL_AMSDU_LEN_MASK GENMASK(5, 0)
4496+#define WTBL_AMSDU_NUM_MASK GENMASK(8, 6)
4497+#define WTBL_AMSDU_EN_MASK BIT(9)
4498+#define UWTBL_HW_AMSDU_DW 6
4499+
4500+ struct mt7915_dev *dev = data;
4501+ u32 len = FIELD_GET(GENMASK(7, 0), tx_amsdu);
4502+ u32 num = FIELD_GET(GENMASK(15, 8), tx_amsdu);
4503+ u32 uwtbl;
4504+
developer9e5bcc52022-09-27 10:30:15 +08004505+ mt7915_mcu_set_amsdu_algo(dev, dev->wlan_idx, 0);
4506+
developer3fa816c2022-04-19 10:21:20 +08004507+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4508+ UWTBL_HW_AMSDU_DW, 1, &uwtbl);
4509+
4510+ if (len) {
4511+ uwtbl &= ~WTBL_AMSDU_LEN_MASK;
4512+ uwtbl |= FIELD_PREP(WTBL_AMSDU_LEN_MASK, len);
4513+ }
4514+
4515+ uwtbl &= ~WTBL_AMSDU_NUM_MASK;
4516+ uwtbl |= FIELD_PREP(WTBL_AMSDU_NUM_MASK, num);
4517+
4518+ if (tx_amsdu & BIT(16))
4519+ uwtbl |= WTBL_AMSDU_EN_MASK;
4520+
4521+ mt7915_wtbl_write_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4522+ UWTBL_HW_AMSDU_DW, uwtbl);
4523+
4524+ return 0;
4525+}
4526+
4527+DEFINE_DEBUGFS_ATTRIBUTE(fops_tx_amsdu, NULL,
4528+ mt7915_sta_tx_amsdu_set, "%llx\n");
4529+
4530+static int mt7915_red_enable_set(void *data, u64 en)
4531+{
4532+ struct mt7915_dev *dev = data;
4533+
4534+ return mt7915_mcu_set_red(dev, en);
4535+}
4536+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_en, NULL,
4537+ mt7915_red_enable_set, "%llx\n");
4538+
4539+static int mt7915_red_show_sta_set(void *data, u64 wlan_idx)
4540+{
4541+ struct mt7915_dev *dev = data;
4542+
4543+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4544+ MCU_WA_PARAM_RED_SHOW_STA,
4545+ wlan_idx, 0, true);
4546+
4547+ return 0;
4548+}
4549+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_show_sta, NULL,
4550+ mt7915_red_show_sta_set, "%llx\n");
4551+
4552+static int mt7915_red_target_dly_set(void *data, u64 delay)
4553+{
4554+ struct mt7915_dev *dev = data;
4555+
4556+ if (delay > 0 && delay <= 32767)
4557+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4558+ MCU_WA_PARAM_RED_TARGET_DELAY,
4559+ delay, 0, true);
4560+
4561+ return 0;
4562+}
4563+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_target_dly, NULL,
4564+ mt7915_red_target_dly_set, "%llx\n");
4565+
4566+static int
4567+mt7915_txpower_level_set(void *data, u64 val)
4568+{
4569+ struct mt7915_dev *dev = data;
4570+ struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
4571+ mt7915_mcu_set_txpower_level(&dev->phy, val);
4572+ if (ext_phy)
4573+ mt7915_mcu_set_txpower_level(ext_phy, val);
4574+
4575+ return 0;
4576+}
4577+
4578+DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
4579+ mt7915_txpower_level_set, "%lld\n");
4580+
4581+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
4582+static int
4583+mt7915_wa_set(void *data, u64 val)
4584+{
4585+ struct mt7915_dev *dev = data;
4586+ u32 arg1, arg2, arg3;
4587+
4588+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4589+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4590+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4591+
4592+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), arg1, arg2, arg3, false);
4593+
4594+ return 0;
4595+}
4596+
4597+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7915_wa_set,
4598+ "0x%llx\n");
4599+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
4600+static int
4601+mt7915_wa_query(void *data, u64 val)
4602+{
4603+ struct mt7915_dev *dev = data;
4604+ u32 arg1, arg2, arg3;
4605+
4606+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4607+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4608+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4609+
4610+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), arg1, arg2, arg3, false);
4611+
4612+ return 0;
4613+}
4614+
4615+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7915_wa_query,
4616+ "0x%llx\n");
4617+/* set wa debug level
4618+ usage:
4619+ echo 0x[arg] > fw_wa_debug
4620+ bit0 : DEBUG_WIFI_TX
4621+ bit1 : DEBUG_CMD_EVENT
4622+ bit2 : DEBUG_RED
4623+ bit3 : DEBUG_WARN
4624+ bit4 : DEBUG_WIFI_RX
4625+ bit5 : DEBUG_TIME_STAMP
4626+ bit6 : DEBUG_TX_FREE_DONE_EVENT
4627+ bit12 : DEBUG_WIFI_TXD */
4628+static int
4629+mt7915_wa_debug(void *data, u64 val)
4630+{
4631+ struct mt7915_dev *dev = data;
4632+ u32 arg;
4633+
4634+ arg = FIELD_GET(GENMASK_ULL(15, 0), val);
4635+
4636+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(DEBUG), arg, 0, 0, false);
4637+
4638+ return 0;
4639+}
4640+
4641+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_debug, NULL, mt7915_wa_debug,
4642+ "0x%llx\n");
4643+
4644+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
4645+{
4646+ struct mt7915_dev *dev = phy->dev;
4647+ u32 device_id = (dev->mt76.rev) >> 16;
4648+ int i = 0;
4649+
4650+ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
4651+ if (device_id == dbg_reg_s[i].id) {
4652+ dev->dbg_reg = &dbg_reg_s[i];
4653+ break;
4654+ }
4655+ }
4656+
4657+ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
4658+
4659+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
4660+ &fops_fw_debug_module);
4661+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
4662+ &fops_fw_debug_level);
4663+
developerf32dabf2022-06-01 10:59:24 +08004664+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
4665+ mt7915_sta_info);
developer3fa816c2022-04-19 10:21:20 +08004666+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
4667+ mt7915_wtbl_read);
4668+ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
4669+ mt7915_uwtbl_read);
4670+
4671+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
4672+ mt7915_trinfo_read);
4673+
4674+ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
4675+ mt7915_drr_info);
4676+
4677+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
4678+ mt7915_pleinfo_read);
4679+
4680+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
4681+ mt7915_pseinfo_read);
4682+
4683+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4684+ mt7915_mibinfo_band0);
4685+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4686+ mt7915_mibinfo_band1);
4687+
4688+ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
4689+ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
4690+ mt7915_token_read);
4691+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
4692+ mt7915_token_txd_read);
4693+
4694+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
4695+ mt7915_amsduinfo_read);
4696+
4697+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
4698+ mt7915_agginfo_read_band0);
4699+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
4700+ mt7915_agginfo_read_band1);
4701+
4702+ debugfs_create_file("tx_amsdu", 0600, dir, dev, &fops_tx_amsdu);
4703+
4704+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
4705+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
4706+ debugfs_create_file("fw_wa_debug", 0600, dir, dev, &fops_wa_debug);
4707+
4708+ debugfs_create_file("red_en", 0600, dir, dev,
4709+ &fops_red_en);
4710+ debugfs_create_file("red_show_sta", 0600, dir, dev,
4711+ &fops_red_show_sta);
4712+ debugfs_create_file("red_target_dly", 0600, dir, dev,
4713+ &fops_red_target_dly);
4714+
4715+ debugfs_create_file("txpower_level", 0400, dir, dev,
4716+ &fops_txpower_level);
4717+
developeraace7f52022-06-24 13:40:42 +08004718+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
4719+
developer3fa816c2022-04-19 10:21:20 +08004720+ return 0;
4721+}
4722+#endif
4723diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
4724new file mode 100644
developerf1313102022-10-11 11:02:55 +08004725index 0000000..145fe78
developer3fa816c2022-04-19 10:21:20 +08004726--- /dev/null
4727+++ b/mt7915/mtk_mcu.c
4728@@ -0,0 +1,51 @@
4729+#include <linux/firmware.h>
4730+#include <linux/fs.h>
4731+#include<linux/inet.h>
4732+#include "mt7915.h"
4733+#include "mcu.h"
4734+#include "mac.h"
4735+
4736+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
4737+{
4738+ struct mt7915_dev *dev = phy->dev;
4739+ struct mt7915_sku_val {
4740+ u8 format_id;
4741+ u8 val;
4742+ u8 band;
4743+ u8 _rsv;
4744+ } __packed req = {
4745+ .format_id = 1,
4746+ .band = phy->band_idx,
4747+ .val = !!drop_level,
4748+ };
4749+ int ret;
4750+
4751+ ret = mt76_mcu_send_msg(&dev->mt76,
4752+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4753+ sizeof(req), true);
4754+ if (ret)
4755+ return ret;
4756+
4757+ req.format_id = 2;
4758+ if ((drop_level > 90 && drop_level < 100) || !drop_level)
4759+ req.val = 0;
4760+ else if (drop_level > 60 && drop_level <= 90)
4761+ /* reduce Pwr for 1 dB. */
4762+ req.val = 2;
4763+ else if (drop_level > 30 && drop_level <= 60)
4764+ /* reduce Pwr for 3 dB. */
4765+ req.val = 6;
4766+ else if (drop_level > 15 && drop_level <= 30)
4767+ /* reduce Pwr for 6 dB. */
4768+ req.val = 12;
4769+ else if (drop_level > 9 && drop_level <= 15)
4770+ /* reduce Pwr for 9 dB. */
4771+ req.val = 18;
4772+ else if (drop_level > 0 && drop_level <= 9)
4773+ /* reduce Pwr for 12 dB. */
4774+ req.val = 24;
4775+
4776+ return mt76_mcu_send_msg(&dev->mt76,
4777+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4778+ sizeof(req), true);
4779+}
4780diff --git a/tools/fwlog.c b/tools/fwlog.c
developerf1313102022-10-11 11:02:55 +08004781index e5d4a10..3d51d9e 100644
developer3fa816c2022-04-19 10:21:20 +08004782--- a/tools/fwlog.c
4783+++ b/tools/fwlog.c
4784@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
4785 return path;
4786 }
4787
4788-static int mt76_set_fwlog_en(const char *phyname, bool en)
4789+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
4790 {
4791 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
4792
4793@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
4794 return 1;
4795 }
4796
4797- fprintf(f, "7");
4798+ if (en && val)
4799+ fprintf(f, "%s", val);
4800+ else if (en)
4801+ fprintf(f, "7");
4802+ else
4803+ fprintf(f, "0");
4804+
4805 fclose(f);
4806
4807 return 0;
4808@@ -76,6 +82,7 @@ static void handle_signal(int sig)
4809
4810 int mt76_fwlog(const char *phyname, int argc, char **argv)
4811 {
4812+#define BUF_SIZE 1504
4813 struct sockaddr_in local = {
4814 .sin_family = AF_INET,
4815 .sin_addr.s_addr = INADDR_ANY,
developerf32dabf2022-06-01 10:59:24 +08004816@@ -84,9 +91,10 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08004817 .sin_family = AF_INET,
4818 .sin_port = htons(55688),
4819 };
4820- char buf[1504];
4821+ char *buf = calloc(BUF_SIZE, sizeof(char));
developerf32dabf2022-06-01 10:59:24 +08004822+ FILE *logfile = NULL;
developer3fa816c2022-04-19 10:21:20 +08004823 int ret = 0;
4824- int yes = 1;
4825+ /* int yes = 1; */
4826 int s, fd;
4827
4828 if (argc < 1) {
developerf32dabf2022-06-01 10:59:24 +08004829@@ -99,19 +107,28 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4830 return 1;
4831 }
4832
4833+ if (argc == 3) {
4834+ fprintf(stdout, "start logging to file %s\n", argv[2]);
4835+ logfile = fopen(argv[2], "wb");
4836+ if (!logfile) {
4837+ perror("fopen");
4838+ return 1;
4839+ }
4840+ }
4841+
4842 s = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
4843 if (s < 0) {
4844 perror("socket");
developer3fa816c2022-04-19 10:21:20 +08004845 return 1;
4846 }
4847
4848- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
4849+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
4850 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
4851 perror("bind");
4852 return 1;
4853 }
4854
4855- if (mt76_set_fwlog_en(phyname, true))
4856+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
4857 return 1;
4858
4859 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
developerf32dabf2022-06-01 10:59:24 +08004860@@ -145,8 +162,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08004861 if (!r)
4862 continue;
4863
4864- if (len > sizeof(buf)) {
4865- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
4866+ if (len > BUF_SIZE) {
4867+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
4868 ret = 1;
4869 break;
4870 }
developerf32dabf2022-06-01 10:59:24 +08004871@@ -164,14 +181,19 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4872 break;
4873 }
4874
4875- /* send buf */
4876- sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
4877+ if (logfile)
4878+ fwrite(buf, 1, len, logfile);
4879+ else
4880+ /* send buf */
4881+ sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
4882 }
4883
developer3fa816c2022-04-19 10:21:20 +08004884 close(fd);
4885
4886 out:
4887- mt76_set_fwlog_en(phyname, false);
4888+ mt76_set_fwlog_en(phyname, false, NULL);
4889+ free(buf);
developerf32dabf2022-06-01 10:59:24 +08004890+ fclose(logfile);
developer3fa816c2022-04-19 10:21:20 +08004891
4892 return ret;
4893 }
4894--
developer9e5bcc52022-09-27 10:30:15 +080048952.18.0
developer3fa816c2022-04-19 10:21:20 +08004896