developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 1 | From 3049935f79f524aa6984ccfa97075df4b1aadb41 Mon Sep 17 00:00:00 2001 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 2 | From: Sujuan Chen <sujuan.chen@mediatek.com> |
| 3 | Date: Sun, 12 Jun 2022 16:38:45 +0800 |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 4 | Subject: [PATCH 3001/3006] mt76 add wed tx support |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 5 | |
| 6 | Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com> |
| 7 | --- |
developer | c89c547 | 2022-08-02 13:00:04 +0800 | [diff] [blame] | 8 | mt76_connac.h | 1 + |
| 9 | mt7915/dma.c | 59 +++++++++++++++++++------- |
| 10 | mt7915/mac.c | 4 +- |
| 11 | mt7915/main.c | 9 +++- |
| 12 | mt7915/mcu.c | 2 +- |
| 13 | mt7915/mmio.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++- |
| 14 | mt7915/mt7915.h | 2 + |
| 15 | mt7915/pci.c | 72 +------------------------------ |
| 16 | mt7915/regs.h | 15 +++++++ |
| 17 | mt7915/soc.c | 16 +++++-- |
developer | d497569 | 2022-07-15 18:30:03 +0800 | [diff] [blame] | 18 | 10 files changed, 193 insertions(+), 97 deletions(-) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 19 | |
| 20 | diff --git a/mt76_connac.h b/mt76_connac.h |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 21 | index 7b6b3aa..f71ded8 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 22 | --- a/mt76_connac.h |
| 23 | +++ b/mt76_connac.h |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 24 | @@ -116,6 +116,7 @@ struct mt76_connac_sta_key_conf { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 25 | }; |
| 26 | |
| 27 | #define MT_TXP_MAX_BUF_NUM 6 |
| 28 | +#define MT_TXD_TXP_BUF_SIZE 128 |
| 29 | |
| 30 | struct mt76_connac_fw_txp { |
| 31 | __le16 flags; |
| 32 | diff --git a/mt7915/dma.c b/mt7915/dma.c |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 33 | index 4b594a5..ac30698 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 34 | --- a/mt7915/dma.c |
| 35 | +++ b/mt7915/dma.c |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 36 | @@ -11,7 +11,10 @@ mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base |
| 37 | struct mt7915_dev *dev = phy->dev; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 38 | |
| 39 | if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { |
| 40 | - ring_base = MT_WED_TX_RING_BASE; |
| 41 | + if(!is_mt7986(&dev->mt76)) |
| 42 | + ring_base = MT_WED_TX_RING_BASE; |
| 43 | + else |
| 44 | + ring_base += MT_TXQ_ID(0) * MT_RING_SIZE; |
| 45 | idx -= MT_TXQ_ID(0); |
| 46 | } |
| 47 | |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 48 | @@ -58,14 +61,23 @@ static void mt7915_dma_config(struct mt7915_dev *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 49 | MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, MT7915_TXQ_MCU_WA); |
| 50 | MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL); |
| 51 | } else { |
| 52 | - RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0); |
| 53 | + if(is_mt7916(&dev->mt76) && (mtk_wed_device_active(&dev->mt76.mmio.wed))) { |
| 54 | + RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_WED_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0); |
| 55 | + RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MT7916, MT7916_RXQ_MCU_WA); |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 56 | + RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 57 | + RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN); |
| 58 | + TXQ_CONFIG(0, WFDMA0, MT_INT_WED_TX_DONE_BAND0, MT7915_TXQ_BAND0); |
| 59 | + TXQ_CONFIG(1, WFDMA0, MT_INT_WED_TX_DONE_BAND1, MT7915_TXQ_BAND1); |
| 60 | + } else { |
| 61 | + RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0); |
| 62 | + RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA); |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 63 | + RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 64 | + RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN); |
| 65 | + TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0); |
| 66 | + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1); |
| 67 | + } |
| 68 | RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7916_RXQ_MCU_WM); |
| 69 | - RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA); |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 70 | - RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1); |
| 71 | RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, MT7916_RXQ_MCU_WA_EXT); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 72 | - RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN); |
| 73 | - TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0); |
| 74 | - TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1); |
| 75 | MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM); |
| 76 | MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, MT7915_TXQ_MCU_WA); |
| 77 | MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL); |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 78 | @@ -323,7 +335,9 @@ static int mt7915_dma_enable(struct mt7915_dev *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 79 | u32 wed_irq_mask = irq_mask; |
| 80 | |
| 81 | wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1; |
| 82 | - mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask); |
| 83 | + if (!is_mt7986(&dev->mt76)) |
| 84 | + mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask); |
| 85 | + mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); |
| 86 | mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask); |
| 87 | } |
| 88 | |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 89 | @@ -348,15 +362,19 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 90 | |
| 91 | mt7915_dma_disable(dev, true); |
| 92 | |
| 93 | - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
| 94 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && !is_mt7986(mdev)) { |
| 95 | mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); |
| 96 | - |
| 97 | + if(is_mt7915(mdev)) { |
| 98 | mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL, |
| 99 | FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) | |
| 100 | FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) | |
| 101 | FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1)); |
| 102 | - } else { |
| 103 | - mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); |
| 104 | + } else { |
| 105 | + mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL, |
| 106 | + FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) | |
| 107 | + FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) | |
| 108 | + FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 2)); |
| 109 | + } |
| 110 | } |
| 111 | |
| 112 | /* init tx queue */ |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 113 | @@ -410,7 +428,7 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 114 | return ret; |
| 115 | |
| 116 | /* event from WA */ |
| 117 | - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
| 118 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && is_mt7915(mdev)) { |
| 119 | wa_rx_base = MT_WED_RX_RING_BASE; |
| 120 | wa_rx_idx = MT7915_RXQ_MCU_WA; |
| 121 | dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE; |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 122 | @@ -437,11 +455,20 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 123 | |
| 124 | /* tx free notify event from WA for band0 */ |
| 125 | if (!is_mt7915(mdev)) { |
| 126 | + wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA); |
| 127 | + wa_rx_idx = MT_RXQ_ID(MT_RXQ_MAIN_WA); |
| 128 | + |
| 129 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
| 130 | + dev->mt76.q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE; |
| 131 | + if (is_mt7916(mdev)) { |
| 132 | + wa_rx_base = MT_WED_RX_RING_BASE; |
| 133 | + wa_rx_idx = MT7915_RXQ_MCU_WA; |
| 134 | + } |
| 135 | + } |
| 136 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA], |
| 137 | - MT_RXQ_ID(MT_RXQ_MAIN_WA), |
| 138 | + wa_rx_idx, |
| 139 | MT7915_RX_MCU_RING_SIZE, |
| 140 | - MT_RX_BUF_SIZE, |
| 141 | - MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA)); |
| 142 | + MT_RX_BUF_SIZE, wa_rx_base); |
| 143 | if (ret) |
| 144 | return ret; |
| 145 | } |
| 146 | diff --git a/mt7915/mac.c b/mt7915/mac.c |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 147 | index 7c11e28..0a13b7d 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 148 | --- a/mt7915/mac.c |
| 149 | +++ b/mt7915/mac.c |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 150 | @@ -826,9 +826,9 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 151 | |
| 152 | txp->token = cpu_to_le16(token_id); |
| 153 | txp->nbuf = 1; |
| 154 | - txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); |
| 155 | + txp->buf[0] = cpu_to_le32(phys + MT_TXD_TXP_BUF_SIZE); |
| 156 | |
| 157 | - return MT_TXD_SIZE + sizeof(*txp); |
| 158 | + return MT_TXD_TXP_BUF_SIZE; |
| 159 | } |
| 160 | |
| 161 | static void |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 162 | diff --git a/mt7915/main.c b/mt7915/main.c |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 163 | index c287de3..b77b3be 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 164 | --- a/mt7915/main.c |
| 165 | +++ b/mt7915/main.c |
| 166 | @@ -1439,14 +1439,19 @@ mt7915_net_fill_forward_path(struct ieee80211_hw *hw, |
| 167 | if (!mtk_wed_device_active(wed)) |
| 168 | return -ENODEV; |
| 169 | |
| 170 | - if (msta->wcid.idx > 0xff) |
| 171 | + if (msta->wcid.idx > MT7915_WTBL_STA) |
| 172 | return -EIO; |
| 173 | |
| 174 | path->type = DEV_PATH_MTK_WDMA; |
| 175 | path->dev = ctx->dev; |
| 176 | path->mtk_wdma.wdma_idx = wed->wdma_idx; |
| 177 | path->mtk_wdma.bss = mvif->mt76.idx; |
| 178 | - path->mtk_wdma.wcid = msta->wcid.idx; |
| 179 | + /* fw will find the wcid by dest addr */ |
| 180 | + if(is_mt7915(&dev->mt76)) |
| 181 | + path->mtk_wdma.wcid = 0xff; |
| 182 | + else |
| 183 | + path->mtk_wdma.wcid = 0x3ff; |
| 184 | + |
| 185 | path->mtk_wdma.queue = phy != &dev->phy; |
| 186 | |
| 187 | ctx->dev = NULL; |
| 188 | diff --git a/mt7915/mcu.c b/mt7915/mcu.c |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 189 | index 6931f2a..a041bb2 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 190 | --- a/mt7915/mcu.c |
| 191 | +++ b/mt7915/mcu.c |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 192 | @@ -2377,7 +2377,7 @@ int mt7915_run_firmware(struct mt7915_dev *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 193 | if (ret) |
| 194 | return ret; |
| 195 | |
| 196 | - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) |
| 197 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && is_mt7915(&dev->mt76)) |
| 198 | mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), 0, 0, 0); |
| 199 | |
| 200 | ret = mt7915_mcu_set_mwds(dev, 1); |
| 201 | diff --git a/mt7915/mmio.c b/mt7915/mmio.c |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 202 | index 8d966ef..b0d8a61 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 203 | --- a/mt7915/mmio.c |
| 204 | +++ b/mt7915/mmio.c |
| 205 | @@ -10,6 +10,9 @@ |
| 206 | #include "mac.h" |
| 207 | #include "../trace.h" |
| 208 | |
| 209 | +static bool wed_enable = true; |
| 210 | +module_param(wed_enable, bool, 0644); |
| 211 | + |
| 212 | static const u32 mt7915_reg[] = { |
| 213 | [INT_SOURCE_CSR] = 0xd7010, |
| 214 | [INT_MASK_CSR] = 0xd7014, |
| 215 | @@ -541,7 +544,11 @@ void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, |
| 216 | mdev->mmio.irqmask |= set; |
| 217 | |
| 218 | if (write_reg) { |
| 219 | - mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); |
| 220 | + if (mtk_wed_device_active(&mdev->mmio.wed)) |
| 221 | + mtk_wed_device_irq_set_mask(&mdev->mmio.wed, |
| 222 | + mdev->mmio.irqmask); |
| 223 | + else |
| 224 | + mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); |
| 225 | mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); |
| 226 | } |
| 227 | |
| 228 | @@ -565,6 +572,8 @@ static void mt7915_irq_tasklet(struct tasklet_struct *t) |
| 229 | |
| 230 | if (mtk_wed_device_active(wed)) { |
| 231 | mtk_wed_device_irq_set_mask(wed, 0); |
| 232 | + if (dev->hif2) |
| 233 | + mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 234 | intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); |
| 235 | } else { |
| 236 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 237 | @@ -646,6 +655,105 @@ irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) |
| 238 | return IRQ_HANDLED; |
| 239 | } |
| 240 | |
| 241 | +#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 242 | +static int mt7915_wed_offload_enable(struct mtk_wed_device *wed) |
| 243 | +{ |
| 244 | + struct mt7915_dev *dev; |
| 245 | + int ret; |
| 246 | + |
| 247 | + dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); |
| 248 | + |
| 249 | + spin_lock_bh(&dev->mt76.token_lock); |
| 250 | + dev->mt76.token_size = wed->wlan.token_start; |
| 251 | + spin_unlock_bh(&dev->mt76.token_lock); |
| 252 | + |
| 253 | + ret = wait_event_timeout(dev->mt76.tx_wait, |
| 254 | + !dev->mt76.wed_token_count, HZ); |
| 255 | + if (!ret) |
| 256 | + return -EAGAIN; |
| 257 | + |
| 258 | + return 0; |
| 259 | +} |
| 260 | + |
| 261 | +static void mt7915_wed_offload_disable(struct mtk_wed_device *wed) |
| 262 | +{ |
| 263 | + struct mt7915_dev *dev; |
| 264 | + |
| 265 | + dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); |
| 266 | + |
| 267 | + spin_lock_bh(&dev->mt76.token_lock); |
| 268 | + dev->mt76.token_size = wed->wlan.token_start;//MT7915_TOKEN_SIZE; |
| 269 | + spin_unlock_bh(&dev->mt76.token_lock); |
| 270 | +} |
| 271 | +#endif |
| 272 | + |
| 273 | +int |
| 274 | +mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq) |
| 275 | +{ |
| 276 | +#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 277 | + struct mt76_dev *mdev = &dev->mt76; |
| 278 | + struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 279 | + u32 base; |
| 280 | + int ret; |
| 281 | + |
| 282 | + if (!wed_enable) |
| 283 | + return 0; |
| 284 | + |
| 285 | + if (dev_is_pci(pdev)) { |
| 286 | + struct pci_dev *pci_dev; |
| 287 | + |
| 288 | + pci_dev = container_of(pdev, struct pci_dev, dev); |
| 289 | + base = pci_resource_start(pci_dev, 0); |
| 290 | + wed->wlan.base = (void __iomem *)ioremap(base, pci_resource_len(pci_dev, 0)); |
| 291 | + |
| 292 | + wed->wlan.pci_dev = pci_dev; |
| 293 | + wed->wlan.bus_type = MTK_BUS_TYPE_PCIE; |
| 294 | + wed->wlan.wpdma_int = base + MT_INT_WED_SOURCE_CSR; |
| 295 | + wed->wlan.wpdma_mask = base + MT_INT_WED_MASK_CSR; |
| 296 | + } else { |
| 297 | + struct platform_device *plat_dev; |
| 298 | + struct resource *res; |
| 299 | + |
| 300 | + plat_dev = to_platform_device(pdev); |
| 301 | + res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); |
| 302 | + base = res->start; |
| 303 | + wed->wlan.base = (void __iomem *)ioremap(base, resource_size(res)); |
| 304 | + wed->wlan.bus_type = MTK_BUS_TYPE_AXI; |
| 305 | + wed->wlan.wpdma_int = base + MT_INT_SOURCE_CSR; |
| 306 | + wed->wlan.wpdma_mask = base + MT_INT_MASK_CSR; |
| 307 | + } |
| 308 | + wed->wlan.wpdma_tx = base + MT_TXQ_WED_RING_BASE; |
| 309 | + wed->wlan.wpdma_txfree = base + MT_RXQ_WED_RING_BASE; |
| 310 | + |
| 311 | + wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0; |
| 312 | + wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1; |
| 313 | + wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE; |
| 314 | + wed->wlan.nbuf = 7168; |
| 315 | + wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf; |
| 316 | + wed->wlan.init_buf = mt7915_wed_init_buf; |
| 317 | + /* disable dynamic tx token */ |
| 318 | + wed->wlan.offload_enable = mt7915_wed_offload_enable; |
| 319 | + wed->wlan.offload_disable = mt7915_wed_offload_disable; |
| 320 | + |
| 321 | + if (mtk_wed_device_attach(wed) != 0) |
| 322 | + return 0; |
| 323 | + |
| 324 | + if (wed->ver == MTK_WED_V1) |
| 325 | + wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE; |
| 326 | + |
| 327 | + *irq = wed->irq; |
| 328 | + dev->mt76.dma_dev = wed->dev; |
| 329 | + mdev->token_size = wed->wlan.token_start; |
| 330 | + ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32)); |
| 331 | + if (ret) |
| 332 | + return ret; |
| 333 | + |
| 334 | + return 1; |
| 335 | +#else |
| 336 | + return 0; |
| 337 | +#endif |
| 338 | +} |
| 339 | + |
| 340 | struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, |
| 341 | void __iomem *mem_base, u32 device_id) |
| 342 | { |
| 343 | diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 344 | index e8ac75e..e329f74 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 345 | --- a/mt7915/mt7915.h |
| 346 | +++ b/mt7915/mt7915.h |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 347 | @@ -536,6 +536,8 @@ static inline void mt7986_wmac_disable(struct mt7915_dev *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 348 | { |
| 349 | } |
| 350 | #endif |
| 351 | +int mt7915_pci_wed_init(struct mt7915_dev *dev, |
| 352 | + struct device *pdev, int *irq); |
| 353 | struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, |
| 354 | void __iomem *mem_base, u32 device_id); |
| 355 | void mt7915_wfsys_reset(struct mt7915_dev *dev); |
| 356 | diff --git a/mt7915/pci.c b/mt7915/pci.c |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 357 | index d74f609..c5da01a 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 358 | --- a/mt7915/pci.c |
| 359 | +++ b/mt7915/pci.c |
| 360 | @@ -12,9 +12,6 @@ |
| 361 | #include "mac.h" |
| 362 | #include "../trace.h" |
| 363 | |
| 364 | -static bool wed_enable = false; |
| 365 | -module_param(wed_enable, bool, 0644); |
| 366 | - |
| 367 | static LIST_HEAD(hif_list); |
| 368 | static DEFINE_SPINLOCK(hif_lock); |
| 369 | static u32 hif_idx; |
| 370 | @@ -95,73 +92,6 @@ static int mt7915_pci_hif2_probe(struct pci_dev *pdev) |
| 371 | return 0; |
| 372 | } |
| 373 | |
| 374 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 375 | -static int mt7915_wed_offload_enable(struct mtk_wed_device *wed) |
| 376 | -{ |
| 377 | - struct mt7915_dev *dev; |
| 378 | - int ret; |
| 379 | - |
| 380 | - dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); |
| 381 | - |
| 382 | - spin_lock_bh(&dev->mt76.token_lock); |
| 383 | - dev->mt76.token_size = wed->wlan.token_start; |
| 384 | - spin_unlock_bh(&dev->mt76.token_lock); |
| 385 | - |
| 386 | - ret = wait_event_timeout(dev->mt76.tx_wait, |
| 387 | - !dev->mt76.wed_token_count, HZ); |
| 388 | - if (!ret) |
| 389 | - return -EAGAIN; |
| 390 | - |
| 391 | - return 0; |
| 392 | -} |
| 393 | - |
| 394 | -static void mt7915_wed_offload_disable(struct mtk_wed_device *wed) |
| 395 | -{ |
| 396 | - struct mt7915_dev *dev; |
| 397 | - |
| 398 | - dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); |
| 399 | - |
| 400 | - spin_lock_bh(&dev->mt76.token_lock); |
| 401 | - dev->mt76.token_size = MT7915_TOKEN_SIZE; |
| 402 | - spin_unlock_bh(&dev->mt76.token_lock); |
| 403 | -} |
| 404 | -#endif |
| 405 | - |
| 406 | -static int |
| 407 | -mt7915_pci_wed_init(struct mt7915_dev *dev, struct pci_dev *pdev, int *irq) |
| 408 | -{ |
| 409 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 410 | - struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 411 | - int ret; |
| 412 | - |
| 413 | - if (!wed_enable) |
| 414 | - return 0; |
| 415 | - |
| 416 | - wed->wlan.pci_dev = pdev; |
| 417 | - wed->wlan.wpdma_phys = pci_resource_start(pdev, 0) + |
| 418 | - MT_WFDMA_EXT_CSR_BASE; |
| 419 | - wed->wlan.nbuf = 4096; |
| 420 | - wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf; |
| 421 | - wed->wlan.init_buf = mt7915_wed_init_buf; |
| 422 | - wed->wlan.offload_enable = mt7915_wed_offload_enable; |
| 423 | - wed->wlan.offload_disable = mt7915_wed_offload_disable; |
| 424 | - |
| 425 | - if (mtk_wed_device_attach(wed) != 0) |
| 426 | - return 0; |
| 427 | - |
| 428 | - *irq = wed->irq; |
| 429 | - dev->mt76.dma_dev = wed->dev; |
| 430 | - |
| 431 | - ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32)); |
| 432 | - if (ret) |
| 433 | - return ret; |
| 434 | - |
| 435 | - return 1; |
| 436 | -#else |
| 437 | - return 0; |
| 438 | -#endif |
| 439 | -} |
| 440 | - |
| 441 | static int mt7915_pci_probe(struct pci_dev *pdev, |
| 442 | const struct pci_device_id *id) |
| 443 | { |
| 444 | @@ -199,7 +129,7 @@ static int mt7915_pci_probe(struct pci_dev *pdev, |
| 445 | mt7915_wfsys_reset(dev); |
| 446 | hif2 = mt7915_pci_init_hif2(pdev); |
| 447 | |
| 448 | - ret = mt7915_pci_wed_init(dev, pdev, &irq); |
| 449 | + ret = mt7915_pci_wed_init(dev, &pdev->dev, &irq); |
| 450 | if (ret < 0) |
| 451 | goto free_wed_or_irq_vector; |
| 452 | |
| 453 | diff --git a/mt7915/regs.h b/mt7915/regs.h |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 454 | index 05ab6d9..432ed30 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 455 | --- a/mt7915/regs.h |
| 456 | +++ b/mt7915/regs.h |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 457 | @@ -617,6 +617,7 @@ enum offs_rev { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 458 | #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) |
| 459 | #define MT_PCIE_RECOG_ID_SEM BIT(31) |
| 460 | |
| 461 | +#define MT_INT_WED_SOURCE_CSR MT_WFDMA_EXT_CSR(0x200) |
| 462 | #define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204) |
| 463 | |
| 464 | #define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300) |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 465 | @@ -663,6 +664,13 @@ enum offs_rev { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 466 | #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ |
| 467 | MT_TXQ_ID(q)* 0x4) |
| 468 | |
| 469 | +#define MT_TXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7300 : 0x24420) |
| 470 | +#define MT_RXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7410 : 0x24520) |
| 471 | + |
| 472 | +#define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30) |
| 473 | +#define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31) |
| 474 | +#define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2) |
| 475 | + |
| 476 | #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR) |
| 477 | #define MT_INT_MASK_CSR __REG(INT_MASK_CSR) |
| 478 | |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 479 | @@ -681,6 +689,11 @@ enum offs_rev { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 480 | #define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2) |
| 481 | #define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3) |
| 482 | |
| 483 | +#define MT_INT_WED_RX_DONE_BAND0_MT7916 BIT(18) |
| 484 | +#define MT_INT_WED_RX_DONE_BAND1_MT7916 BIT(19) |
| 485 | +#define MT_INT_WED_RX_DONE_WA_MAIN_MT7916 BIT(1) |
| 486 | +#define MT_INT_WED_RX_DONE_WA_MT7916 BIT(17) |
| 487 | + |
| 488 | #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) |
| 489 | #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) |
| 490 | |
developer | 4df64ba | 2022-09-01 14:44:55 +0800 | [diff] [blame] | 491 | @@ -704,6 +717,8 @@ enum offs_rev { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 492 | #define MT_INT_TX_DONE_BAND0 BIT(30) |
| 493 | #define MT_INT_TX_DONE_BAND1 BIT(31) |
| 494 | #define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25) |
| 495 | +#define MT_INT_WED_TX_DONE_BAND0 BIT(4) |
| 496 | +#define MT_INT_WED_TX_DONE_BAND1 BIT(5) |
| 497 | |
| 498 | #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ |
| 499 | MT_INT_TX_MCU(MT_MCUQ_WM) | \ |
| 500 | diff --git a/mt7915/soc.c b/mt7915/soc.c |
developer | 27b5525 | 2022-09-05 19:09:45 +0800 | [diff] [blame^] | 501 | index 3618718..8d0b206 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 502 | --- a/mt7915/soc.c |
| 503 | +++ b/mt7915/soc.c |
| 504 | @@ -1171,10 +1171,6 @@ static int mt7986_wmac_probe(struct platform_device *pdev) |
| 505 | |
| 506 | chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev); |
| 507 | |
| 508 | - irq = platform_get_irq(pdev, 0); |
| 509 | - if (irq < 0) |
| 510 | - return irq; |
| 511 | - |
| 512 | mem_base = devm_platform_ioremap_resource(pdev, 0); |
| 513 | if (IS_ERR(mem_base)) { |
| 514 | dev_err(&pdev->dev, "Failed to get memory resource\n"); |
| 515 | @@ -1186,6 +1182,16 @@ static int mt7986_wmac_probe(struct platform_device *pdev) |
| 516 | return PTR_ERR(dev); |
| 517 | |
| 518 | mdev = &dev->mt76; |
| 519 | + ret = mt7915_pci_wed_init(dev, &pdev->dev, &irq); |
| 520 | + if (ret < 0) |
| 521 | + goto free_device; |
| 522 | + |
| 523 | + if (!ret) { |
| 524 | + irq = platform_get_irq(pdev, 0); |
| 525 | + if (irq < 0) |
| 526 | + return irq;; |
| 527 | + } |
| 528 | + |
| 529 | ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler, |
| 530 | IRQF_SHARED, KBUILD_MODNAME, dev); |
| 531 | if (ret) |
| 532 | @@ -1207,6 +1213,8 @@ free_irq: |
| 533 | devm_free_irq(mdev->dev, irq, dev); |
| 534 | |
| 535 | free_device: |
| 536 | + if (mtk_wed_device_active(&mdev->mmio.wed)) |
| 537 | + mtk_wed_device_detach(&mdev->mmio.wed); |
| 538 | mt76_free_device(&dev->mt76); |
| 539 | |
| 540 | return ret; |
| 541 | -- |
developer | c89c547 | 2022-08-02 13:00:04 +0800 | [diff] [blame] | 542 | 2.18.0 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 543 | |