blob: 9d9765b2a437b24336c893e9e0af6015283df07a [file] [log] [blame]
developer2458e702022-12-13 15:52:04 +08001From 7f80dae506d79a41a7357ec14bd6dabdeeb9cd4f Mon Sep 17 00:00:00 2001
developer3d5faf22022-11-29 18:07:22 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Fri, 25 Nov 2022 14:32:35 +0800
developer2458e702022-12-13 15:52:04 +08004Subject: [PATCH 3008/3011] mt76: mt7915: wed: find rx token by physical
developerbcc85ca2022-12-05 11:29:56 +08005 address
developer3d5faf22022-11-29 18:07:22 +08006
7The token id in RxDMAD may be incorrect when it is not the last frame due to
8WED HW bug. Lookup correct token id by physical address in sdp0.
9
10Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
11---
12 dma.c | 21 ++++++++++++++++++++-
13 1 file changed, 20 insertions(+), 1 deletion(-)
14
15diff --git a/dma.c b/dma.c
developer2458e702022-12-13 15:52:04 +080016index 35beec72..327ed3bc 100644
developer3d5faf22022-11-29 18:07:22 +080017--- a/dma.c
18+++ b/dma.c
developer2458e702022-12-13 15:52:04 +080019@@ -376,10 +376,29 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
developer3d5faf22022-11-29 18:07:22 +080020
21 if ((q->flags & MT_QFLAG_WED) &&
22 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX) {
23+ u32 id, find = 0;
24 u32 token = FIELD_GET(MT_DMA_CTL_TOKEN,
25 le32_to_cpu(desc->buf1));
26- struct mt76_txwi_cache *t = mt76_rx_token_release(dev, token);
27+ struct mt76_txwi_cache *t;
28+
29+ if (*more) {
30+ spin_lock_bh(&dev->rx_token_lock);
31+
32+ idr_for_each_entry(&dev->rx_token, t, id) {
33+ if (t->dma_addr == le32_to_cpu(desc->buf0)) {
34+ find = 1;
35+ desc->buf1 = FIELD_PREP(MT_DMA_CTL_TOKEN, id);
36+ token = id;
37+ break;
38+ }
39+ }
40+
41+ spin_unlock_bh(&dev->rx_token_lock);
42+ if (!find)
43+ return NULL;
44+ }
45
46+ t = mt76_rx_token_release(dev, token);
47 if (!t)
48 return NULL;
49
50--
developer2458e702022-12-13 15:52:04 +0800512.25.1
developer3d5faf22022-11-29 18:07:22 +080052