blob: 4b7c3493e1d5a21d43ccc5d80d52950072afb9c0 [file] [log] [blame]
developer27b55252022-09-05 19:09:45 +08001From 3516b23f9acad60c44a13119e42636f92ca9d9a2 Mon Sep 17 00:00:00 2001
developer3262bf82022-07-12 11:37:54 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Tue, 5 Jul 2022 19:42:55 +0800
developer27b55252022-09-05 19:09:45 +08004Subject: [PATCH 3002/3006] mt76 add wed rx support
developer3262bf82022-07-12 11:37:54 +08005
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developerc89c5472022-08-02 13:00:04 +08008 dma.c | 250 ++++++++++++++++++++++++++++++++++++++--------
9 dma.h | 10 ++
10 mac80211.c | 8 +-
developer20126ad2022-09-12 14:42:56 +080011 mt76.h | 24 ++++-
developerc89c5472022-08-02 13:00:04 +080012 mt7603/dma.c | 2 +-
13 mt7603/mt7603.h | 2 +-
14 mt7615/mac.c | 2 +-
15 mt7615/mt7615.h | 2 +-
16 mt76_connac_mcu.c | 9 ++
17 mt76x02.h | 2 +-
18 mt76x02_txrx.c | 2 +-
19 mt7915/dma.c | 25 +++--
developerc89c5472022-08-02 13:00:04 +080020 mt7915/mac.c | 103 ++++++++++++++++++-
developer20126ad2022-09-12 14:42:56 +080021 mt7915/mcu.c | 3 +
developerc89c5472022-08-02 13:00:04 +080022 mt7915/mmio.c | 26 ++++-
developer20126ad2022-09-12 14:42:56 +080023 mt7915/mt7915.h | 7 +-
developerc89c5472022-08-02 13:00:04 +080024 mt7915/regs.h | 14 ++-
25 mt7921/mac.c | 2 +-
26 mt7921/mt7921.h | 4 +-
27 mt7921/pci_mac.c | 4 +-
28 tx.c | 34 +++++++
developer20126ad2022-09-12 14:42:56 +080029 21 files changed, 460 insertions(+), 75 deletions(-)
developer3262bf82022-07-12 11:37:54 +080030
31diff --git a/dma.c b/dma.c
developer27b55252022-09-05 19:09:45 +080032index 8ea09e6..3317d2b 100644
developer3262bf82022-07-12 11:37:54 +080033--- a/dma.c
34+++ b/dma.c
35@@ -98,6 +98,63 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
36 }
37 EXPORT_SYMBOL_GPL(mt76_put_txwi);
38
39+static struct mt76_txwi_cache *
40+mt76_alloc_rxwi(struct mt76_dev *dev)
41+{
42+ struct mt76_txwi_cache *r;
43+ int size;
44+
45+ size = L1_CACHE_ALIGN(sizeof(*r));
46+ r = kzalloc(size, GFP_ATOMIC);
47+ if (!r)
48+ return NULL;
49+
50+ r->buf = NULL;
51+
52+ return r;
53+}
54+
55+static struct mt76_txwi_cache *
56+__mt76_get_rxwi(struct mt76_dev *dev)
57+{
58+ struct mt76_txwi_cache *r = NULL;
59+
60+ spin_lock(&dev->wed_lock);
61+ if (!list_empty(&dev->rxwi_cache)) {
62+ r = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
63+ list);
64+ if(r)
65+ list_del(&r->list);
66+ }
67+ spin_unlock(&dev->wed_lock);
68+
69+ return r;
70+}
71+
72+struct mt76_txwi_cache *
73+mt76_get_rxwi(struct mt76_dev *dev)
74+{
75+ struct mt76_txwi_cache *r = __mt76_get_rxwi(dev);
76+
77+ if (r)
78+ return r;
79+
80+ return mt76_alloc_rxwi(dev);
81+}
82+EXPORT_SYMBOL_GPL(mt76_get_rxwi);
83+
84+void
85+mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *r)
86+{
87+ if (!r)
88+ return;
89+
90+ spin_lock(&dev->wed_lock);
91+ list_add(&r->list, &dev->rxwi_cache);
92+ spin_unlock(&dev->wed_lock);
93+}
94+EXPORT_SYMBOL_GPL(mt76_put_rxwi);
95+
96 static void
97 mt76_free_pending_txwi(struct mt76_dev *dev)
98 {
developer29f66b32022-07-12 15:23:20 +080099@@ -112,6 +169,21 @@ mt76_free_pending_txwi(struct mt76_dev *dev)
100 local_bh_enable();
101 }
102
103+static void
104+mt76_free_pending_rxwi(struct mt76_dev *dev)
105+{
106+ struct mt76_txwi_cache *r;
107+
108+ local_bh_disable();
109+ while ((r = __mt76_get_rxwi(dev)) != NULL) {
110+ if (r->buf)
111+ skb_free_frag(r->buf);
112+
113+ kfree(r);
114+ }
115+ local_bh_enable();
116+}
117+
118 static void
119 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
120 {
121@@ -141,12 +213,15 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
developer3262bf82022-07-12 11:37:54 +0800122 static int
123 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
124 struct mt76_queue_buf *buf, int nbufs, u32 info,
125- struct sk_buff *skb, void *txwi)
126+ struct sk_buff *skb, void *txwi, void *rxwi)
127 {
128+ struct mtk_wed_device *wed = &dev->mmio.wed;
129+
130 struct mt76_queue_entry *entry;
131 struct mt76_desc *desc;
132 u32 ctrl;
133 int i, idx = -1;
134+ int type;
135
136 if (txwi) {
137 q->entry[q->head].txwi = DMA_DUMMY_DATA;
developer29f66b32022-07-12 15:23:20 +0800138@@ -162,28 +237,42 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
developer3262bf82022-07-12 11:37:54 +0800139 desc = &q->desc[idx];
140 entry = &q->entry[idx];
141
142- if (buf[0].skip_unmap)
143- entry->skip_buf0 = true;
144- entry->skip_buf1 = i == nbufs - 1;
145-
146- entry->dma_addr[0] = buf[0].addr;
147- entry->dma_len[0] = buf[0].len;
148-
149- ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
150- if (i < nbufs - 1) {
151- entry->dma_addr[1] = buf[1].addr;
152- entry->dma_len[1] = buf[1].len;
153- buf1 = buf[1].addr;
154- ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
155- if (buf[1].skip_unmap)
156- entry->skip_buf1 = true;
157+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
158+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
159+ struct mt76_txwi_cache *r = rxwi;
160+ int rx_token;
161+
162+ if (!r)
163+ return -ENOMEM;
164+
165+ rx_token = mt76_rx_token_consume(dev, (void *)skb, r, buf[0].addr);
166+
167+ buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
168+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, MTK_WED_RX_PKT_SIZE);
169+ ctrl |= MT_DMA_CTL_TO_HOST;
170+ } else {
171+ if (buf[0].skip_unmap)
172+ entry->skip_buf0 = true;
173+ entry->skip_buf1 = i == nbufs - 1;
174+
175+ entry->dma_addr[0] = buf[0].addr;
176+ entry->dma_len[0] = buf[0].len;
177+
178+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
179+ if (i < nbufs - 1) {
180+ entry->dma_addr[1] = buf[1].addr;
181+ entry->dma_len[1] = buf[1].len;
182+ buf1 = buf[1].addr;
183+ ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
184+ if (buf[1].skip_unmap)
185+ entry->skip_buf1 = true;
186+ }
187+ if (i == nbufs - 1)
188+ ctrl |= MT_DMA_CTL_LAST_SEC0;
189+ else if (i == nbufs - 2)
190+ ctrl |= MT_DMA_CTL_LAST_SEC1;
191 }
192
193- if (i == nbufs - 1)
194- ctrl |= MT_DMA_CTL_LAST_SEC0;
195- else if (i == nbufs - 2)
196- ctrl |= MT_DMA_CTL_LAST_SEC1;
197-
198 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
199 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
200 WRITE_ONCE(desc->info, cpu_to_le32(info));
developera15518e2022-07-25 19:03:42 +0800201@@ -272,33 +361,65 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
developer3262bf82022-07-12 11:37:54 +0800202
203 static void *
204 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
205- int *len, u32 *info, bool *more)
206+ int *len, u32 *info, bool *more, bool *drop)
207 {
208 struct mt76_queue_entry *e = &q->entry[idx];
209 struct mt76_desc *desc = &q->desc[idx];
210 dma_addr_t buf_addr;
developera15518e2022-07-25 19:03:42 +0800211- void *buf = e->buf;
212+ void *buf = e->buf, *copy = NULL;
developer3262bf82022-07-12 11:37:54 +0800213 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
214+ struct mtk_wed_device *wed = &dev->mmio.wed;
215+ int type;
216
217- buf_addr = e->dma_addr[0];
218 if (len) {
219 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
220 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
221 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
222 }
223
224- if (info)
225- *info = le32_to_cpu(desc->info);
226+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
227+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
228+ u32 token;
229+ struct mt76_txwi_cache *r;
230+
231+ token = FIELD_GET(MT_DMA_CTL_TOKEN, desc->buf1);
232+
233+ r = mt76_rx_token_release(dev, token);
234+ if (!r)
235+ return NULL;
236+
237+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
238+ if (!buf)
239+ return NULL;
240+
developera15518e2022-07-25 19:03:42 +0800241+ copy = r->buf;
developer3262bf82022-07-12 11:37:54 +0800242+ buf_addr = r->dma_addr;
243+ buf_len = MTK_WED_RX_PKT_SIZE;
244+ r->dma_addr = 0;
developer3262bf82022-07-12 11:37:54 +0800245+
246+ mt76_put_rxwi(dev, r);
247+
248+ if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
249+ *drop = true;
250+ } else {
251+ buf_addr = e->dma_addr[0];
252+ e->buf = NULL;
253+ }
254
255 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
256- e->buf = NULL;
257+
developera15518e2022-07-25 19:03:42 +0800258+ if (copy)
259+ memcpy(buf, copy, MTK_WED_RX_PKT_SIZE);
260+
developer3262bf82022-07-12 11:37:54 +0800261+ if (info)
262+ *info = le32_to_cpu(desc->info);
263
264 return buf;
265 }
266
267 static void *
268 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
269- int *len, u32 *info, bool *more)
270+ int *len, u32 *info, bool *more, bool *drop)
271 {
272 int idx = q->tail;
273
developerc89c5472022-08-02 13:00:04 +0800274@@ -314,7 +435,7 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
developer3262bf82022-07-12 11:37:54 +0800275 q->tail = (q->tail + 1) % q->ndesc;
276 q->queued--;
277
278- return mt76_dma_get_buf(dev, q, idx, len, info, more);
279+ return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
280 }
281
282 static int
developerc89c5472022-08-02 13:00:04 +0800283@@ -336,7 +457,7 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
developer3262bf82022-07-12 11:37:54 +0800284 buf.len = skb->len;
285
286 spin_lock_bh(&q->lock);
287- mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
288+ mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL);
289 mt76_dma_kick_queue(dev, q);
290 spin_unlock_bh(&q->lock);
291
developerc89c5472022-08-02 13:00:04 +0800292@@ -413,7 +534,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
developer3262bf82022-07-12 11:37:54 +0800293 goto unmap;
294
295 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
296- tx_info.info, tx_info.skb, t);
297+ tx_info.info, tx_info.skb, t, NULL);
298
299 unmap:
300 for (n--; n > 0; n--)
developerc89c5472022-08-02 13:00:04 +0800301@@ -448,6 +569,8 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer3262bf82022-07-12 11:37:54 +0800302 int frames = 0;
303 int len = SKB_WITH_OVERHEAD(q->buf_size);
304 int offset = q->buf_offset;
305+ struct mtk_wed_device *wed = &dev->mmio.wed;
developer29f66b32022-07-12 15:23:20 +0800306+ struct page_frag_cache *rx_page;
developer3262bf82022-07-12 11:37:54 +0800307
308 if (!q->ndesc)
309 return 0;
developerc89c5472022-08-02 13:00:04 +0800310@@ -456,10 +579,29 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer3262bf82022-07-12 11:37:54 +0800311
312 while (q->queued < q->ndesc - 1) {
313 struct mt76_queue_buf qbuf;
314+ int type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
315+ bool skip_alloc = false;
316+ struct mt76_txwi_cache *r = NULL;
317+
developer29f66b32022-07-12 15:23:20 +0800318+ rx_page = &q->rx_page;
developer3262bf82022-07-12 11:37:54 +0800319+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
developer29f66b32022-07-12 15:23:20 +0800320+ rx_page = &wed->rx_page;
developer3262bf82022-07-12 11:37:54 +0800321+ r = mt76_get_rxwi(dev);
322+ if (!r)
323+ return -ENOMEM;
324+
325+ if (r->buf) {
326+ skip_alloc = true;
327+ len = MTK_WED_RX_PKT_SIZE;
328+ buf = r->buf;
329+ }
330+ }
331
332- buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
333- if (!buf)
334- break;
335+ if (!skip_alloc) {
developer29f66b32022-07-12 15:23:20 +0800336+ buf = page_frag_alloc(rx_page, q->buf_size, GFP_ATOMIC);
developer3262bf82022-07-12 11:37:54 +0800337+ if (!buf)
338+ break;
339+ }
340
341 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
342 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
developerc89c5472022-08-02 13:00:04 +0800343@@ -470,7 +612,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer3262bf82022-07-12 11:37:54 +0800344 qbuf.addr = addr + offset;
345 qbuf.len = len - offset;
346 qbuf.skip_unmap = false;
347- mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
348+ mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL, r);
349 frames++;
350 }
351
developerc89c5472022-08-02 13:00:04 +0800352@@ -516,6 +658,11 @@ mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
developer3262bf82022-07-12 11:37:54 +0800353 if (!ret)
354 q->wed_regs = wed->txfree_ring.reg_base;
355 break;
356+ case MT76_WED_Q_RX:
357+ ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
358+ if (!ret)
359+ q->wed_regs = wed->rx_ring[ring].reg_base;
360+ break;
361 default:
362 ret = -EINVAL;
363 }
developerc89c5472022-08-02 13:00:04 +0800364@@ -531,7 +678,8 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer3262bf82022-07-12 11:37:54 +0800365 int idx, int n_desc, int bufsize,
366 u32 ring_base)
367 {
368- int ret, size;
369+ int ret, size, type;
370+ struct mtk_wed_device *wed = &dev->mmio.wed;
371
372 spin_lock_init(&q->lock);
373 spin_lock_init(&q->cleanup_lock);
developerc89c5472022-08-02 13:00:04 +0800374@@ -541,6 +689,11 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer3262bf82022-07-12 11:37:54 +0800375 q->buf_size = bufsize;
376 q->hw_idx = idx;
377
378+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
379+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX)
380+ q->buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + MTK_WED_RX_PKT_SIZE) +
381+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
382+
383 size = q->ndesc * sizeof(struct mt76_desc);
384 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
385 if (!q->desc)
developerc89c5472022-08-02 13:00:04 +0800386@@ -573,7 +726,7 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
developer3262bf82022-07-12 11:37:54 +0800387
388 spin_lock_bh(&q->lock);
389 do {
390- buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
391+ buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
392 if (!buf)
393 break;
394
developerc89c5472022-08-02 13:00:04 +0800395@@ -614,7 +767,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
developer3262bf82022-07-12 11:37:54 +0800396
397 static void
398 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
399- int len, bool more)
400+ int len, bool more, u32 info)
401 {
402 struct sk_buff *skb = q->rx_head;
403 struct skb_shared_info *shinfo = skb_shinfo(skb);
developerc89c5472022-08-02 13:00:04 +0800404@@ -634,7 +787,7 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
developer3262bf82022-07-12 11:37:54 +0800405
406 q->rx_head = NULL;
407 if (nr_frags < ARRAY_SIZE(shinfo->frags))
408- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
409+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
410 else
411 dev_kfree_skb(skb);
412 }
developerc89c5472022-08-02 13:00:04 +0800413@@ -655,6 +808,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer3262bf82022-07-12 11:37:54 +0800414 }
415
416 while (done < budget) {
417+ bool drop = false;
418 u32 info;
419
420 if (check_ddone) {
developerc89c5472022-08-02 13:00:04 +0800421@@ -665,10 +819,13 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer3262bf82022-07-12 11:37:54 +0800422 break;
423 }
424
425- data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
426+ data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop);
427 if (!data)
428 break;
429
430+ if (drop)
431+ goto free_frag;
432+
433 if (q->rx_head)
434 data_len = q->buf_size;
435 else
developerc89c5472022-08-02 13:00:04 +0800436@@ -681,7 +838,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer3262bf82022-07-12 11:37:54 +0800437 }
438
439 if (q->rx_head) {
440- mt76_add_fragment(dev, q, data, len, more);
441+ mt76_add_fragment(dev, q, data, len, more, info);
442 continue;
443 }
444
developerc89c5472022-08-02 13:00:04 +0800445@@ -708,7 +865,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer3262bf82022-07-12 11:37:54 +0800446 continue;
447 }
448
449- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
450+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
451 continue;
452
453 free_frag:
developerc89c5472022-08-02 13:00:04 +0800454@@ -785,7 +942,7 @@ EXPORT_SYMBOL_GPL(mt76_dma_attach);
developer29f66b32022-07-12 15:23:20 +0800455
456 void mt76_dma_cleanup(struct mt76_dev *dev)
457 {
458- int i;
developer29f66b32022-07-12 15:23:20 +0800459+ int i, type;
developerd4975692022-07-15 18:30:03 +0800460
developer29f66b32022-07-12 15:23:20 +0800461 mt76_worker_disable(&dev->tx_worker);
462 netif_napi_del(&dev->tx_napi);
developer4df64ba2022-09-01 14:44:55 +0800463@@ -806,12 +963,17 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
developer29f66b32022-07-12 15:23:20 +0800464
465 mt76_for_each_q_rx(dev, i) {
466 netif_napi_del(&dev->napi[i]);
467- mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
468+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->q_rx[i].flags);
469+ if (type != MT76_WED_Q_RX)
470+ mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
471 }
472
473 mt76_free_pending_txwi(dev);
474+ mt76_free_pending_rxwi(dev);
475
476 if (mtk_wed_device_active(&dev->mmio.wed))
477 mtk_wed_device_detach(&dev->mmio.wed);
478+
479+ mt76_free_pending_rxwi(dev);
480 }
481 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
developer3262bf82022-07-12 11:37:54 +0800482diff --git a/dma.h b/dma.h
developer27b55252022-09-05 19:09:45 +0800483index fdf786f..90370d1 100644
developer3262bf82022-07-12 11:37:54 +0800484--- a/dma.h
485+++ b/dma.h
486@@ -16,6 +16,16 @@
487 #define MT_DMA_CTL_LAST_SEC0 BIT(30)
488 #define MT_DMA_CTL_DMA_DONE BIT(31)
489
490+#define MT_DMA_CTL_TO_HOST BIT(8)
491+#define MT_DMA_CTL_TO_HOST_A BIT(12)
492+#define MT_DMA_CTL_DROP BIT(14)
493+
494+#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
495+
496+#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
497+#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
498+#define MT_DMA_INFO_PPE_VLD BIT(31)
499+
500 #define MT_DMA_HDR_LEN 4
501 #define MT_RX_INFO_LEN 4
502 #define MT_FCE_INFO_LEN 4
503diff --git a/mac80211.c b/mac80211.c
developer20126ad2022-09-12 14:42:56 +0800504index 4eaf317..731b78f 100644
developer3262bf82022-07-12 11:37:54 +0800505--- a/mac80211.c
506+++ b/mac80211.c
developer20126ad2022-09-12 14:42:56 +0800507@@ -599,11 +599,14 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
developer3262bf82022-07-12 11:37:54 +0800508 BIT(NL80211_IFTYPE_ADHOC);
509
510 spin_lock_init(&dev->token_lock);
511+ spin_lock_init(&dev->rx_token_lock);
512 idr_init(&dev->token);
513+ idr_init(&dev->rx_token);
514
515 INIT_LIST_HEAD(&dev->wcid_list);
516
517 INIT_LIST_HEAD(&dev->txwi_cache);
518+ INIT_LIST_HEAD(&dev->rxwi_cache);
519 dev->token_size = dev->drv->token_size;
520
521 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
developer20126ad2022-09-12 14:42:56 +0800522@@ -1301,7 +1304,10 @@ void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developer3262bf82022-07-12 11:37:54 +0800523
524 while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) {
525 mt76_check_sta(dev, skb);
526- mt76_rx_aggr_reorder(skb, &frames);
527+ if (mtk_wed_device_active(&dev->mmio.wed))
528+ __skb_queue_tail(&frames, skb);
529+ else
530+ mt76_rx_aggr_reorder(skb, &frames);
531 }
532
533 mt76_rx_complete(dev, &frames, napi);
534diff --git a/mt76.h b/mt76.h
developer20126ad2022-09-12 14:42:56 +0800535index b7da992..20fd0ec 100644
developer3262bf82022-07-12 11:37:54 +0800536--- a/mt76.h
537+++ b/mt76.h
538@@ -20,6 +20,8 @@
539
540 #define MT_MCU_RING_SIZE 32
541 #define MT_RX_BUF_SIZE 2048
542+#define MTK_WED_RX_PKT_SIZE 1700
543+
544 #define MT_SKB_HEAD_LEN 256
545
546 #define MT_MAX_NON_AQL_PKT 16
547@@ -35,6 +37,7 @@
548 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
549 FIELD_PREP(MT_QFLAG_WED_RING, _n))
550 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
551+#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
552 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
553
554 struct mt76_dev;
555@@ -56,6 +59,7 @@ enum mt76_bus_type {
556 enum mt76_wed_type {
557 MT76_WED_Q_TX,
558 MT76_WED_Q_TXFREE,
559+ MT76_WED_Q_RX,
560 };
561
562 struct mt76_bus_ops {
developer4df64ba2022-09-01 14:44:55 +0800563@@ -313,7 +317,10 @@ struct mt76_txwi_cache {
developer3262bf82022-07-12 11:37:54 +0800564 struct list_head list;
565 dma_addr_t dma_addr;
566
567- struct sk_buff *skb;
568+ union {
569+ void *buf;
570+ struct sk_buff *skb;
571+ };
572 };
573
574 struct mt76_rx_tid {
developer4df64ba2022-09-01 14:44:55 +0800575@@ -411,7 +418,7 @@ struct mt76_driver_ops {
developer3262bf82022-07-12 11:37:54 +0800576 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
577
578 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
579- struct sk_buff *skb);
580+ struct sk_buff *skb, u32 info);
581
582 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
583
developer20126ad2022-09-12 14:42:56 +0800584@@ -757,6 +764,7 @@ struct mt76_dev {
developer3262bf82022-07-12 11:37:54 +0800585 struct ieee80211_hw *hw;
586
587 spinlock_t lock;
588+ spinlock_t wed_lock;
589 spinlock_t cc_lock;
590
591 u32 cur_cc_bss_rx;
developer20126ad2022-09-12 14:42:56 +0800592@@ -782,6 +790,7 @@ struct mt76_dev {
developer3262bf82022-07-12 11:37:54 +0800593 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
594
595 struct list_head txwi_cache;
596+ struct list_head rxwi_cache;
597 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
598 struct mt76_queue q_rx[__MT_RXQ_MAX];
599 const struct mt76_queue_ops *queue_ops;
developer20126ad2022-09-12 14:42:56 +0800600@@ -795,6 +804,9 @@ struct mt76_dev {
developer3262bf82022-07-12 11:37:54 +0800601 u16 wed_token_count;
602 u16 token_count;
603 u16 token_size;
604+ u16 rx_token_size;
605+ spinlock_t rx_token_lock;
606+ struct idr rx_token;
607
608 wait_queue_head_t tx_wait;
609 /* spinclock used to protect wcid pktid linked list */
developer20126ad2022-09-12 14:42:56 +0800610@@ -1359,6 +1371,8 @@ mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
developer3262bf82022-07-12 11:37:54 +0800611 }
612
613 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
614+void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
615+struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
616 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
617 struct napi_struct *napi);
618 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developer20126ad2022-09-12 14:42:56 +0800619@@ -1503,6 +1517,12 @@ struct mt76_txwi_cache *
developer3262bf82022-07-12 11:37:54 +0800620 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
621 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
622 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
623+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
624+ struct mt76_txwi_cache *r, dma_addr_t phys);
625+void skb_trace(const struct sk_buff *skb, bool full_pkt);
626+
627+struct mt76_txwi_cache *
628+mt76_rx_token_release(struct mt76_dev *dev, int token);
629
630 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
631 {
632diff --git a/mt7603/dma.c b/mt7603/dma.c
developer27b55252022-09-05 19:09:45 +0800633index 590cff9..2ff71c5 100644
developer3262bf82022-07-12 11:37:54 +0800634--- a/mt7603/dma.c
635+++ b/mt7603/dma.c
636@@ -69,7 +69,7 @@ free:
637 }
638
639 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
640- struct sk_buff *skb)
641+ struct sk_buff *skb, u32 info)
642 {
643 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
644 __le32 *rxd = (__le32 *)skb->data;
645diff --git a/mt7603/mt7603.h b/mt7603/mt7603.h
developer27b55252022-09-05 19:09:45 +0800646index 0fd46d9..f2ce22a 100644
developer3262bf82022-07-12 11:37:54 +0800647--- a/mt7603/mt7603.h
648+++ b/mt7603/mt7603.h
649@@ -244,7 +244,7 @@ int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
650 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
651
652 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
653- struct sk_buff *skb);
654+ struct sk_buff *skb, u32 info);
655 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
656 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
657 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
658diff --git a/mt7615/mac.c b/mt7615/mac.c
developer27b55252022-09-05 19:09:45 +0800659index d6aae60..4774eaa 100644
developer3262bf82022-07-12 11:37:54 +0800660--- a/mt7615/mac.c
661+++ b/mt7615/mac.c
developer4df64ba2022-09-01 14:44:55 +0800662@@ -1651,7 +1651,7 @@ bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
developer3262bf82022-07-12 11:37:54 +0800663 EXPORT_SYMBOL_GPL(mt7615_rx_check);
664
665 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
666- struct sk_buff *skb)
667+ struct sk_buff *skb, u32 info)
668 {
669 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
670 __le32 *rxd = (__le32 *)skb->data;
671diff --git a/mt7615/mt7615.h b/mt7615/mt7615.h
developer27b55252022-09-05 19:09:45 +0800672index 060d52c..232b0f2 100644
developer3262bf82022-07-12 11:37:54 +0800673--- a/mt7615/mt7615.h
674+++ b/mt7615/mt7615.h
675@@ -511,7 +511,7 @@ void mt7615_tx_worker(struct mt76_worker *w);
676 void mt7615_tx_token_put(struct mt7615_dev *dev);
677 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len);
678 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
679- struct sk_buff *skb);
680+ struct sk_buff *skb, u32 info);
681 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
682 int mt7615_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
683 struct ieee80211_sta *sta);
684diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developer27b55252022-09-05 19:09:45 +0800685index e701db8..6ae1159 100644
developer3262bf82022-07-12 11:37:54 +0800686--- a/mt76_connac_mcu.c
687+++ b/mt76_connac_mcu.c
688@@ -1190,6 +1190,7 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
689 int cmd, bool enable, bool tx)
690 {
691 struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv;
692+ struct mtk_wed_device *wed = &dev->mmio.wed;
693 struct wtbl_req_hdr *wtbl_hdr;
694 struct tlv *sta_wtbl;
695 struct sk_buff *skb;
696@@ -1210,6 +1211,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
697 mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl,
698 wtbl_hdr);
699
700+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
701+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
702 ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true);
703 if (ret)
704 return ret;
705@@ -1220,6 +1223,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
706
707 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
708
709+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
710+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
711 return mt76_mcu_skb_send_msg(dev, skb, cmd, true);
712 }
713 EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba);
714@@ -2634,6 +2639,7 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
715 struct mt76_wcid *wcid, enum set_key_cmd cmd)
716 {
717 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
718+ struct mtk_wed_device *wed = &dev->mmio.wed;
719 struct sk_buff *skb;
720 int ret;
721
722@@ -2645,6 +2651,9 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
723 if (ret)
724 return ret;
725
726+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
727+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
728+
729 return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true);
730 }
731 EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key);
732diff --git a/mt76x02.h b/mt76x02.h
developer27b55252022-09-05 19:09:45 +0800733index f76fd22..0b872af 100644
developer3262bf82022-07-12 11:37:54 +0800734--- a/mt76x02.h
735+++ b/mt76x02.h
736@@ -173,7 +173,7 @@ int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
737 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
738 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
739 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
740- struct sk_buff *skb);
741+ struct sk_buff *skb, u32 info);
742 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
743 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
744 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
745diff --git a/mt76x02_txrx.c b/mt76x02_txrx.c
developer27b55252022-09-05 19:09:45 +0800746index 96fdf42..bf24d3e 100644
developer3262bf82022-07-12 11:37:54 +0800747--- a/mt76x02_txrx.c
748+++ b/mt76x02_txrx.c
749@@ -33,7 +33,7 @@ void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
750 EXPORT_SYMBOL_GPL(mt76x02_tx);
751
752 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
753- struct sk_buff *skb)
754+ struct sk_buff *skb, u32 info)
755 {
756 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
757 void *rxwi = skb->data;
758diff --git a/mt7915/dma.c b/mt7915/dma.c
developer27b55252022-09-05 19:09:45 +0800759index ac30698..197a016 100644
developer3262bf82022-07-12 11:37:54 +0800760--- a/mt7915/dma.c
761+++ b/mt7915/dma.c
developer4df64ba2022-09-01 14:44:55 +0800762@@ -349,6 +349,7 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
developerc89c5472022-08-02 13:00:04 +0800763 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
764 {
765 struct mt76_dev *mdev = &dev->mt76;
766+ struct mtk_wed_device *wed = &mdev->mmio.wed;
767 u32 wa_rx_base, wa_rx_idx;
768 u32 hif1_ofs = 0;
769 int ret;
developer4df64ba2022-09-01 14:44:55 +0800770@@ -365,10 +366,12 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developerc89c5472022-08-02 13:00:04 +0800771 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && !is_mt7986(mdev)) {
772 mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
773 if(is_mt7915(mdev)) {
774- mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
775- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
776- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
777- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
778+ mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
779+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
780+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
781+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
782+ mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
783+ MT_WFDMA0_EXT0_RXWB_KEEP);
developer3262bf82022-07-12 11:37:54 +0800784 } else {
785 mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
786 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
developer4df64ba2022-09-01 14:44:55 +0800787@@ -428,7 +431,7 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developerc89c5472022-08-02 13:00:04 +0800788 return ret;
789
790 /* event from WA */
791- if (mtk_wed_device_active(&dev->mt76.mmio.wed) && is_mt7915(mdev)) {
792+ if (mtk_wed_device_active(wed) && is_mt7915(mdev)) {
793 wa_rx_base = MT_WED_RX_RING_BASE;
794 wa_rx_idx = MT7915_RXQ_MCU_WA;
795 dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE;
developer4df64ba2022-09-01 14:44:55 +0800796@@ -444,6 +447,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer3262bf82022-07-12 11:37:54 +0800797
798 /* rx data queue for band0 */
799 if (!dev->phy.band_idx) {
developerc89c5472022-08-02 13:00:04 +0800800+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1) {
developer3262bf82022-07-12 11:37:54 +0800801+ dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0);
developerc89c5472022-08-02 13:00:04 +0800802+ dev->mt76.rx_token_size += MT7915_RX_RING_SIZE;
803+ }
developer3262bf82022-07-12 11:37:54 +0800804+
805 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
806 MT_RXQ_ID(MT_RXQ_MAIN),
807 MT7915_RX_RING_SIZE,
developer4df64ba2022-09-01 14:44:55 +0800808@@ -458,7 +466,7 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developerc89c5472022-08-02 13:00:04 +0800809 wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA);
810 wa_rx_idx = MT_RXQ_ID(MT_RXQ_MAIN_WA);
811
812- if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
813+ if (mtk_wed_device_active(wed)) {
814 dev->mt76.q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE;
815 if (is_mt7916(mdev)) {
816 wa_rx_base = MT_WED_RX_RING_BASE;
developer4df64ba2022-09-01 14:44:55 +0800817@@ -474,6 +482,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
818 }
developer3262bf82022-07-12 11:37:54 +0800819
820 if (dev->dbdc_support || dev->phy.band_idx) {
developerc89c5472022-08-02 13:00:04 +0800821+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1) {
developer4df64ba2022-09-01 14:44:55 +0800822+ dev->mt76.q_rx[MT_RXQ_BAND1].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1);
developerc89c5472022-08-02 13:00:04 +0800823+ dev->mt76.rx_token_size += MT7915_RX_RING_SIZE;
824+ }
developer3262bf82022-07-12 11:37:54 +0800825+
developer4df64ba2022-09-01 14:44:55 +0800826 /* rx data queue for band1 */
827 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],
828 MT_RXQ_ID(MT_RXQ_BAND1),
developer3262bf82022-07-12 11:37:54 +0800829diff --git a/mt7915/mac.c b/mt7915/mac.c
developer27b55252022-09-05 19:09:45 +0800830index 0a13b7d..4e1dfc9 100644
developer3262bf82022-07-12 11:37:54 +0800831--- a/mt7915/mac.c
832+++ b/mt7915/mac.c
833@@ -217,7 +217,7 @@ static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
834 }
835
836 static int
837-mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
838+mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 info)
839 {
840 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
841 struct mt76_phy *mphy = &dev->mt76.phy;
developer29f66b32022-07-12 15:23:20 +0800842@@ -234,7 +234,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
843 bool unicast, insert_ccmp_hdr = false;
844 u8 remove_pad, amsdu_info;
845 u8 mode = 0, qos_ctl = 0;
846- struct mt7915_sta *msta;
847+ struct mt7915_sta *msta = NULL;
848 bool hdr_trans;
849 u16 hdr_gap;
850 u16 seq_ctrl = 0;
developer3262bf82022-07-12 11:37:54 +0800851@@ -494,6 +494,27 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
852 #endif
853 } else {
854 status->flag |= RX_FLAG_8023;
developer29f66b32022-07-12 15:23:20 +0800855+ if (msta && msta->vif) {
developer3262bf82022-07-12 11:37:54 +0800856+ struct mtk_wed_device *wed;
857+ int type;
858+
859+ wed = &dev->mt76.mmio.wed;
860+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->mt76.q_rx[q].flags);
861+ if ((mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) &&
developer29f66b32022-07-12 15:23:20 +0800862+ (info & MT_DMA_INFO_PPE_VLD)) {
developer3262bf82022-07-12 11:37:54 +0800863+ struct ieee80211_vif *vif;
864+ u32 hash, reason;
865+
866+ vif = container_of((void *)msta->vif, struct ieee80211_vif,
developer29f66b32022-07-12 15:23:20 +0800867+ drv_priv);
developer3262bf82022-07-12 11:37:54 +0800868+
869+ skb->dev = ieee80211_vif_to_netdev(vif);
870+ reason = FIELD_GET(MT_DMA_PPE_CPU_REASON, info);
871+ hash = FIELD_GET(MT_DMA_PPE_ENTRY, info);
872+
873+ mtk_wed_device_ppe_check(wed, skb, reason, hash);
874+ }
875+ }
876 }
877
878 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
developer4df64ba2022-09-01 14:44:55 +0800879@@ -831,6 +852,80 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer3262bf82022-07-12 11:37:54 +0800880 return MT_TXD_TXP_BUF_SIZE;
881 }
882
883+u32
884+mt7915_wed_init_rx_buf(struct mtk_wed_device *wed, int pkt_num)
885+{
886+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
887+ struct mt7915_dev *dev;
888+ dma_addr_t buf_phys;
889+ void *buf;
890+ int i, token, buf_size;
891+
892+ buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_pkt_size) +
893+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
894+
895+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
896+ for (i = 0; i < pkt_num; i++) {
897+ struct mt76_txwi_cache *r = mt76_get_rxwi(&dev->mt76);
898+
899+ buf = page_frag_alloc(&wed->rx_page, buf_size, GFP_ATOMIC);
900+ if (!buf)
901+ return -ENOMEM;
902+
903+ buf_phys = dma_map_single(dev->mt76.dma_dev, buf, wed->wlan.rx_pkt_size,
904+ DMA_TO_DEVICE);
905+
906+ if (unlikely(dma_mapping_error(dev->mt76.dev, buf_phys))) {
907+ skb_free_frag(buf);
908+ break;
909+ }
910+
911+ desc->buf0 = buf_phys;
912+
913+ token = mt76_rx_token_consume(&dev->mt76, buf, r, buf_phys);
914+
915+ desc->token |= FIELD_PREP(MT_DMA_CTL_TOKEN, token);
916+ desc++;
917+ }
918+
919+ return 0;
920+}
921+
922+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed)
923+{
924+ struct mt76_txwi_cache *rxwi;
925+ struct mt7915_dev *dev;
developer29f66b32022-07-12 15:23:20 +0800926+ struct page *page;
developer3262bf82022-07-12 11:37:54 +0800927+ int token;
928+
929+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
930+
931+ for(token = 0; token < dev->mt76.rx_token_size; token++) {
932+ rxwi = mt76_rx_token_release(&dev->mt76, token);
933+ if(!rxwi)
934+ continue;
935+
developer29f66b32022-07-12 15:23:20 +0800936+ if(!rxwi->buf)
937+ continue;
938+
developer3262bf82022-07-12 11:37:54 +0800939+ dma_unmap_single(dev->mt76.dma_dev, rxwi->dma_addr,
940+ wed->wlan.rx_pkt_size, DMA_FROM_DEVICE);
941+ skb_free_frag(rxwi->buf);
942+ rxwi->buf = NULL;
943+
944+ mt76_put_rxwi(&dev->mt76, rxwi);
945+ }
developer29f66b32022-07-12 15:23:20 +0800946+
947+ if (wed->rx_page.va)
948+ return;
949+
950+ page = virt_to_page(wed->rx_page.va);
951+ __page_frag_cache_drain(page, wed->rx_page.pagecnt_bias);
952+ memset(&wed->rx_page, 0, sizeof(wed->rx_page));
953+
developer3262bf82022-07-12 11:37:54 +0800954+ return;
955+}
956+
957 static void
958 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
959 {
developer4df64ba2022-09-01 14:44:55 +0800960@@ -1107,7 +1202,7 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developer3262bf82022-07-12 11:37:54 +0800961 }
962
963 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
964- struct sk_buff *skb)
965+ struct sk_buff *skb, u32 info)
966 {
967 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
968 __le32 *rxd = (__le32 *)skb->data;
developer4df64ba2022-09-01 14:44:55 +0800969@@ -1141,7 +1236,7 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developer3262bf82022-07-12 11:37:54 +0800970 dev_kfree_skb(skb);
971 break;
972 case PKT_TYPE_NORMAL:
973- if (!mt7915_mac_fill_rx(dev, skb)) {
974+ if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
975 mt76_rx(&dev->mt76, q, skb);
976 return;
977 }
978diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer20126ad2022-09-12 14:42:56 +0800979index 73efa55..22f68da 100644
developer3262bf82022-07-12 11:37:54 +0800980--- a/mt7915/mcu.c
981+++ b/mt7915/mcu.c
developer27b55252022-09-05 19:09:45 +0800982@@ -1722,6 +1722,7 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer3262bf82022-07-12 11:37:54 +0800983 struct ieee80211_sta *sta, bool enable)
984 {
985 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
986+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
987 struct mt7915_sta *msta;
988 struct sk_buff *skb;
989 int ret;
developer27b55252022-09-05 19:09:45 +0800990@@ -1774,6 +1775,8 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer3262bf82022-07-12 11:37:54 +0800991 return ret;
992 }
993 out:
994+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
995+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
996 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
997 MCU_EXT_CMD(STA_REC_UPDATE), true);
998 }
999diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer27b55252022-09-05 19:09:45 +08001000index b0d8a61..111444d 100644
developer3262bf82022-07-12 11:37:54 +08001001--- a/mt7915/mmio.c
1002+++ b/mt7915/mmio.c
1003@@ -28,6 +28,9 @@ static const u32 mt7915_reg[] = {
1004 [FW_EXCEPTION_ADDR] = 0x219848,
1005 [SWDEF_BASE_ADDR] = 0x41f200,
1006 [EXCEPTION_BASE_ADDR] = 0x219848,
1007+ [WED_TX_RING] = 0xd7300,
1008+ [WED_RX_RING] = 0xd7410,
1009+ [WED_RX_DATA_RING] = 0xd4500,
1010 };
1011
1012 static const u32 mt7916_reg[] = {
1013@@ -45,6 +48,9 @@ static const u32 mt7916_reg[] = {
1014 [FW_EXCEPTION_ADDR] = 0x022050bc,
1015 [SWDEF_BASE_ADDR] = 0x411400,
1016 [EXCEPTION_BASE_ADDR] = 0x022050BC,
1017+ [WED_TX_RING] = 0xd7300,
1018+ [WED_RX_RING] = 0xd7410,
1019+ [WED_RX_DATA_RING] = 0xd4540,
1020 };
1021
1022 static const u32 mt7986_reg[] = {
1023@@ -62,6 +68,9 @@ static const u32 mt7986_reg[] = {
1024 [FW_EXCEPTION_ADDR] = 0x02204ffc,
1025 [SWDEF_BASE_ADDR] = 0x411400,
1026 [EXCEPTION_BASE_ADDR] = 0x02204FFC,
1027+ [WED_TX_RING] = 0x24420,
1028+ [WED_RX_RING] = 0x24520,
1029+ [WED_RX_DATA_RING] = 0x24540,
1030 };
1031
1032 static const u32 mt7915_offs[] = {
1033@@ -710,6 +719,7 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
1034 wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
1035 wed->wlan.wpdma_int = base + MT_INT_WED_SOURCE_CSR;
1036 wed->wlan.wpdma_mask = base + MT_INT_WED_MASK_CSR;
1037+ wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1038 } else {
1039 struct platform_device *plat_dev;
1040 struct resource *res;
1041@@ -722,12 +732,19 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
1042 wed->wlan.wpdma_int = base + MT_INT_SOURCE_CSR;
1043 wed->wlan.wpdma_mask = base + MT_INT_MASK_CSR;
1044 }
1045+ wed->wlan.rx_pkt = MT7915_WED_RX_TOKEN_SIZE;
1046+ wed->wlan.phy_base = base;
1047 wed->wlan.wpdma_tx = base + MT_TXQ_WED_RING_BASE;
1048 wed->wlan.wpdma_txfree = base + MT_RXQ_WED_RING_BASE;
1049+ wed->wlan.wpdma_rx_glo = base + MT_WPDMA_GLO_CFG;
1050+ wed->wlan.wpdma_rx = base + MT_RXQ_WED_DATA_RING_BASE;
1051
1052 wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0;
1053 wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1;
1054 wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE;
1055+ wed->wlan.rx_tbit[0] = MT_WED_RX_DONE_BAND0;
1056+ wed->wlan.rx_tbit[1] = MT_WED_RX_DONE_BAND1;
1057+
1058 wed->wlan.nbuf = 7168;
1059 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
1060 wed->wlan.init_buf = mt7915_wed_init_buf;
1061@@ -735,12 +752,15 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
1062 wed->wlan.offload_enable = mt7915_wed_offload_enable;
1063 wed->wlan.offload_disable = mt7915_wed_offload_disable;
1064
1065+ wed->wlan.rx_nbuf = 65536;
1066+ wed->wlan.rx_pkt_size = MTK_WED_RX_PKT_SIZE;
1067+ wed->wlan.init_rx_buf = mt7915_wed_init_rx_buf;
1068+ wed->wlan.release_rx_buf = mt7915_wed_release_rx_buf;
1069+
developerc89c5472022-08-02 13:00:04 +08001070+ dev->mt76.rx_token_size = wed->wlan.rx_pkt;
developer3262bf82022-07-12 11:37:54 +08001071 if (mtk_wed_device_attach(wed) != 0)
1072 return 0;
1073
1074- if (wed->ver == MTK_WED_V1)
1075- wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1076-
1077 *irq = wed->irq;
1078 dev->mt76.dma_dev = wed->dev;
1079 mdev->token_size = wed->wlan.token_start;
1080diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer20126ad2022-09-12 14:42:56 +08001081index 33c00af..b805aae 100644
developer3262bf82022-07-12 11:37:54 +08001082--- a/mt7915/mt7915.h
1083+++ b/mt7915/mt7915.h
developer20126ad2022-09-12 14:42:56 +08001084@@ -81,6 +81,7 @@
developer3262bf82022-07-12 11:37:54 +08001085 #define MT7915_MAX_STA_TWT_AGRT 8
1086 #define MT7915_MIN_TWT_DUR 64
developer4df64ba2022-09-01 14:44:55 +08001087 #define MT7915_MAX_QUEUE (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2)
developer3262bf82022-07-12 11:37:54 +08001088+#define MT7915_WED_RX_TOKEN_SIZE 12288
1089
1090 struct mt7915_vif;
1091 struct mt7915_sta;
developer20126ad2022-09-12 14:42:56 +08001092@@ -547,7 +548,9 @@ void mt7915_wfsys_reset(struct mt7915_dev *dev);
developer3262bf82022-07-12 11:37:54 +08001093 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
1094 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
1095 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
1096-
1097+u32 mt7915_wed_init_rx_buf(struct mtk_wed_device *wed,
1098+ int pkt_num);
1099+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed);
1100 int mt7915_register_device(struct mt7915_dev *dev);
1101 void mt7915_unregister_device(struct mt7915_dev *dev);
1102 int mt7915_eeprom_init(struct mt7915_dev *dev);
developer20126ad2022-09-12 14:42:56 +08001103@@ -700,7 +703,7 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer3262bf82022-07-12 11:37:54 +08001104 struct mt76_tx_info *tx_info);
1105 void mt7915_tx_token_put(struct mt7915_dev *dev);
1106 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1107- struct sk_buff *skb);
1108+ struct sk_buff *skb, u32 info);
1109 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
developer20126ad2022-09-12 14:42:56 +08001110 bool mt7915_wed_wds_check(struct mt76_dev *mdev, struct ieee80211_sta *sta);
developer3262bf82022-07-12 11:37:54 +08001111 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
developer3262bf82022-07-12 11:37:54 +08001112diff --git a/mt7915/regs.h b/mt7915/regs.h
developer27b55252022-09-05 19:09:45 +08001113index 432ed30..36ef8a9 100644
developer3262bf82022-07-12 11:37:54 +08001114--- a/mt7915/regs.h
1115+++ b/mt7915/regs.h
developer4df64ba2022-09-01 14:44:55 +08001116@@ -27,6 +27,9 @@ enum reg_rev {
developer3262bf82022-07-12 11:37:54 +08001117 FW_EXCEPTION_ADDR,
1118 SWDEF_BASE_ADDR,
1119 EXCEPTION_BASE_ADDR,
1120+ WED_TX_RING,
1121+ WED_RX_RING,
1122+ WED_RX_DATA_RING,
1123 __MT_REG_MAX,
1124 };
1125
developer4df64ba2022-09-01 14:44:55 +08001126@@ -564,9 +567,13 @@ enum offs_rev {
developer3262bf82022-07-12 11:37:54 +08001127 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
1128
1129 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
1130+#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
1131+#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
1132+
1133 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
1134 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
1135 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
1136+#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
1137
1138 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
1139 #define MT_WFDMA0_MT_WA_WDT_INT BIT(31)
developer4df64ba2022-09-01 14:44:55 +08001140@@ -664,12 +671,15 @@ enum offs_rev {
developer3262bf82022-07-12 11:37:54 +08001141 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
1142 MT_TXQ_ID(q)* 0x4)
1143
1144-#define MT_TXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7300 : 0x24420)
1145-#define MT_RXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7410 : 0x24520)
1146+#define MT_TXQ_WED_RING_BASE __REG(WED_TX_RING)
1147+#define MT_RXQ_WED_RING_BASE __REG(WED_RX_RING)
1148+#define MT_RXQ_WED_DATA_RING_BASE __REG(WED_RX_DATA_RING)
1149
1150 #define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30)
1151 #define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31)
1152 #define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
1153+#define MT_WED_RX_DONE_BAND0 (is_mt7915(mdev)? 16 : 22)
1154+#define MT_WED_RX_DONE_BAND1 (is_mt7915(mdev)? 17 : 23)
1155
1156 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
1157 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
1158diff --git a/mt7921/mac.c b/mt7921/mac.c
developer27b55252022-09-05 19:09:45 +08001159index 1374c15..275f367 100644
developer3262bf82022-07-12 11:37:54 +08001160--- a/mt7921/mac.c
1161+++ b/mt7921/mac.c
1162@@ -555,7 +555,7 @@ out:
1163 EXPORT_SYMBOL_GPL(mt7921_mac_add_txs);
1164
1165 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1166- struct sk_buff *skb)
1167+ struct sk_buff *skb, u32 info)
1168 {
1169 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1170 __le32 *rxd = (__le32 *)skb->data;
1171diff --git a/mt7921/mt7921.h b/mt7921/mt7921.h
developer27b55252022-09-05 19:09:45 +08001172index c161031..0a1f035 100644
developer3262bf82022-07-12 11:37:54 +08001173--- a/mt7921/mt7921.h
1174+++ b/mt7921/mt7921.h
developer4df64ba2022-09-01 14:44:55 +08001175@@ -381,7 +381,7 @@ int mt7921e_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer3262bf82022-07-12 11:37:54 +08001176 void mt7921_tx_worker(struct mt76_worker *w);
1177 void mt7921_tx_token_put(struct mt7921_dev *dev);
1178 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1179- struct sk_buff *skb);
1180+ struct sk_buff *skb, u32 info);
1181 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1182 void mt7921_stats_work(struct work_struct *work);
1183 void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
developer4df64ba2022-09-01 14:44:55 +08001184@@ -417,7 +417,7 @@ int mt7921_mcu_parse_response(struct mt76_dev *mdev, int cmd,
developer3262bf82022-07-12 11:37:54 +08001185
1186 bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len);
1187 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1188- struct sk_buff *skb);
1189+ struct sk_buff *skb, u32 info);
1190 int mt7921e_driver_own(struct mt7921_dev *dev);
1191 int mt7921e_mac_reset(struct mt7921_dev *dev);
1192 int mt7921e_mcu_init(struct mt7921_dev *dev);
1193diff --git a/mt7921/pci_mac.c b/mt7921/pci_mac.c
developer27b55252022-09-05 19:09:45 +08001194index e180067..ca982eb 100644
developer3262bf82022-07-12 11:37:54 +08001195--- a/mt7921/pci_mac.c
1196+++ b/mt7921/pci_mac.c
1197@@ -182,7 +182,7 @@ bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len)
1198 }
1199
1200 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1201- struct sk_buff *skb)
1202+ struct sk_buff *skb, u32 info)
1203 {
1204 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1205 __le32 *rxd = (__le32 *)skb->data;
1206@@ -196,7 +196,7 @@ void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1207 napi_consume_skb(skb, 1);
1208 break;
1209 default:
1210- mt7921_queue_rx_skb(mdev, q, skb);
1211+ mt7921_queue_rx_skb(mdev, q, skb, info);
1212 break;
1213 }
1214 }
1215diff --git a/tx.c b/tx.c
developer27b55252022-09-05 19:09:45 +08001216index 8b33186..b812d06 100644
developer3262bf82022-07-12 11:37:54 +08001217--- a/tx.c
1218+++ b/tx.c
developer4df64ba2022-09-01 14:44:55 +08001219@@ -778,3 +778,37 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
developer3262bf82022-07-12 11:37:54 +08001220 return txwi;
1221 }
1222 EXPORT_SYMBOL_GPL(mt76_token_release);
1223+
1224+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1225+ struct mt76_txwi_cache *r, dma_addr_t phys)
1226+{
1227+ int token;
1228+
1229+ spin_lock_bh(&dev->rx_token_lock);
1230+
1231+ token = idr_alloc(&dev->rx_token, r, 0, dev->rx_token_size, GFP_ATOMIC);
1232+
1233+ spin_unlock_bh(&dev->rx_token_lock);
1234+
1235+ r->buf = ptr;
1236+ r->dma_addr = phys;
1237+
1238+ return token;
1239+}
1240+EXPORT_SYMBOL_GPL(mt76_rx_token_consume);
1241+
1242+struct mt76_txwi_cache *
1243+mt76_rx_token_release(struct mt76_dev *dev, int token)
1244+{
1245+
1246+ struct mt76_txwi_cache *rxwi;
1247+
1248+ spin_lock_bh(&dev->rx_token_lock);
1249+
1250+ rxwi = idr_remove(&dev->rx_token, token);
1251+
1252+ spin_unlock_bh(&dev->rx_token_lock);
1253+
1254+ return rxwi;
1255+}
1256+EXPORT_SYMBOL_GPL(mt76_rx_token_release);
1257--
developerc89c5472022-08-02 13:00:04 +080012582.18.0
developer3262bf82022-07-12 11:37:54 +08001259