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developer05f3b2b2024-08-19 19:17:34 +08001From 594116fbcff4d30156c7207244633ad3c1bf9ec1 Mon Sep 17 00:00:00 2001
developer73e5a572022-04-19 10:21:20 +08002From: Bo Jiao <Bo.Jiao@mediatek.com>
developer6caa5e22022-06-16 13:33:13 +08003Date: Mon, 6 Jun 2022 20:13:02 +0800
developer05f3b2b2024-08-19 19:17:34 +08004Subject: [PATCH 1001/1052] wifi: mt76: mt7915: csi: implement csi support
developer73e5a572022-04-19 10:21:20 +08005
6---
developer28b11e22022-09-05 19:09:45 +08007 mt76_connac_mcu.h | 2 +
8 mt7915/Makefile | 4 +-
developera20cdc22024-05-31 18:57:31 +08009 mt7915/debugfs.c | 48 ++++
10 mt7915/init.c | 46 ++++
11 mt7915/main.c | 13 +
12 mt7915/mcu.c | 203 ++++++++++++++++
13 mt7915/mcu.h | 74 ++++++
14 mt7915/mt7915.h | 78 ++++++
15 mt7915/vendor.c | 606 ++++++++++++++++++++++++++++++++++++++++++++++
16 mt7915/vendor.h | 75 ++++++
17 10 files changed, 1147 insertions(+), 2 deletions(-)
developer28b11e22022-09-05 19:09:45 +080018 create mode 100644 mt7915/vendor.c
19 create mode 100644 mt7915/vendor.h
developer73e5a572022-04-19 10:21:20 +080020
21diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developer05f3b2b2024-08-19 19:17:34 +080022index 01d6598a..ad63596d 100644
developer73e5a572022-04-19 10:21:20 +080023--- a/mt76_connac_mcu.h
24+++ b/mt76_connac_mcu.h
developer05f3b2b2024-08-19 19:17:34 +080025@@ -1030,6 +1030,7 @@ enum {
developer47efbdb2023-06-29 20:33:22 +080026 MCU_EXT_EVENT_WA_TX_STAT = 0x74,
developer73e5a572022-04-19 10:21:20 +080027 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
28 MCU_EXT_EVENT_MURU_CTRL = 0x9f,
29+ MCU_EXT_EVENT_CSI_REPORT = 0xc2,
30 };
31
developer3609d782022-11-29 18:07:22 +080032 /* unified event table */
developer05f3b2b2024-08-19 19:17:34 +080033@@ -1245,6 +1246,7 @@ enum {
developer73e5a572022-04-19 10:21:20 +080034 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
35 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
developerdad89a32024-04-29 14:17:17 +080036 MCU_EXT_CMD_SET_QOS_MAP = 0xb4,
developer73e5a572022-04-19 10:21:20 +080037+ MCU_EXT_CMD_CSI_CTRL = 0xc2,
38 };
39
40 enum {
41diff --git a/mt7915/Makefile b/mt7915/Makefile
developer05f3b2b2024-08-19 19:17:34 +080042index fd711416..65129b4f 100644
developer73e5a572022-04-19 10:21:20 +080043--- a/mt7915/Makefile
44+++ b/mt7915/Makefile
developer60a3d662023-02-07 15:24:34 +080045@@ -1,10 +1,10 @@
developer73e5a572022-04-19 10:21:20 +080046 # SPDX-License-Identifier: ISC
developer60a3d662023-02-07 15:24:34 +080047
48-EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
49+EXTRA_CFLAGS += -DCONFIG_MT76_LEDS -DCONFIG_MTK_VENDOR
developer73e5a572022-04-19 10:21:20 +080050 obj-$(CONFIG_MT7915E) += mt7915e.o
51
52 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
53- debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
54+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o vendor.o
55
56 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
developer7af0f762023-05-22 15:16:16 +080057 mt7915e-$(CONFIG_MT798X_WMAC) += soc.o
developera20cdc22024-05-31 18:57:31 +080058diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
developer05f3b2b2024-08-19 19:17:34 +080059index 26613869..909df246 100644
developera20cdc22024-05-31 18:57:31 +080060--- a/mt7915/debugfs.c
61+++ b/mt7915/debugfs.c
62@@ -1241,6 +1241,51 @@ mt7915_rf_regval_set(void *data, u64 val)
63 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7915_rf_regval_get,
64 mt7915_rf_regval_set, "0x%08llx\n");
65
66+#ifdef CONFIG_MTK_VENDOR
67+static ssize_t
68+mt7915_get_csi_stats(struct file *file, char __user *user_buf,
69+ size_t count, loff_t *ppos)
70+
71+{
72+ struct mt7915_phy *phy = file->private_data;
73+ struct csi_mac_filter *current_mac, *tmp_mac;
74+ static const size_t sz = 4096;
75+ char *buf;
76+ u32 reg, len = 0;
77+ int ret;
78+
79+ buf = kzalloc(sz, GFP_KERNEL);
80+ if (!buf)
81+ return -ENOMEM;
82+
83+ len += scnprintf(buf + len, sz - len, "CSI enable: %d\n", phy->csi.enable);
84+
85+ if (phy->csi.enable) {
86+ len += scnprintf(buf + len, sz - len, "CSI data_cnt: %d\n", phy->csi.count);
87+
88+ mutex_lock(&phy->csi.mac_filter_lock);
89+
90+ list_for_each_entry_safe(current_mac, tmp_mac, &phy->csi.mac_filter_list, node) {
91+ len += scnprintf(buf + len, sz - len, "mac: %pM, interval: %d\n", current_mac->mac, current_mac->interval);
92+ }
93+
94+ mutex_unlock(&phy->csi.mac_filter_lock);
95+ }
96+
97+ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
98+
99+out:
100+ kfree(buf);
101+ return ret;
102+}
103+
104+static const struct file_operations mt7915_csi_ops = {
105+ .read = mt7915_get_csi_stats,
106+ .open = simple_open,
107+ .llseek = default_llseek,
108+};
109+#endif
110+
111 int mt7915_init_debugfs(struct mt7915_phy *phy)
112 {
113 struct mt7915_dev *dev = phy->dev;
114@@ -1283,6 +1328,9 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
115 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir,
116 mt7915_rdd_monitor);
117 }
118+#ifdef CONFIG_MTK_VENDOR
119+ debugfs_create_file("csi_stats", 0400, dir, phy, &mt7915_csi_ops);
120+#endif
121
122 if (!ext_phy)
123 dev->debugfs_dir = dir;
developer73e5a572022-04-19 10:21:20 +0800124diff --git a/mt7915/init.c b/mt7915/init.c
developer05f3b2b2024-08-19 19:17:34 +0800125index 84c69a88..ac15bc53 100644
developer73e5a572022-04-19 10:21:20 +0800126--- a/mt7915/init.c
127+++ b/mt7915/init.c
developer05f3b2b2024-08-19 19:17:34 +0800128@@ -668,6 +668,14 @@ mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy)
developer73e5a572022-04-19 10:21:20 +0800129 /* init wiphy according to mphy and phy */
developer17bb0a82022-12-13 15:52:04 +0800130 mt7915_init_wiphy(phy);
developer73e5a572022-04-19 10:21:20 +0800131
132+#ifdef CONFIG_MTK_VENDOR
developera20cdc22024-05-31 18:57:31 +0800133+ INIT_LIST_HEAD(&phy->csi.data_list);
134+ spin_lock_init(&phy->csi.data_lock);
135+ INIT_LIST_HEAD(&phy->csi.mac_filter_list);
136+ mutex_init(&phy->csi.mac_filter_lock);
developer73e5a572022-04-19 10:21:20 +0800137+ mt7915_vendor_register(phy);
138+#endif
139+
140 ret = mt76_register_phy(mphy, true, mt76_rates,
141 ARRAY_SIZE(mt76_rates));
142 if (ret)
developer05f3b2b2024-08-19 19:17:34 +0800143@@ -1146,6 +1154,28 @@ void mt7915_set_stream_he_caps(struct mt7915_phy *phy)
developer73e5a572022-04-19 10:21:20 +0800144 }
145 }
146
147+#ifdef CONFIG_MTK_VENDOR
148+static int mt7915_unregister_features(struct mt7915_phy *phy)
149+{
150+ struct csi_data *c, *tmp_c;
151+
developera20cdc22024-05-31 18:57:31 +0800152+ spin_lock_bh(&phy->csi.data_lock);
developer73e5a572022-04-19 10:21:20 +0800153+ phy->csi.enable = 0;
154+
developera20cdc22024-05-31 18:57:31 +0800155+ list_for_each_entry_safe(c, tmp_c, &phy->csi.data_list, node) {
developer73e5a572022-04-19 10:21:20 +0800156+ list_del(&c->node);
157+ kfree(c);
158+ }
developera20cdc22024-05-31 18:57:31 +0800159+ spin_unlock_bh(&phy->csi.data_lock);
160+
161+ mutex_lock(&phy->csi.mac_filter_lock);
162+ mt7915_csi_mac_filter_clear(phy);
163+ mutex_unlock(&phy->csi.mac_filter_lock);
developer73e5a572022-04-19 10:21:20 +0800164+
developer73e5a572022-04-19 10:21:20 +0800165+ return 0;
166+}
167+#endif
168+
169 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
170 {
171 struct mt7915_phy *phy = mt7915_ext_phy(dev);
developer05f3b2b2024-08-19 19:17:34 +0800172@@ -1154,6 +1184,10 @@ static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
developer73e5a572022-04-19 10:21:20 +0800173 if (!phy)
174 return;
175
176+#ifdef CONFIG_MTK_VENDOR
177+ mt7915_unregister_features(phy);
178+#endif
179+
180 mt7915_unregister_thermal(phy);
181 mt76_unregister_phy(mphy);
182 ieee80211_free_hw(mphy->hw);
developer05f3b2b2024-08-19 19:17:34 +0800183@@ -1166,6 +1200,10 @@ static void mt7915_stop_hardware(struct mt7915_dev *dev)
developer73e5a572022-04-19 10:21:20 +0800184 mt7915_dma_cleanup(dev);
developer7af0f762023-05-22 15:16:16 +0800185 tasklet_disable(&dev->mt76.irq_tasklet);
developer73e5a572022-04-19 10:21:20 +0800186
187+#ifdef CONFIG_MTK_VENDOR
188+ mt7915_unregister_features(&dev->phy);
189+#endif
190+
developer7af0f762023-05-22 15:16:16 +0800191 if (is_mt798x(&dev->mt76))
developer73e5a572022-04-19 10:21:20 +0800192 mt7986_wmac_disable(dev);
193 }
developer05f3b2b2024-08-19 19:17:34 +0800194@@ -1210,6 +1248,14 @@ int mt7915_register_device(struct mt7915_dev *dev)
developer73e5a572022-04-19 10:21:20 +0800195 dev->mt76.test_ops = &mt7915_testmode_ops;
196 #endif
197
198+#ifdef CONFIG_MTK_VENDOR
developera20cdc22024-05-31 18:57:31 +0800199+ INIT_LIST_HEAD(&dev->phy.csi.data_list);
200+ spin_lock_init(&dev->phy.csi.data_lock);
201+ INIT_LIST_HEAD(&dev->phy.csi.mac_filter_list);
202+ mutex_init(&dev->phy.csi.mac_filter_lock);
developer73e5a572022-04-19 10:21:20 +0800203+ mt7915_vendor_register(&dev->phy);
204+#endif
205+
developer17bb0a82022-12-13 15:52:04 +0800206 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
207 ARRAY_SIZE(mt76_rates));
208 if (ret)
developer1a173672023-12-21 14:49:33 +0800209diff --git a/mt7915/main.c b/mt7915/main.c
developer05f3b2b2024-08-19 19:17:34 +0800210index fc9a464a..12bb0b39 100644
developer1a173672023-12-21 14:49:33 +0800211--- a/mt7915/main.c
212+++ b/mt7915/main.c
developera20cdc22024-05-31 18:57:31 +0800213@@ -810,6 +810,19 @@ void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
214 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
developer1a173672023-12-21 14:49:33 +0800215 struct mt7915_phy *phy = msta->vif->phy;
216 int i;
developer1a173672023-12-21 14:49:33 +0800217+#ifdef CONFIG_MTK_VENDOR
developera20cdc22024-05-31 18:57:31 +0800218+ struct csi_mac_filter *ent;
developer1a173672023-12-21 14:49:33 +0800219+
developera20cdc22024-05-31 18:57:31 +0800220+ mutex_lock(&phy->csi.mac_filter_lock);
221+ ent = mt7915_csi_mac_filter_find(phy, sta->addr);
222+ if (ent && !mt7915_mcu_set_csi(phy, 2, 8, 1, 0, sta->addr, 0)) {
223+ list_del(&ent->node);
224+ kfree(ent);
225+ phy->csi.mac_filter_cnt--;
226+ }
227+
228+ mutex_unlock(&phy->csi.mac_filter_lock);
229+#endif
230
developer1a173672023-12-21 14:49:33 +0800231 mt7915_mcu_add_sta(dev, vif, sta, false);
232
developer73e5a572022-04-19 10:21:20 +0800233diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer05f3b2b2024-08-19 19:17:34 +0800234index ff7f81b0..44765b1f 100644
developer73e5a572022-04-19 10:21:20 +0800235--- a/mt7915/mcu.c
236+++ b/mt7915/mcu.c
developer7af0f762023-05-22 15:16:16 +0800237@@ -40,6 +40,10 @@ static bool sr_scene_detect = true;
developer3609d782022-11-29 18:07:22 +0800238 module_param(sr_scene_detect, bool, 0644);
239 MODULE_PARM_DESC(sr_scene_detect, "Enable firmware scene detection algorithm");
developer73e5a572022-04-19 10:21:20 +0800240
241+#ifdef CONFIG_MTK_VENDOR
242+static int mt7915_mcu_report_csi(struct mt7915_dev *dev, struct sk_buff *skb);
243+#endif
244+
245 static u8
246 mt7915_mcu_get_sta_nss(u16 mcs_map)
247 {
developer753619c2024-02-22 13:42:45 +0800248@@ -466,6 +470,11 @@ mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
developer73e5a572022-04-19 10:21:20 +0800249 case MCU_EXT_EVENT_FW_LOG_2_HOST:
250 mt7915_mcu_rx_log_message(dev, skb);
251 break;
252+#ifdef CONFIG_MTK_VENDOR
253+ case MCU_EXT_EVENT_CSI_REPORT:
254+ mt7915_mcu_report_csi(dev, skb);
255+ break;
256+#endif
257 case MCU_EXT_EVENT_BCC_NOTIFY:
258 mt7915_mcu_rx_bcc_notify(dev, skb);
259 break;
developera46f6132024-03-26 14:09:54 +0800260@@ -4195,6 +4204,200 @@ out:
developer47efbdb2023-06-29 20:33:22 +0800261 return ret;
developer73e5a572022-04-19 10:21:20 +0800262 }
263
264+#ifdef CONFIG_MTK_VENDOR
265+int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
developer1a173672023-12-21 14:49:33 +0800266+ u8 cfg, u8 v1, u32 v2, u8 *mac_addr, u32 sta_interval)
developer73e5a572022-04-19 10:21:20 +0800267+{
268+ struct mt7915_dev *dev = phy->dev;
269+ struct mt7915_mcu_csi req = {
270+ .band = phy != &dev->phy,
271+ .mode = mode,
272+ .cfg = cfg,
273+ .v1 = v1,
274+ .v2 = cpu_to_le32(v2),
275+ };
276+
developer1a173672023-12-21 14:49:33 +0800277+ if (is_valid_ether_addr(mac_addr)) {
developer73e5a572022-04-19 10:21:20 +0800278+ ether_addr_copy(req.mac_addr, mac_addr);
279+
developera20cdc22024-05-31 18:57:31 +0800280+ if ((req.v2 == ADD_CSI_MAC) && sta_interval)
developer1a173672023-12-21 14:49:33 +0800281+ req.sta_interval = sta_interval;
282+ }
283+
developer73e5a572022-04-19 10:21:20 +0800284+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(CSI_CTRL), &req,
developer1a173672023-12-21 14:49:33 +0800285+ sizeof(req), true);
developer73e5a572022-04-19 10:21:20 +0800286+}
287+
developer1a173672023-12-21 14:49:33 +0800288+static int csi_integret_segment_data(struct mt7915_phy *phy, struct csi_data *csi)
289+{
290+ struct csi_data *csi_temp = NULL;
291+
292+ if (csi->segment_num == 0 &&
293+ csi->remain_last == 0)
294+ return CSI_CHAIN_COMPLETE;
295+ else if (csi->segment_num == 0 &&
296+ csi->remain_last == 1) {
297+ memcpy(&phy->csi.buffered_csi,
298+ csi, sizeof(struct csi_data));
299+
300+ return CSI_CHAIN_SEGMENT_FIRST;
301+ } else if (csi->segment_num != 0) {
302+ csi_temp = &phy->csi.buffered_csi;
303+ if (csi->chain_info !=
304+ csi_temp->chain_info ||
305+ csi->segment_num !=
306+ (csi_temp->segment_num + 1))
307+ return CSI_CHAIN_SEGMENT_ERR;
308+
309+ memcpy(&csi_temp->data_i[csi_temp->data_num],
310+ csi->data_i, csi->data_num * sizeof(s16));
311+
312+ memcpy(&csi_temp->data_q[csi_temp->data_num],
313+ csi->data_q, csi->data_num * sizeof(s16));
314+
315+ csi_temp->data_num += csi->data_num;
316+ csi_temp->segment_num = csi->segment_num;
317+ csi_temp->remain_last = csi->remain_last;
318+
319+ if (csi->remain_last == 0)
320+ return CSI_CHAIN_SEGMENT_LAST;
321+ else if (csi->remain_last == 1)
322+ return CSI_CHAIN_SEGMENT_MIDDLE;
323+ }
324+
325+ return CSI_CHAIN_ERR;
326+}
327+
developer73e5a572022-04-19 10:21:20 +0800328+static int
329+mt7915_mcu_report_csi(struct mt7915_dev *dev, struct sk_buff *skb)
330+{
developer7c3a5082022-06-24 13:40:42 +0800331+ struct mt76_connac2_mcu_rxd *rxd = (struct mt76_connac2_mcu_rxd *)skb->data;
developer73e5a572022-04-19 10:21:20 +0800332+ struct mt7915_phy *phy = &dev->phy;
developer73e5a572022-04-19 10:21:20 +0800333+ int len, i;
developer1a173672023-12-21 14:49:33 +0800334+ struct mt7915_mcu_csi_report *cr;
335+ int ret;
336+ struct csi_data *current_csi = NULL;
337+ struct csi_data *target_csi = NULL;
developer73e5a572022-04-19 10:21:20 +0800338+
developer7c3a5082022-06-24 13:40:42 +0800339+ skb_pull(skb, sizeof(struct mt76_connac2_mcu_rxd));
developer73e5a572022-04-19 10:21:20 +0800340+
developer7c3a5082022-06-24 13:40:42 +0800341+ len = le16_to_cpu(rxd->len) - sizeof(struct mt76_connac2_mcu_rxd) + 24;
developer73e5a572022-04-19 10:21:20 +0800342+
343+ cr = (struct mt7915_mcu_csi_report *)skb->data;
344+
345+ if (phy->csi.interval &&
346+ le32_to_cpu(cr->ts) < phy->csi.last_record + phy->csi.interval)
347+ return 0;
348+
developer1a173672023-12-21 14:49:33 +0800349+ current_csi = kzalloc(sizeof(*current_csi), GFP_KERNEL);
350+
351+ if (!current_csi)
developer73e5a572022-04-19 10:21:20 +0800352+ return -ENOMEM;
353+
developer1a173672023-12-21 14:49:33 +0800354+ memset(current_csi, 0, sizeof(struct csi_data));
355+
356+#define SET_CSI_DATA(_field) (current_csi->_field = le32_to_cpu((cr->_field)))
developer73e5a572022-04-19 10:21:20 +0800357+ SET_CSI_DATA(ch_bw);
358+ SET_CSI_DATA(rssi);
359+ SET_CSI_DATA(snr);
360+ SET_CSI_DATA(data_num);
361+ SET_CSI_DATA(data_bw);
362+ SET_CSI_DATA(pri_ch_idx);
developer1a173672023-12-21 14:49:33 +0800363+ SET_CSI_DATA(ext_info);
developer73e5a572022-04-19 10:21:20 +0800364+ SET_CSI_DATA(rx_mode);
developer1a173672023-12-21 14:49:33 +0800365+ SET_CSI_DATA(chain_info);
developer73e5a572022-04-19 10:21:20 +0800366+ SET_CSI_DATA(ts);
367+
developer1a173672023-12-21 14:49:33 +0800368+ if (is_mt798x(&dev->mt76) || is_mt7916(&dev->mt76)) {
369+ SET_CSI_DATA(segment_num);
370+ SET_CSI_DATA(remain_last);
371+ SET_CSI_DATA(pkt_sn);
372+ SET_CSI_DATA(tr_stream);
373+ }
374+
developer73e5a572022-04-19 10:21:20 +0800375+ SET_CSI_DATA(band);
developer1a173672023-12-21 14:49:33 +0800376+ if (current_csi->band && !phy->mt76->band_idx)
developer73e5a572022-04-19 10:21:20 +0800377+ phy = mt7915_ext_phy(dev);
378+#undef SET_CSI_DATA
379+
developer1a173672023-12-21 14:49:33 +0800380+ switch (current_csi->ch_bw) {
381+ case CSI_BW20:
382+ if (is_mt798x(&dev->mt76) || is_mt7916(&dev->mt76))
383+ current_csi->data_num = CSI_BW20_DATA_COUNT;
384+ break;
385+ case CSI_BW40:
386+ if (is_mt798x(&dev->mt76) || is_mt7916(&dev->mt76))
387+ current_csi->data_num = CSI_BW40_DATA_COUNT;
388+ break;
389+ default:
390+ break;
developer73e5a572022-04-19 10:21:20 +0800391+ }
392+
developer1a173672023-12-21 14:49:33 +0800393+ for (i = 0; i < current_csi->data_num; i++) {
394+ current_csi->data_i[i] = le16_to_cpu(cr->data_i[i]);
395+ current_csi->data_q[i] = le16_to_cpu(cr->data_q[i]);
396+ }
397+
398+ memcpy(current_csi->ta, cr->ta, ETH_ALEN);
399+ current_csi->tx_idx = le32_get_bits(cr->trx_idx, GENMASK(31, 16));
400+ current_csi->rx_idx = le32_get_bits(cr->trx_idx, GENMASK(15, 0));
401+
402+ /* integret the bw80 segment */
403+ if ((is_mt798x(&dev->mt76) || is_mt7916(&dev->mt76)) && current_csi->ch_bw >= CSI_BW80) {
404+ ret = csi_integret_segment_data(phy, current_csi);
developer73e5a572022-04-19 10:21:20 +0800405+
developer1a173672023-12-21 14:49:33 +0800406+ /* event data error or event drop */
407+ if (ret == CSI_CHAIN_ERR || ret == CSI_CHAIN_SEGMENT_ERR) {
408+ kfree(current_csi);
409+ return -EINVAL;
410+ }
411+
412+ if (ret == CSI_CHAIN_SEGMENT_FIRST || ret == CSI_CHAIN_SEGMENT_MIDDLE) {
413+ kfree(current_csi);
414+ return 0;
415+ } else if (ret == CSI_CHAIN_COMPLETE) {
416+ target_csi = current_csi;
417+ } else if (ret == CSI_CHAIN_SEGMENT_LAST) {
418+ target_csi = current_csi;
419+ memcpy(target_csi, &phy->csi.buffered_csi, sizeof(struct csi_data));
420+ memset(&phy->csi.buffered_csi, 0, sizeof(struct csi_data));
421+ }
422+ } else {
423+ target_csi = current_csi;
424+ }
425+
426+ /* put the csi data into list */
427+ INIT_LIST_HEAD(&target_csi->node);
developera20cdc22024-05-31 18:57:31 +0800428+ spin_lock_bh(&phy->csi.data_lock);
developer73e5a572022-04-19 10:21:20 +0800429+
430+ if (!phy->csi.enable) {
developer1a173672023-12-21 14:49:33 +0800431+ kfree(target_csi);
developera20cdc22024-05-31 18:57:31 +0800432+ spin_unlock_bh(&phy->csi.data_lock);
developer73e5a572022-04-19 10:21:20 +0800433+ return 0;
434+ }
435+
developera20cdc22024-05-31 18:57:31 +0800436+ list_add_tail(&target_csi->node, &phy->csi.data_list);
developer73e5a572022-04-19 10:21:20 +0800437+ phy->csi.count++;
438+
439+ if (phy->csi.count > CSI_MAX_BUF_NUM) {
440+ struct csi_data *old;
441+
developera20cdc22024-05-31 18:57:31 +0800442+ old = list_first_entry(&phy->csi.data_list,
developer73e5a572022-04-19 10:21:20 +0800443+ struct csi_data, node);
444+
445+ list_del(&old->node);
446+ kfree(old);
447+ phy->csi.count--;
448+ }
449+
developer1a173672023-12-21 14:49:33 +0800450+ if (target_csi->chain_info & BIT(15)) /* last chain */
451+ phy->csi.last_record = target_csi->ts;
developera20cdc22024-05-31 18:57:31 +0800452+ spin_unlock_bh(&phy->csi.data_lock);
developer73e5a572022-04-19 10:21:20 +0800453+
454+ return 0;
455+}
456+#endif
457+
458 #ifdef MTK_DEBUG
459 int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
460 {
461diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer05f3b2b2024-08-19 19:17:34 +0800462index 9ae0f07a..f32d5256 100644
developer73e5a572022-04-19 10:21:20 +0800463--- a/mt7915/mcu.h
464+++ b/mt7915/mcu.h
developer753619c2024-02-22 13:42:45 +0800465@@ -604,4 +604,78 @@ mt7915_get_power_bound(struct mt7915_phy *phy, s8 txpower)
developer8effbd32023-04-17 15:57:28 +0800466 enum {
467 MCU_GET_TX_RATE = 4
468 };
469+
developer73e5a572022-04-19 10:21:20 +0800470+#ifdef CONFIG_MTK_VENDOR
471+struct mt7915_mcu_csi {
472+ u8 band;
473+ u8 mode;
474+ u8 cfg;
475+ u8 v1;
476+ __le32 v2;
477+ u8 mac_addr[ETH_ALEN];
developer1a173672023-12-21 14:49:33 +0800478+ u8 _rsv1[2];
479+ u32 sta_interval;
480+ u8 _rsv2[28];
developer73e5a572022-04-19 10:21:20 +0800481+} __packed;
482+
483+struct csi_tlv {
484+ __le32 tag;
485+ __le32 len;
486+} __packed;
487+
developer73e5a572022-04-19 10:21:20 +0800488+#define CSI_MAX_BUF_NUM 3000
489+
490+struct mt7915_mcu_csi_report {
491+ struct csi_tlv _t0;
492+ __le32 ver;
493+ struct csi_tlv _t1;
494+ __le32 ch_bw;
495+ struct csi_tlv _t2;
496+ __le32 rssi;
497+ struct csi_tlv _t3;
498+ __le32 snr;
499+ struct csi_tlv _t4;
500+ __le32 band;
501+ struct csi_tlv _t5;
502+ __le32 data_num;
503+ struct csi_tlv _t6;
developer1a173672023-12-21 14:49:33 +0800504+ __le16 data_i[CSI_BW80_DATA_COUNT];
developer73e5a572022-04-19 10:21:20 +0800505+ struct csi_tlv _t7;
developer1a173672023-12-21 14:49:33 +0800506+ __le16 data_q[CSI_BW80_DATA_COUNT];
developer73e5a572022-04-19 10:21:20 +0800507+ struct csi_tlv _t8;
508+ __le32 data_bw;
509+ struct csi_tlv _t9;
510+ __le32 pri_ch_idx;
511+ struct csi_tlv _t10;
512+ u8 ta[8];
513+ struct csi_tlv _t11;
developer1a173672023-12-21 14:49:33 +0800514+ __le32 ext_info;
developer73e5a572022-04-19 10:21:20 +0800515+ struct csi_tlv _t12;
516+ __le32 rx_mode;
517+ struct csi_tlv _t17;
developer1a173672023-12-21 14:49:33 +0800518+ __le32 chain_info;
developer73e5a572022-04-19 10:21:20 +0800519+ struct csi_tlv _t18;
520+ __le32 trx_idx;
521+ struct csi_tlv _t19;
522+ __le32 ts;
developer1a173672023-12-21 14:49:33 +0800523+ struct csi_tlv _t20;
524+ __le32 pkt_sn;
525+ struct csi_tlv _t21;
526+ __le32 segment_num;
527+ struct csi_tlv _t22;
528+ __le32 remain_last;
529+ struct csi_tlv _t23;
530+ __le32 tr_stream;
developer73e5a572022-04-19 10:21:20 +0800531+} __packed;
532+
developer1a173672023-12-21 14:49:33 +0800533+enum CSI_CHAIN_TYPE {
534+ CSI_CHAIN_ERR,
535+ CSI_CHAIN_COMPLETE,
536+ CSI_CHAIN_SEGMENT_FIRST,
537+ CSI_CHAIN_SEGMENT_MIDDLE,
538+ CSI_CHAIN_SEGMENT_LAST,
539+ CSI_CHAIN_SEGMENT_ERR,
540+};
541+#endif
542+
543 #endif
544diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer05f3b2b2024-08-19 19:17:34 +0800545index 58c0bf99..1316f93d 100644
developer1a173672023-12-21 14:49:33 +0800546--- a/mt7915/mt7915.h
547+++ b/mt7915/mt7915.h
developer05f3b2b2024-08-19 19:17:34 +0800548@@ -195,6 +195,57 @@ struct mt7915_hif {
developer1a173672023-12-21 14:49:33 +0800549 int irq;
550 };
551
552+#ifdef CONFIG_MTK_VENDOR
553+enum csi_bw {
554+ CSI_BW20,
555+ CSI_BW40,
556+ CSI_BW80,
557+ CSI_BW160
558+};
559+
560+#define CSI_BW20_DATA_COUNT 64
561+#define CSI_BW40_DATA_COUNT 128
562+#define CSI_BW80_DATA_COUNT 256
563+#define CSI_BW160_DATA_COUNT 512
564+
developer73e5a572022-04-19 10:21:20 +0800565+struct csi_data {
566+ u8 ch_bw;
567+ u16 data_num;
developer1a173672023-12-21 14:49:33 +0800568+ s16 data_i[CSI_BW160_DATA_COUNT];
569+ s16 data_q[CSI_BW160_DATA_COUNT];
developer73e5a572022-04-19 10:21:20 +0800570+ u8 band;
571+ s8 rssi;
572+ u8 snr;
573+ u32 ts;
574+ u8 data_bw;
575+ u8 pri_ch_idx;
576+ u8 ta[ETH_ALEN];
developer1a173672023-12-21 14:49:33 +0800577+ u32 ext_info;
developer73e5a572022-04-19 10:21:20 +0800578+ u8 rx_mode;
developer1a173672023-12-21 14:49:33 +0800579+ u32 chain_info;
developer73e5a572022-04-19 10:21:20 +0800580+ u16 tx_idx;
581+ u16 rx_idx;
developer1a173672023-12-21 14:49:33 +0800582+ u32 segment_num;
583+ u8 remain_last;
584+ u16 pkt_sn;
585+ u8 tr_stream;
developer73e5a572022-04-19 10:21:20 +0800586+
587+ struct list_head node;
developera20cdc22024-05-31 18:57:31 +0800588+};
589+struct csi_mac_filter {
590+ struct list_head node;
591+
592+ u8 mac[ETH_ALEN];
593+ u32 interval;
developer73e5a572022-04-19 10:21:20 +0800594+};
developera20cdc22024-05-31 18:57:31 +0800595+
596+#define DEL_CSI_MAC 0
597+#define ADD_CSI_MAC 1
598+#define SHOW_CSI_MAC 2
599+
600+#define MAX_CSI_MAC_NUM 10
developer73e5a572022-04-19 10:21:20 +0800601+#endif
602+
developer1a173672023-12-21 14:49:33 +0800603 struct mt7915_phy {
604 struct mt76_phy *mt76;
605 struct mt7915_dev *dev;
developer05f3b2b2024-08-19 19:17:34 +0800606@@ -243,6 +294,25 @@ struct mt7915_phy {
developer73e5a572022-04-19 10:21:20 +0800607 u8 spe_idx;
608 } test;
609 #endif
610+
611+#ifdef CONFIG_MTK_VENDOR
612+ struct {
developera20cdc22024-05-31 18:57:31 +0800613+ struct list_head data_list;
614+ spinlock_t data_lock;
developer73e5a572022-04-19 10:21:20 +0800615+ u32 count;
616+ bool mask;
617+ bool reorder;
618+ bool enable;
619+
developera20cdc22024-05-31 18:57:31 +0800620+ struct mutex mac_filter_lock;
621+ struct list_head mac_filter_list;
622+ u8 mac_filter_cnt;
623+
developer1a173672023-12-21 14:49:33 +0800624+ struct csi_data buffered_csi;
developer73e5a572022-04-19 10:21:20 +0800625+ u32 interval;
626+ u32 last_record;
627+ } csi;
628+#endif
629 };
630
developera46f6132024-03-26 14:09:54 +0800631 #ifdef MTK_DEBUG
developer05f3b2b2024-08-19 19:17:34 +0800632@@ -646,6 +716,14 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerec567112022-10-11 11:02:55 +0800633 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
634 bool pci, int *irq);
developer73e5a572022-04-19 10:21:20 +0800635
636+#ifdef CONFIG_MTK_VENDOR
637+void mt7915_vendor_register(struct mt7915_phy *phy);
638+int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
developer1a173672023-12-21 14:49:33 +0800639+ u8 cfg, u8 v1, u32 v2, u8 *mac_addr, u32 sta_interval);
developera20cdc22024-05-31 18:57:31 +0800640+struct csi_mac_filter *mt7915_csi_mac_filter_find(struct mt7915_phy *phy, u8 *addr);
641+void mt7915_csi_mac_filter_clear(struct mt7915_phy *phy);
developer73e5a572022-04-19 10:21:20 +0800642+#endif
643+
644 #ifdef MTK_DEBUG
645 int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
646 int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
647diff --git a/mt7915/vendor.c b/mt7915/vendor.c
648new file mode 100644
developer05f3b2b2024-08-19 19:17:34 +0800649index 00000000..92496513
developer73e5a572022-04-19 10:21:20 +0800650--- /dev/null
651+++ b/mt7915/vendor.c
developera20cdc22024-05-31 18:57:31 +0800652@@ -0,0 +1,606 @@
developer73e5a572022-04-19 10:21:20 +0800653+// SPDX-License-Identifier: ISC
654+/*
655+ * Copyright (C) 2020, MediaTek Inc. All rights reserved.
656+ */
657+
658+#include <net/netlink.h>
659+
660+#include "mt7915.h"
661+#include "mcu.h"
662+#include "vendor.h"
663+
664+static const struct nla_policy
665+csi_ctrl_policy[NUM_MTK_VENDOR_ATTRS_CSI_CTRL] = {
666+ [MTK_VENDOR_ATTR_CSI_CTRL_CFG] = {.type = NLA_NESTED },
667+ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE] = { .type = NLA_U8 },
668+ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE] = { .type = NLA_U8 },
669+ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1] = { .type = NLA_U8 },
670+ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2] = { .type = NLA_U8 },
671+ [MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR] = { .type = NLA_NESTED },
672+ [MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL] = { .type = NLA_U32 },
developer1a173672023-12-21 14:49:33 +0800673+ [MTK_VENDOR_ATTR_CSI_CTRL_STA_INTERVAL] = { .type = NLA_U32 },
developer73e5a572022-04-19 10:21:20 +0800674+ [MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM] = { .type = NLA_U16 },
675+ [MTK_VENDOR_ATTR_CSI_CTRL_DATA] = { .type = NLA_NESTED },
developera20cdc22024-05-31 18:57:31 +0800676+ [MTK_VENDOR_ATTR_CSI_CTRL_DUMP_MAC_FILTER] = { .type = NLA_NESTED },
developer73e5a572022-04-19 10:21:20 +0800677+};
678+
679+struct csi_null_tone {
680+ u8 start;
681+ u8 end;
682+};
683+
developer1a173672023-12-21 14:49:33 +0800684+struct csi_reorder {
developer73e5a572022-04-19 10:21:20 +0800685+ u8 dest;
686+ u8 start;
687+ u8 end;
688+};
689+
690+struct csi_mask {
691+ struct csi_null_tone null[10];
692+ u8 pilot[8];
693+ struct csi_reorder ro[3];
694+};
695+
696+static const struct csi_mask csi_mask_groups[] = {
697+ /* OFDM */
698+ { .null = { { 0 }, { 27, 37 } },
699+ .ro = { {0, 0, 63} },
700+ },
701+ { .null = { { 0, 69 }, { 96 }, { 123, 127 } },
702+ .ro = { { 0, 96 }, { 38, 70, 95 }, { 1, 97, 122 } },
703+ },
704+ { .null = { { 0, 5 }, { 32 }, { 59, 127 } },
705+ .ro = { { 0, 32 }, { 38, 6, 31 }, { 1, 33, 58 } },
706+ },
707+ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 127 } },
708+ .ro = { { 0, 0, 127 } },
709+ },
710+ { .null = { { 0, 133 }, { 160 }, { 187, 255 } },
711+ .ro = { { 0, 160 }, { 1, 161, 186 }, { 38, 134, 159 } },
712+ },
713+ { .null = { { 0, 197 }, { 224 }, { 251, 255 } },
714+ .ro = { { 0, 224 }, { 1, 225, 250 }, { 38, 198, 223 } },
715+ },
716+ { .null = { { 0, 5 }, { 32 }, { 59, 255 } },
717+ .ro = { { 0, 32 }, { 1, 33, 58 }, { 38, 6, 31 } },
718+ },
719+ { .null = { { 0, 69 }, { 96 }, { 123, 255 } },
720+ .ro = { { 0, 96 }, { 1, 97, 122 }, { 38, 70, 95 } },
721+ },
722+ { .null = { { 0, 133 }, { 160 }, { 187, 197 }, { 224 }, { 251, 255 } },
723+ .ro = { { 0, 192 }, { 2, 198, 250 }, { 74, 134, 186 } },
724+ },
725+ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 255 } },
726+ .ro = { { 0, 64 }, { 2, 70, 122 }, { 74, 6, 58 } },
727+ },
728+ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 133 },
729+ { 160 }, { 187, 197 }, { 224 }, { 251, 255 } },
730+ .ro = { { 0, 0, 255 } },
731+ },
732+
733+ /* HT/VHT */
734+ { .null = { { 0 }, { 29, 35 } },
735+ .pilot = { 7, 21, 43, 57 },
736+ .ro = { { 0, 0, 63 } },
737+ },
738+ { .null = { { 0, 67 }, { 96 }, { 125, 127 } },
739+ .pilot = { 75, 89, 103, 117 },
740+ .ro = { { 0, 96 }, { 36, 68, 95 }, { 1, 97, 124 } },
741+ },
742+ { .null = { { 0, 3 }, { 32 }, { 61, 127 } },
743+ .pilot = { 11, 25, 39, 53 },
744+ .ro = { { 0, 32 }, { 36, 4, 31 }, { 1, 33, 60 } },
745+ },
746+ { .null = { { 0, 1 }, { 59, 69 }, { 127 } },
747+ .pilot = { 11, 25, 53, 75, 103, 117 },
748+ .ro = { { 0, 0, 127 } },
749+ },
750+ { .null = { { 0, 131 }, { 160 }, { 189, 255 } },
751+ .pilot = { 139, 153, 167, 181 },
752+ .ro = { { 0, 160 }, { 1, 161, 188 }, { 36, 132, 159 } },
753+ },
754+ { .null = { { 0, 195 }, { 224 }, { 253 }, { 255 } },
755+ .pilot = { 203, 217, 231, 245 },
756+ .ro = { { 0, 224 }, { 1, 225, 252 }, { 36, 196, 223 } },
757+ },
758+ { .null = { { 0, 3 }, { 32 }, { 61, 255 } },
759+ .pilot = { 11, 25, 39, 53 },
760+ .ro = { { 0, 32 }, { 1, 33, 60 }, { 36, 4, 31 } },
761+ },
762+ { .null = { { 0, 67 }, { 96 }, { 125, 255 } },
763+ .pilot = { 75, 89, 103, 117 },
764+ .ro = { { 0, 96 }, { 1, 97, 124 }, { 36, 68, 95 } },
765+ },
766+ { .null = { { 0, 133 }, { 191, 193 }, { 251, 255 } },
767+ .pilot = { 139, 167, 181, 203, 217, 245 },
768+ .ro = { { 0, 192 }, { 2, 194, 250 }, { 70, 134, 190 } },
769+ },
770+ { .null = { { 0, 5 }, { 63, 65 }, { 123, 127 } },
771+ .pilot = { 11, 39, 53, 75, 89, 117 },
772+ .ro = { { 0, 64 }, { 2, 66, 122 }, { 70, 6, 62 } },
773+ },
774+ { .null = { { 0, 1 }, { 123, 133 }, { 255 } },
775+ .pilot = { 11, 39, 75, 103, 153, 181, 217, 245 },
776+ .ro = { { 0, 0, 255 } },
777+ },
778+
779+ /* HE */
780+ { .null = { { 0 }, { 31, 33 } },
781+ .pilot = { 12, 29, 35, 52 },
782+ .ro = { { 0, 0, 63 } },
783+ },
784+ { .null = { { 30, 34 }, { 96 } },
785+ .pilot = { 4, 21, 43, 60, 70, 87, 105, 122 },
786+ .ro = { { 0, 96 }, { 34, 66, 95 }, { 1, 97, 126 } },
787+ },
788+ { .null = { { 32 }, { 94, 98 } },
789+ .pilot = { 6, 23, 41, 58, 68, 85, 107, 124 },
790+ .ro = { { 0, 32 }, { 34, 2, 31 }, { 1, 31, 62 } },
791+ },
792+ { .null = { { 0 }, { 62, 66 } },
793+ .pilot = { 9, 26, 36, 53, 75, 92, 102, 119 },
794+ .ro = { { 0, 0, 127 } },
795+ },
796+ { .null = { { 30, 34 }, { 160 } },
797+ .pilot = { 4, 21, 43, 60, 137, 154, 166, 183 },
798+ .ro = { { 0, 160 }, { 1, 161, 190 }, { 34, 130, 159 } },
799+ },
800+ { .null = { { 94, 98 }, { 224 } },
801+ .pilot = { 68, 85, 107, 124, 201, 218, 230, 247 },
802+ .ro = { { 0, 224 }, { 1, 225, 254 }, { 34, 194, 223 } },
803+ },
804+ { .null = { { 32 }, { 158, 162 } },
805+ .pilot = { 9, 26, 38, 55, 132, 149, 171, 188 },
806+ .ro = { { 0, 32 }, { 1, 33, 62 }, { 34, 2, 31 } },
807+ },
808+ { .null = { { 96 }, { 222, 226 } },
809+ .pilot = { 73, 90, 102, 119, 196, 213, 235, 252 },
810+ .ro = { { 0, 96 }, { 1, 97, 126 }, { 34, 66, 95 } },
811+ },
812+ { .null = { { 62, 66 }, { 192 } },
813+ .pilot = { 36, 53, 75, 92, 169, 186, 198, 215 },
814+ .ro = { { 0, 192 }, { 1, 193, 253 }, { 67, 131, 191 } },
815+ },
816+ { .null = { { 64 }, { 190, 194 } },
817+ .pilot = { 41, 58, 70, 87, 164, 181, 203, 220 },
818+ .ro = { { 0, 64 }, { 1, 65, 125 }, { 67, 3, 63 } },
819+ },
820+ { .null = { { 0 }, { 126, 130 } },
821+ .pilot = { 6, 23, 100, 117, 139, 156, 233, 250 },
822+ .ro = { { 0, 0, 255 } },
823+ },
824+};
825+
826+static inline u8 csi_group_idx(u8 mode, u8 ch_bw, u8 data_bw, u8 pri_ch_idx)
827+{
828+ if (ch_bw < 2 || data_bw < 1)
829+ return mode * 11 + ch_bw * ch_bw + pri_ch_idx;
830+ else
831+ return mode * 11 + ch_bw * ch_bw + (data_bw + 1) * 2 + pri_ch_idx;
832+}
833+
developera20cdc22024-05-31 18:57:31 +0800834+struct csi_mac_filter *mt7915_csi_mac_filter_find(struct mt7915_phy *phy, u8 *addr)
835+{
836+ struct csi_mac_filter *ent, *tmp_ent;
837+
838+ list_for_each_entry_safe(ent, tmp_ent, &phy->csi.mac_filter_list, node) {
839+ if (ether_addr_equal(ent->mac, addr))
840+ return ent;
841+ }
842+
843+ return NULL;
844+}
845+
846+void mt7915_csi_mac_filter_clear(struct mt7915_phy *phy)
847+{
848+ struct csi_mac_filter *ent, *tmp_ent;
849+ list_for_each_entry_safe(ent, tmp_ent, &phy->csi.mac_filter_list, node) {
850+ list_del(&ent->node);
851+ kfree(ent);
852+ }
853+
854+ phy->csi.mac_filter_cnt = 0;
855+}
856+
857+static int mt7915_vendor_reply_csi_mac_filter(struct wiphy *wiphy, struct mt7915_phy *phy)
858+{
859+ struct sk_buff *skb;
860+ struct csi_mac_filter *ent, *tmp_ent;
861+ int idx = 0;
862+ struct nlattr *a, *b;
863+
864+ mutex_lock(&phy->csi.mac_filter_lock);
865+
866+#define ENTRY_SIZE nla_total_size(nla_total_size(ETH_ALEN) + \
867+ nla_total_size(sizeof(ent->interval)))
868+
869+ skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, ENTRY_SIZE *
870+ phy->csi.mac_filter_cnt);
871+ if (!skb) {
872+ mutex_unlock(&phy->csi.mac_filter_lock);
873+ return -ENOMEM;
874+ }
875+
876+ a = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_CTRL_DUMP_MAC_FILTER);
877+
878+ list_for_each_entry_safe(ent, tmp_ent, &phy->csi.mac_filter_list, node) {
879+
880+ b = nla_nest_start(skb, idx++);
881+ nla_put(skb, MTK_VENDOR_ATTR_CSI_MAC_FILTER_MAC,
882+ ETH_ALEN, ent->mac);
883+ nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_MAC_FILTER_INTERVAL, ent->interval);
884+ nla_nest_end(skb, b);
885+ }
886+
887+ nla_nest_end(skb, a);
888+#undef ENTRY_SIZE
889+
890+ mutex_unlock(&phy->csi.mac_filter_lock);
891+
892+ return cfg80211_vendor_cmd_reply(skb);
893+}
894+
developer73e5a572022-04-19 10:21:20 +0800895+static int mt7915_vendor_csi_ctrl(struct wiphy *wiphy,
896+ struct wireless_dev *wdev,
897+ const void *data,
898+ int data_len)
899+{
900+ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
901+ struct mt7915_phy *phy = mt7915_hw_phy(hw);
902+ struct nlattr *tb[NUM_MTK_VENDOR_ATTRS_CSI_CTRL];
903+ int err;
904+
905+ err = nla_parse(tb, MTK_VENDOR_ATTR_CSI_CTRL_MAX, data, data_len,
906+ csi_ctrl_policy, NULL);
907+ if (err)
908+ return err;
909+
developer1a173672023-12-21 14:49:33 +0800910+ if (is_mt7915(phy->mt76->dev) && phy->mt76->chandef.width > NL80211_CHAN_WIDTH_80) {
911+ err = -EINVAL;
912+ return err;
913+ }
914+
developer73e5a572022-04-19 10:21:20 +0800915+ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_CFG]) {
916+ u8 mode = 0, type = 0, v1 = 0, v2 = 0;
917+ u8 mac_addr[ETH_ALEN] = {};
918+ struct nlattr *cur;
919+ int rem;
developer1a173672023-12-21 14:49:33 +0800920+ u32 sta_interval = 0;
developer73e5a572022-04-19 10:21:20 +0800921+
922+ nla_for_each_nested(cur, tb[MTK_VENDOR_ATTR_CSI_CTRL_CFG], rem) {
developer1a173672023-12-21 14:49:33 +0800923+ switch (nla_type(cur)) {
developer73e5a572022-04-19 10:21:20 +0800924+ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE:
925+ mode = nla_get_u8(cur);
926+ break;
927+ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE:
928+ type = nla_get_u8(cur);
929+ break;
930+ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1:
931+ v1 = nla_get_u8(cur);
932+ break;
933+ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2:
934+ v2 = nla_get_u8(cur);
935+ break;
936+ default:
937+ return -EINVAL;
938+ };
939+ }
940+
941+ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR]) {
942+ int idx = 0;
943+
944+ nla_for_each_nested(cur, tb[MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR], rem) {
945+ mac_addr[idx++] = nla_get_u8(cur);
946+ }
developer1a173672023-12-21 14:49:33 +0800947+
948+ /* when configure mac filter, add interval for report interval per sta */
949+ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_STA_INTERVAL])
950+ sta_interval =
951+ nla_get_u32(tb[MTK_VENDOR_ATTR_CSI_CTRL_STA_INTERVAL]);
developer73e5a572022-04-19 10:21:20 +0800952+ }
953+
developera20cdc22024-05-31 18:57:31 +0800954+ if (mode == 0) {
955+ mutex_lock(&phy->csi.mac_filter_lock);
developer1a173672023-12-21 14:49:33 +0800956+
developera20cdc22024-05-31 18:57:31 +0800957+ err = mt7915_mcu_set_csi(phy, mode, type, v1, v2,
958+ mac_addr, sta_interval);
959+ if (err) {
960+ mutex_unlock(&phy->csi.mac_filter_lock);
961+ return err;
962+ }
963+
964+ mt7915_csi_mac_filter_clear(phy);
965+
966+ mutex_unlock(&phy->csi.mac_filter_lock);
967+ } else if (mode == 2 && type == 8 && v1 == 1 && (v2 == ADD_CSI_MAC || v2 == DEL_CSI_MAC)) {
968+ struct csi_mac_filter *ent;
969+
970+ mutex_lock(&phy->csi.mac_filter_lock);
971+
972+ if (v2 == DEL_CSI_MAC) {
973+ ent = mt7915_csi_mac_filter_find(phy, mac_addr);
974+ if (!ent) {
975+ mutex_unlock(&phy->csi.mac_filter_lock);
976+ return -ENOENT;
977+ }
978+ } else {
979+ if (is_mt7915(phy->mt76->dev)) {
980+ if (phy->csi.mac_filter_cnt >= MAX_CSI_MAC_NUM) {
981+ mutex_unlock(&phy->csi.mac_filter_lock);
982+ return -ENOSPC;
983+ }
984+ } else {
985+ if (phy->csi.mac_filter_cnt >= MAX_CSI_MAC_NUM/2) {
986+ mutex_unlock(&phy->csi.mac_filter_lock);
987+ return -ENOSPC;
988+ }
989+ }
990+
991+ ent = mt7915_csi_mac_filter_find(phy, mac_addr);
992+ if (ent) {
993+ mutex_unlock(&phy->csi.mac_filter_lock);
994+ return -EEXIST;
995+ }
996+
997+ ent = kzalloc(sizeof(*ent), GFP_KERNEL);
998+ if (!ent) {
999+ mutex_unlock(&phy->csi.mac_filter_lock);
1000+ return -ENOMEM;
1001+ }
1002+
1003+ ether_addr_copy(ent->mac, mac_addr);
1004+ ent->interval = sta_interval;
1005+ }
developer73e5a572022-04-19 10:21:20 +08001006+
developera20cdc22024-05-31 18:57:31 +08001007+ err = mt7915_mcu_set_csi(phy, mode, type, v1, v2,
1008+ mac_addr, sta_interval);
1009+ if (err) {
1010+ if (v2 == ADD_CSI_MAC)
1011+ kfree(ent);
1012+ mutex_unlock(&phy->csi.mac_filter_lock);
1013+ return err;
1014+ }
1015+
1016+ if (v2 == DEL_CSI_MAC) {
1017+ list_del(&ent->node);
1018+ kfree(ent);
1019+ phy->csi.mac_filter_cnt--;
1020+ } else {
1021+ list_add_tail(&ent->node, &phy->csi.mac_filter_list);
1022+ phy->csi.mac_filter_cnt++;
1023+ }
1024+
1025+ mutex_unlock(&phy->csi.mac_filter_lock);
1026+ } else if (mode == 2 && type == 8 && v1 == 1 && v2 == SHOW_CSI_MAC) {
1027+ return mt7915_vendor_reply_csi_mac_filter(wiphy, phy);
1028+ } else {
1029+ err = mt7915_mcu_set_csi(phy, mode, type, v1, v2,
1030+ mac_addr, sta_interval);
1031+ if (err)
1032+ return err;
1033+ }
developer73e5a572022-04-19 10:21:20 +08001034+
1035+ phy->csi.enable = !!mode;
1036+
1037+ if (mode == 2 && type == 5) {
1038+ if (v1 >= 1)
1039+ phy->csi.mask = 1;
1040+ if (v1 == 2)
1041+ phy->csi.reorder = 1;
1042+ }
1043+
1044+ /* clean up old csi stats */
developera20cdc22024-05-31 18:57:31 +08001045+ if (mode == 0 && !list_empty(&phy->csi.data_list)) {
developer73e5a572022-04-19 10:21:20 +08001046+ struct csi_data *c, *tmp_c;
1047+
developera20cdc22024-05-31 18:57:31 +08001048+ spin_lock_bh(&phy->csi.data_lock);
1049+ list_for_each_entry_safe(c, tmp_c, &phy->csi.data_list,
developer73e5a572022-04-19 10:21:20 +08001050+ node) {
1051+ list_del(&c->node);
1052+ kfree(c);
1053+ phy->csi.count--;
1054+ }
developera20cdc22024-05-31 18:57:31 +08001055+ spin_unlock_bh(&phy->csi.data_lock);
developer73e5a572022-04-19 10:21:20 +08001056+ } else if (mode == 1) {
1057+ phy->csi.last_record = 0;
1058+ }
developer73e5a572022-04-19 10:21:20 +08001059+ }
1060+
1061+ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL])
1062+ phy->csi.interval = nla_get_u32(tb[MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL]);
1063+
1064+ return 0;
1065+}
1066+
1067+static void
1068+mt7915_vendor_csi_tone_mask(struct mt7915_phy *phy, struct csi_data *csi)
1069+{
1070+ static const u8 mode_map[] = {
1071+ [MT_PHY_TYPE_OFDM] = 0,
1072+ [MT_PHY_TYPE_HT] = 1,
1073+ [MT_PHY_TYPE_VHT] = 1,
1074+ [MT_PHY_TYPE_HE_SU] = 2,
1075+ };
1076+ const struct csi_mask *cmask;
1077+ int i;
1078+
1079+ if (csi->rx_mode == MT_PHY_TYPE_CCK || !phy->csi.mask)
1080+ return;
1081+
1082+ if (csi->data_bw == IEEE80211_STA_RX_BW_40)
1083+ csi->pri_ch_idx /= 2;
1084+
1085+ cmask = &csi_mask_groups[csi_group_idx(mode_map[csi->rx_mode],
1086+ csi->ch_bw,
1087+ csi->data_bw,
1088+ csi->pri_ch_idx)];
1089+
1090+ for (i = 0; i < 10; i++) {
1091+ const struct csi_null_tone *ntone = &cmask->null[i];
1092+ u8 start = ntone->start;
1093+ u8 end = ntone->end;
1094+ int j;
1095+
1096+ if (!start && !end && i > 0)
1097+ break;
1098+
1099+ if (!end)
1100+ end = start;
1101+
1102+ for (j = start; j <= end; j++) {
1103+ csi->data_i[j] = 0;
1104+ csi->data_q[j] = 0;
1105+ }
1106+ }
1107+
1108+ for (i = 0; i < 8; i++) {
1109+ u8 pilot = cmask->pilot[i];
1110+
1111+ if (!pilot)
1112+ break;
1113+
1114+ csi->data_i[pilot] = 0;
1115+ csi->data_q[pilot] = 0;
1116+ }
1117+
1118+ if (!phy->csi.reorder)
1119+ return;
1120+
1121+ for (i = 0; i < 3; i++) {
1122+ const struct csi_reorder *ro = &cmask->ro[i];
1123+ u8 dest = ro->dest;
1124+ u8 start = ro->start;
1125+ u8 end = ro->end;
1126+
1127+ if (!dest && !start && !end)
1128+ break;
1129+
1130+ if (dest == start)
1131+ continue;
1132+
1133+ if (end) {
1134+ memmove(&csi->data_i[dest], &csi->data_i[start],
1135+ end - start + 1);
1136+ memmove(&csi->data_q[dest], &csi->data_q[start],
1137+ end - start + 1);
1138+ } else {
1139+ csi->data_i[dest] = csi->data_i[start];
1140+ csi->data_q[dest] = csi->data_q[start];
1141+ }
1142+ }
1143+}
1144+
1145+static int
1146+mt7915_vendor_csi_ctrl_dump(struct wiphy *wiphy, struct wireless_dev *wdev,
1147+ struct sk_buff *skb, const void *data, int data_len,
1148+ unsigned long *storage)
1149+{
1150+#define RESERVED_SET BIT(31)
1151+ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1152+ struct mt7915_phy *phy = mt7915_hw_phy(hw);
1153+ struct nlattr *tb[NUM_MTK_VENDOR_ATTRS_CSI_CTRL];
1154+ int err = 0;
1155+
1156+ if (*storage & RESERVED_SET) {
1157+ if ((*storage & GENMASK(15, 0)) == 0)
1158+ return -ENOENT;
1159+ (*storage)--;
1160+ }
1161+
1162+ if (data) {
1163+ err = nla_parse(tb, MTK_VENDOR_ATTR_CSI_CTRL_MAX, data, data_len,
1164+ csi_ctrl_policy, NULL);
1165+ if (err)
1166+ return err;
1167+ }
1168+
1169+ if (!(*storage & RESERVED_SET) && tb[MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM]) {
1170+ *storage = nla_get_u16(tb[MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM]);
1171+ *storage |= RESERVED_SET;
1172+ }
1173+
developera20cdc22024-05-31 18:57:31 +08001174+ spin_lock_bh(&phy->csi.data_lock);
developer73e5a572022-04-19 10:21:20 +08001175+
developera20cdc22024-05-31 18:57:31 +08001176+ if (!list_empty(&phy->csi.data_list)) {
developer73e5a572022-04-19 10:21:20 +08001177+ struct csi_data *csi;
1178+ void *a, *b;
1179+ int i;
1180+
developera20cdc22024-05-31 18:57:31 +08001181+ csi = list_first_entry(&phy->csi.data_list, struct csi_data, node);
developer73e5a572022-04-19 10:21:20 +08001182+
1183+ mt7915_vendor_csi_tone_mask(phy, csi);
1184+
1185+ a = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_CTRL_DATA);
1186+
1187+ if (nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_VER, 1) ||
1188+ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_RSSI, csi->rssi) ||
1189+ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_SNR, csi->snr) ||
1190+ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_BW, csi->data_bw) ||
1191+ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_CH_IDX, csi->pri_ch_idx) ||
1192+ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_MODE, csi->rx_mode))
1193+ goto out;
1194+
1195+ if (nla_put_u16(skb, MTK_VENDOR_ATTR_CSI_DATA_TX_ANT, csi->tx_idx) ||
1196+ nla_put_u16(skb, MTK_VENDOR_ATTR_CSI_DATA_RX_ANT, csi->rx_idx))
1197+ goto out;
1198+
developer1a173672023-12-21 14:49:33 +08001199+ if (nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_INFO, csi->ext_info) ||
1200+ nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_CHAIN_INFO, csi->chain_info) ||
developer73e5a572022-04-19 10:21:20 +08001201+ nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_TS, csi->ts))
1202+ goto out;
1203+
1204+ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_TA);
developer1a173672023-12-21 14:49:33 +08001205+ for (i = 0; i < ARRAY_SIZE(csi->ta); i++)
1206+ if (nla_put_u8(skb, i, csi->ta[i]))
1207+ goto out;
developer73e5a572022-04-19 10:21:20 +08001208+ nla_nest_end(skb, b);
1209+
developer1a173672023-12-21 14:49:33 +08001210+ if (nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_NUM, csi->data_num))
1211+ goto out;
1212+
developer73e5a572022-04-19 10:21:20 +08001213+ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_I);
developer1a173672023-12-21 14:49:33 +08001214+ for (i = 0; i < csi->data_num; i++)
1215+ if (nla_put_u16(skb, i, csi->data_i[i]))
1216+ goto out;
developer73e5a572022-04-19 10:21:20 +08001217+ nla_nest_end(skb, b);
1218+
1219+ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_Q);
developer1a173672023-12-21 14:49:33 +08001220+ for (i = 0; i < csi->data_num; i++)
1221+ if (nla_put_u16(skb, i, csi->data_q[i]))
1222+ goto out;
developer73e5a572022-04-19 10:21:20 +08001223+ nla_nest_end(skb, b);
1224+
1225+ nla_nest_end(skb, a);
1226+
1227+ list_del(&csi->node);
1228+ kfree(csi);
1229+ phy->csi.count--;
1230+
1231+ err = phy->csi.count;
1232+ }
1233+out:
developera20cdc22024-05-31 18:57:31 +08001234+ spin_unlock_bh(&phy->csi.data_lock);
developer73e5a572022-04-19 10:21:20 +08001235+
1236+ return err;
1237+}
1238+
1239+static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
1240+ {
1241+ .info = {
1242+ .vendor_id = MTK_NL80211_VENDOR_ID,
1243+ .subcmd = MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL,
1244+ },
1245+ .flags = WIPHY_VENDOR_CMD_NEED_NETDEV |
1246+ WIPHY_VENDOR_CMD_NEED_RUNNING,
1247+ .doit = mt7915_vendor_csi_ctrl,
1248+ .dumpit = mt7915_vendor_csi_ctrl_dump,
1249+ .policy = csi_ctrl_policy,
1250+ .maxattr = MTK_VENDOR_ATTR_CSI_CTRL_MAX,
1251+ }
1252+};
1253+
1254+void mt7915_vendor_register(struct mt7915_phy *phy)
1255+{
1256+ phy->mt76->hw->wiphy->vendor_commands = mt7915_vendor_commands;
1257+ phy->mt76->hw->wiphy->n_vendor_commands = ARRAY_SIZE(mt7915_vendor_commands);
1258+}
1259diff --git a/mt7915/vendor.h b/mt7915/vendor.h
1260new file mode 100644
developer05f3b2b2024-08-19 19:17:34 +08001261index 00000000..d2b90aa0
developer73e5a572022-04-19 10:21:20 +08001262--- /dev/null
1263+++ b/mt7915/vendor.h
developera20cdc22024-05-31 18:57:31 +08001264@@ -0,0 +1,75 @@
developer1a173672023-12-21 14:49:33 +08001265+/* SPDX-License-Identifier: ISC */
developer73e5a572022-04-19 10:21:20 +08001266+#ifndef __MT7915_VENDOR_H
1267+#define __MT7915_VENDOR_H
1268+
1269+#define MTK_NL80211_VENDOR_ID 0x0ce7
1270+
1271+enum mtk_nl80211_vendor_subcmds {
1272+ MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL = 0xc2,
1273+};
1274+
1275+enum mtk_vendor_attr_csi_ctrl {
1276+ MTK_VENDOR_ATTR_CSI_CTRL_UNSPEC,
1277+
1278+ MTK_VENDOR_ATTR_CSI_CTRL_CFG,
1279+ MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE,
1280+ MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE,
1281+ MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1,
1282+ MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2,
1283+ MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR,
1284+ MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL,
developer1a173672023-12-21 14:49:33 +08001285+ MTK_VENDOR_ATTR_CSI_CTRL_STA_INTERVAL,
developer73e5a572022-04-19 10:21:20 +08001286+
1287+ MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM,
1288+
1289+ MTK_VENDOR_ATTR_CSI_CTRL_DATA,
developera20cdc22024-05-31 18:57:31 +08001290+ MTK_VENDOR_ATTR_CSI_CTRL_DUMP_MAC_FILTER,
developer73e5a572022-04-19 10:21:20 +08001291+
1292+ /* keep last */
1293+ NUM_MTK_VENDOR_ATTRS_CSI_CTRL,
1294+ MTK_VENDOR_ATTR_CSI_CTRL_MAX =
1295+ NUM_MTK_VENDOR_ATTRS_CSI_CTRL - 1
1296+};
1297+
1298+enum mtk_vendor_attr_csi_data {
1299+ MTK_VENDOR_ATTR_CSI_DATA_UNSPEC,
1300+ MTK_VENDOR_ATTR_CSI_DATA_PAD,
1301+
1302+ MTK_VENDOR_ATTR_CSI_DATA_VER,
1303+ MTK_VENDOR_ATTR_CSI_DATA_TS,
1304+ MTK_VENDOR_ATTR_CSI_DATA_RSSI,
1305+ MTK_VENDOR_ATTR_CSI_DATA_SNR,
1306+ MTK_VENDOR_ATTR_CSI_DATA_BW,
1307+ MTK_VENDOR_ATTR_CSI_DATA_CH_IDX,
1308+ MTK_VENDOR_ATTR_CSI_DATA_TA,
developer1a173672023-12-21 14:49:33 +08001309+ MTK_VENDOR_ATTR_CSI_DATA_NUM,
developer73e5a572022-04-19 10:21:20 +08001310+ MTK_VENDOR_ATTR_CSI_DATA_I,
1311+ MTK_VENDOR_ATTR_CSI_DATA_Q,
1312+ MTK_VENDOR_ATTR_CSI_DATA_INFO,
1313+ MTK_VENDOR_ATTR_CSI_DATA_RSVD1,
1314+ MTK_VENDOR_ATTR_CSI_DATA_RSVD2,
1315+ MTK_VENDOR_ATTR_CSI_DATA_RSVD3,
1316+ MTK_VENDOR_ATTR_CSI_DATA_RSVD4,
1317+ MTK_VENDOR_ATTR_CSI_DATA_TX_ANT,
1318+ MTK_VENDOR_ATTR_CSI_DATA_RX_ANT,
1319+ MTK_VENDOR_ATTR_CSI_DATA_MODE,
developer1a173672023-12-21 14:49:33 +08001320+ MTK_VENDOR_ATTR_CSI_DATA_CHAIN_INFO,
developer73e5a572022-04-19 10:21:20 +08001321+
1322+ /* keep last */
1323+ NUM_MTK_VENDOR_ATTRS_CSI_DATA,
1324+ MTK_VENDOR_ATTR_CSI_DATA_MAX =
1325+ NUM_MTK_VENDOR_ATTRS_CSI_DATA - 1
1326+};
1327+
developera20cdc22024-05-31 18:57:31 +08001328+enum mtk_vendor_attr_csi_mac_filter {
1329+ MTK_VENDOR_ATTR_CSI_MAC_FILTER_UNSPEC,
1330+
1331+ MTK_VENDOR_ATTR_CSI_MAC_FILTER_MAC,
1332+ MTK_VENDOR_ATTR_CSI_MAC_FILTER_INTERVAL,
1333+
1334+ /* keep last */
1335+ NUM_MTK_VENDOR_ATTRS_CSI_MAC_FILTER,
1336+ MTK_VENDOR_ATTR_CSI_MAC_FILTER_MAX =
1337+ NUM_MTK_VENDOR_ATTRS_CSI_MAC_FILTER - 1
1338+};
developer73e5a572022-04-19 10:21:20 +08001339+#endif
1340--
developerbd9fa1e2023-10-16 11:04:00 +080013412.18.0
developer73e5a572022-04-19 10:21:20 +08001342