blob: aac1628582754145378d30b90251a27b44b77b42 [file] [log] [blame]
developer05f3b2b2024-08-19 19:17:34 +08001From a95ba55c6e8e2662d7278f0530f3aa75c4f4a798 Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +08002From: Peter Chiu <chui-hao.chiu@mediatek.com>
3Date: Wed, 19 Apr 2023 18:32:41 +0800
developer05f3b2b2024-08-19 19:17:34 +08004Subject: [PATCH 064/199] mtk: mt76: add random early drop support
developer66e89bc2024-04-23 14:50:01 +08005
6---
7 mt7996/debugfs.c | 1 +
8 mt7996/mac.c | 7 ++++
9 mt7996/mcu.c | 81 ++++++++++++++++++++++++++++++++++++++++++--
10 mt7996/mcu.h | 4 ++-
11 mt7996/mt7996.h | 5 ++-
12 mt7996/mtk_debugfs.c | 23 +++++++++++++
13 mt7996/mtk_mcu.c | 26 ++++++++++++++
14 mt7996/mtk_mcu.h | 24 +++++++++++++
15 8 files changed, 167 insertions(+), 4 deletions(-)
16
17diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c
developer05f3b2b2024-08-19 19:17:34 +080018index 6d119467..3301701a 100644
developer66e89bc2024-04-23 14:50:01 +080019--- a/mt7996/debugfs.c
20+++ b/mt7996/debugfs.c
developer05f3b2b2024-08-19 19:17:34 +080021@@ -633,6 +633,7 @@ mt7996_tx_stats_show(struct seq_file *file, void *data)
developer66e89bc2024-04-23 14:50:01 +080022 seq_printf(file, "Tx attempts: %8u (MPDUs)\n", attempts);
23 seq_printf(file, "Tx success: %8u (MPDUs)\n", success);
24 seq_printf(file, "Tx PER: %u%%\n", per);
25+ seq_printf(file, "Tx RED drop: %8u\n", phy->red_drop);
26
27 mt7996_txbf_stat_read_phy(phy, file);
28
29diff --git a/mt7996/mac.c b/mt7996/mac.c
developer05f3b2b2024-08-19 19:17:34 +080030index bcddff23..0c2fee66 100644
developer66e89bc2024-04-23 14:50:01 +080031--- a/mt7996/mac.c
32+++ b/mt7996/mac.c
developer05f3b2b2024-08-19 19:17:34 +080033@@ -1179,6 +1179,13 @@ mt7996_mac_tx_free(struct mt7996_dev *dev, void *data, int len)
developer66e89bc2024-04-23 14:50:01 +080034
35 wcid->stats.tx_retries += tx_retries;
36 wcid->stats.tx_failed += tx_failed;
37+
38+ if (FIELD_GET(MT_TXFREE_INFO_STAT, info) == 2) {
39+ struct mt7996_phy *mphy =
40+ __mt7996_phy(dev, wcid->phy_idx);
41+
42+ mphy->red_drop++;
43+ }
44 continue;
45 }
46
47diff --git a/mt7996/mcu.c b/mt7996/mcu.c
developer05f3b2b2024-08-19 19:17:34 +080048index 9bef1274..7fa44f84 100644
developer66e89bc2024-04-23 14:50:01 +080049--- a/mt7996/mcu.c
50+++ b/mt7996/mcu.c
developer05f3b2b2024-08-19 19:17:34 +080051@@ -3150,8 +3150,8 @@ int mt7996_mcu_init_firmware(struct mt7996_dev *dev)
developer66e89bc2024-04-23 14:50:01 +080052 if (ret)
53 return ret;
54
55- return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
56- MCU_WA_PARAM_RED, 0, 0);
57+ return mt7996_mcu_red_config(dev,
58+ mtk_wed_device_active(&dev->mt76.mmio.wed));
59 }
60
61 int mt7996_mcu_init(struct mt7996_dev *dev)
developer05f3b2b2024-08-19 19:17:34 +080062@@ -3183,6 +3183,83 @@ out:
developer66e89bc2024-04-23 14:50:01 +080063 skb_queue_purge(&dev->mt76.mcu.res_q);
64 }
65
66+static int mt7996_mcu_wa_red_config(struct mt7996_dev *dev)
67+{
68+#define RED_TOKEN_SRC_CNT 4
69+#define RED_TOKEN_CONFIG 2
70+ struct {
71+ __le32 arg0;
72+ __le32 arg1;
73+ __le32 arg2;
74+
75+ u8 mode;
76+ u8 version;
77+ u8 _rsv[4];
78+ __le16 len;
79+
80+ __le16 tcp_offset;
81+ __le16 priority_offset;
82+ __le16 token_per_src[RED_TOKEN_SRC_CNT];
83+ __le16 token_thr_per_src[RED_TOKEN_SRC_CNT];
84+
85+ u8 _rsv2[604];
86+ } __packed req = {
87+ .arg0 = cpu_to_le32(MCU_WA_PARAM_RED_CONFIG),
88+
89+ .mode = RED_TOKEN_CONFIG,
90+ .len = cpu_to_le16(sizeof(req) - sizeof(__le32) * 3),
91+
92+ .tcp_offset = cpu_to_le16(200),
93+ .priority_offset = cpu_to_le16(255),
94+ };
95+ u8 i;
96+
97+ for (i = 0; i < RED_TOKEN_SRC_CNT; i++) {
98+ req.token_per_src[i] = cpu_to_le16(MT7996_TOKEN_SIZE);
99+ req.token_thr_per_src[i] = cpu_to_le16(MT7996_TOKEN_SIZE);
100+ }
101+
102+ if (!mtk_wed_device_active(&dev->mt76.mmio.wed))
103+ req.token_per_src[RED_TOKEN_SRC_CNT - 1] =
104+ cpu_to_le16(MT7996_TOKEN_SIZE - MT7996_HW_TOKEN_SIZE);
105+
106+ return mt76_mcu_send_msg(&dev->mt76, MCU_WA_PARAM_CMD(SET),
107+ &req, sizeof(req), false);
108+}
109+
110+int mt7996_mcu_red_config(struct mt7996_dev *dev, bool enable)
111+{
112+#define RED_DISABLE 0
113+#define RED_BY_WA_ENABLE 2
114+ struct {
115+ u8 __rsv1[4];
116+
117+ __le16 tag;
118+ __le16 len;
119+ u8 enable;
120+ u8 __rsv2[3];
121+ } __packed req = {
122+ .tag = cpu_to_le16(UNI_VOW_RED_ENABLE),
123+ .len = cpu_to_le16(sizeof(req) - 4),
124+ .enable = enable ? RED_BY_WA_ENABLE : RED_DISABLE,
125+ };
126+ int ret;
127+
128+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(VOW), &req,
129+ sizeof(req), true);
130+
131+ if (ret)
132+ return ret;
133+
134+ ret = mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
135+ MCU_WA_PARAM_RED_EN, enable, 0);
136+
137+ if (ret || !enable)
138+ return ret;
139+
140+ return mt7996_mcu_wa_red_config(dev);
141+}
142+
143 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans)
144 {
145 struct {
146diff --git a/mt7996/mcu.h b/mt7996/mcu.h
developer05f3b2b2024-08-19 19:17:34 +0800147index 3025f849..23db3b33 100644
developer66e89bc2024-04-23 14:50:01 +0800148--- a/mt7996/mcu.h
149+++ b/mt7996/mcu.h
150@@ -346,8 +346,9 @@ enum {
151 enum {
152 MCU_WA_PARAM_PDMA_RX = 0x04,
153 MCU_WA_PARAM_CPU_UTIL = 0x0b,
154- MCU_WA_PARAM_RED = 0x0e,
155+ MCU_WA_PARAM_RED_EN = 0x0e,
156 MCU_WA_PARAM_HW_PATH_HIF_VER = 0x2f,
157+ MCU_WA_PARAM_RED_CONFIG = 0x40,
158 };
159
160 enum mcu_mmps_mode {
161@@ -920,6 +921,7 @@ enum {
162 UNI_VOW_DRR_CTRL,
163 UNI_VOW_RX_AT_AIRTIME_EN = 0x0b,
164 UNI_VOW_RX_AT_AIRTIME_CLR_EN = 0x0e,
165+ UNI_VOW_RED_ENABLE = 0x18,
166 };
167
168 enum {
169diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
developer05f3b2b2024-08-19 19:17:34 +0800170index 784fb3db..d40f95cd 100644
developer66e89bc2024-04-23 14:50:01 +0800171--- a/mt7996/mt7996.h
172+++ b/mt7996/mt7996.h
developer05f3b2b2024-08-19 19:17:34 +0800173@@ -355,6 +355,7 @@ struct mt7996_phy {
developer66e89bc2024-04-23 14:50:01 +0800174 u16 punct_bitmap;
175
176 struct mt7996_scs_ctrl scs_ctrl;
177+ u32 red_drop;
178
179 bool sku_limit_en;
180 bool sku_path_en;
developer05f3b2b2024-08-19 19:17:34 +0800181@@ -724,6 +725,7 @@ int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set)
developer66e89bc2024-04-23 14:50:01 +0800182 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
183 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);
184 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
185+int mt7996_mcu_red_config(struct mt7996_dev *dev, bool enable);
186 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);
187 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);
188 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev);
developer05f3b2b2024-08-19 19:17:34 +0800189@@ -897,11 +899,12 @@ void mt7996_mcu_set_ppdu_tx_type(struct mt7996_phy *phy, u8 ppdu_type);
developer66e89bc2024-04-23 14:50:01 +0800190 void mt7996_mcu_set_nusers_ofdma(struct mt7996_phy *phy, u8 type, u8 ofdma_user_cnt);
191 void mt7996_mcu_set_cert(struct mt7996_phy *phy, u8 type);
192 void mt7996_tm_update_channel(struct mt7996_phy *phy);
193+
194+int mt7996_mcu_set_vow_drr_dbg(struct mt7996_dev *dev, u32 val);
195 #endif
196
197 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
198 int mt7996_dma_rro_init(struct mt7996_dev *dev);
199 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
200
201-
202 #endif
203diff --git a/mt7996/mtk_debugfs.c b/mt7996/mtk_debugfs.c
developer05f3b2b2024-08-19 19:17:34 +0800204index 05cfc6ab..1f754796 100644
developer66e89bc2024-04-23 14:50:01 +0800205--- a/mt7996/mtk_debugfs.c
206+++ b/mt7996/mtk_debugfs.c
developer05f3b2b2024-08-19 19:17:34 +0800207@@ -3033,6 +3033,27 @@ static int mt7996_muru_prot_thr_set(void *data, u64 val)
developer66e89bc2024-04-23 14:50:01 +0800208 DEFINE_DEBUGFS_ATTRIBUTE(fops_muru_prot_thr, NULL,
209 mt7996_muru_prot_thr_set, "%lld\n");
210
211+static int
212+mt7996_red_config_set(void *data, u64 val)
213+{
214+ struct mt7996_dev *dev = data;
215+
216+ return mt7996_mcu_red_config(dev, !!val);
217+}
218+
219+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_config, NULL,
220+ mt7996_red_config_set, "%lld\n");
221+
222+static int
223+mt7996_vow_drr_dbg(void *data, u64 val)
224+{
225+ struct mt7996_dev *dev = data;
226+
227+ return mt7996_mcu_set_vow_drr_dbg(dev, (u32)val);
228+}
229+DEFINE_DEBUGFS_ATTRIBUTE(fops_vow_drr_dbg, NULL,
230+ mt7996_vow_drr_dbg, "%lld\n");
231+
232 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir)
233 {
234 struct mt7996_dev *dev = phy->dev;
developer05f3b2b2024-08-19 19:17:34 +0800235@@ -3109,6 +3130,8 @@ int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir)
developer66e89bc2024-04-23 14:50:01 +0800236 mt7996_wtbl_read);
237
238 debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir, mt7996_token_read);
239+ debugfs_create_file("red", 0200, dir, dev, &fops_red_config);
240+ debugfs_create_file("vow_drr_dbg", 0200, dir, dev, &fops_vow_drr_dbg);
241
242 debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
243 debugfs_create_file("scs_enable", 0200, dir, phy, &fops_scs_enable);
244diff --git a/mt7996/mtk_mcu.c b/mt7996/mtk_mcu.c
developer05f3b2b2024-08-19 19:17:34 +0800245index b46a66bb..967ee874 100644
developer66e89bc2024-04-23 14:50:01 +0800246--- a/mt7996/mtk_mcu.c
247+++ b/mt7996/mtk_mcu.c
developer05f3b2b2024-08-19 19:17:34 +0800248@@ -1317,4 +1317,30 @@ void mt7996_mcu_set_cert(struct mt7996_phy *phy, u8 type)
developer66e89bc2024-04-23 14:50:01 +0800249 sizeof(req), false);
250 }
251
252+int mt7996_mcu_set_vow_drr_dbg(struct mt7996_dev *dev, u32 val)
253+{
254+#define MT7996_VOW_DEBUG_MODE 0xe
255+ struct {
256+ u8 __rsv1[4];
257+
258+ __le16 tag;
259+ __le16 len;
260+ u8 __rsv2[4];
261+ __le32 action;
262+ __le32 val;
263+ u8 __rsv3[8];
264+ } __packed req = {
265+ .tag = cpu_to_le16(UNI_VOW_DRR_CTRL),
266+ .len = cpu_to_le16(sizeof(req) - 4),
267+ .action = cpu_to_le32(MT7996_VOW_DEBUG_MODE),
268+ .val = cpu_to_le32(val),
269+ };
270+
271+ if (val & ~VOW_DRR_DBG_FLAGS)
272+ return -EINVAL;
273+
274+ return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(VOW), &req,
275+ sizeof(req), true);
276+}
277+
278 #endif
279diff --git a/mt7996/mtk_mcu.h b/mt7996/mtk_mcu.h
developer05f3b2b2024-08-19 19:17:34 +0800280index 58d61c51..2cffc893 100644
developer66e89bc2024-04-23 14:50:01 +0800281--- a/mt7996/mtk_mcu.h
282+++ b/mt7996/mtk_mcu.h
283@@ -1138,6 +1138,30 @@ enum muru_vendor_ctrl {
284 MU_CTRL_DL_USER_CNT,
285 MU_CTRL_UL_USER_CNT,
286 };
287+
288+enum {
289+ VOW_DRR_DBG_DUMP_BMP = BIT(0),
290+ VOW_DRR_DBG_EST_AT_PRINT = BIT(1),
291+ VOW_DRR_DBG_ADJ_GLOBAL_THLD = BIT(21),
292+ VOW_DRR_DBG_PRN_LOUD = BIT(22),
293+ VOW_DRR_DBG_PRN_ADJ_STA = BIT(23),
294+ VOW_DRR_DBG_FIX_CR = GENMASK(27, 24),
295+ VOW_DRR_DBG_CLR_FIX_CR = BIT(28),
296+ VOW_DRR_DBG_DISABLE = BIT(29),
297+ VOW_DRR_DBG_DUMP_CR = BIT(30),
298+ VOW_DRR_DBG_PRN = BIT(31)
299+};
300+
301+#define VOW_DRR_DBG_FLAGS (VOW_DRR_DBG_DUMP_BMP | \
302+ VOW_DRR_DBG_EST_AT_PRINT | \
303+ VOW_DRR_DBG_ADJ_GLOBAL_THLD | \
304+ VOW_DRR_DBG_PRN_LOUD | \
305+ VOW_DRR_DBG_PRN_ADJ_STA | \
306+ VOW_DRR_DBG_FIX_CR | \
307+ VOW_DRR_DBG_CLR_FIX_CR | \
308+ VOW_DRR_DBG_DISABLE | \
309+ VOW_DRR_DBG_DUMP_CR | \
310+ VOW_DRR_DBG_PRN)
311 #endif
312
313 #endif
314--
developer9237f442024-06-14 17:13:04 +08003152.18.0
developer66e89bc2024-04-23 14:50:01 +0800316