blob: d574613d9cd130573931a06ec666c5eb83706b5b [file] [log] [blame]
developer05f3b2b2024-08-19 19:17:34 +08001From 4a53b4dbb4c727e79752c35c588cb6ebb82d072a Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +08002From: Bo Jiao <Bo.Jiao@mediatek.com>
3Date: Tue, 21 Nov 2023 09:55:46 +0800
developer05f3b2b2024-08-19 19:17:34 +08004Subject: [PATCH 045/199] mtk: mt76: mt7996: add SER overlap handle
developer66e89bc2024-04-23 14:50:01 +08005
developer66e89bc2024-04-23 14:50:01 +08006Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com>
7---
8 mcu.c | 3 ++-
9 mt7996/mac.c | 11 +++++++++++
10 mt7996/mcu.c | 8 ++++++++
11 mt7996/mt7996.h | 2 ++
12 4 files changed, 23 insertions(+), 1 deletion(-)
13
14diff --git a/mcu.c b/mcu.c
developer05f3b2b2024-08-19 19:17:34 +080015index 2926f715..a7afa2d7 100644
developer66e89bc2024-04-23 14:50:01 +080016--- a/mcu.c
17+++ b/mcu.c
18@@ -94,7 +94,8 @@ int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
19 if (retry && retry_cnt < MT76_MSG_MAX_RETRY_CNT) {
20 if (test_bit(MT76_MCU_RESET, &dev->phy.state))
21 usleep_range(200000, 500000);
22- dev_err(dev->dev, "send message %08x timeout, try again.\n", cmd);
23+ dev_err(dev->dev, "send message %08x timeout, try again(%d).\n",
24+ cmd, (MT76_MSG_MAX_RETRY_CNT - retry_cnt));
25 }
26
27 ret = dev->mcu_ops->mcu_skb_send_msg(dev, skb_tmp, cmd, &seq);
28diff --git a/mt7996/mac.c b/mt7996/mac.c
developer05f3b2b2024-08-19 19:17:34 +080029index 503a562a..63408421 100644
developer66e89bc2024-04-23 14:50:01 +080030--- a/mt7996/mac.c
31+++ b/mt7996/mac.c
developer05f3b2b2024-08-19 19:17:34 +080032@@ -1894,6 +1894,7 @@ void mt7996_mac_reset_work(struct work_struct *work)
developer66e89bc2024-04-23 14:50:01 +080033 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA))
34 return;
35
36+ dev->recovery.l1_reset_last = dev->recovery.l1_reset;
37 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.",
38 wiphy_name(dev->mt76.hw->wiphy));
39
developer05f3b2b2024-08-19 19:17:34 +080040@@ -1911,6 +1912,10 @@ void mt7996_mac_reset_work(struct work_struct *work)
developer66e89bc2024-04-23 14:50:01 +080041
42 set_bit(MT76_RESET, &dev->mphy.state);
43 set_bit(MT76_MCU_RESET, &dev->mphy.state);
44+ if (phy2)
45+ set_bit(MT76_RESET, &phy2->mt76->state);
46+ if (phy3)
47+ set_bit(MT76_RESET, &phy3->mt76->state);
48 wake_up(&dev->mt76.mcu.wait);
49
50 mt76_worker_disable(&dev->mt76.tx_worker);
developer05f3b2b2024-08-19 19:17:34 +080051@@ -2106,6 +2111,9 @@ void mt7996_coredump(struct mt7996_dev *dev, u8 state)
developer66e89bc2024-04-23 14:50:01 +080052
53 void mt7996_reset(struct mt7996_dev *dev)
54 {
55+ dev_info(dev->mt76.dev, "%s SER recovery state: 0x%08x\n",
56+ wiphy_name(dev->mt76.hw->wiphy), READ_ONCE(dev->recovery.state));
57+
58 if (!dev->recovery.hw_init_done)
59 return;
60
developer05f3b2b2024-08-19 19:17:34 +080061@@ -2125,6 +2133,9 @@ void mt7996_reset(struct mt7996_dev *dev)
developer66e89bc2024-04-23 14:50:01 +080062 return;
63 }
64
65+ if ((READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA))
66+ dev->recovery.l1_reset++;
67+
68 queue_work(dev->mt76.wq, &dev->reset_work);
69 wake_up(&dev->reset_wait);
70 }
71diff --git a/mt7996/mcu.c b/mt7996/mcu.c
developer05f3b2b2024-08-19 19:17:34 +080072index 548f6660..49a55bd3 100644
developer66e89bc2024-04-23 14:50:01 +080073--- a/mt7996/mcu.c
74+++ b/mt7996/mcu.c
75@@ -246,6 +246,14 @@ mt7996_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
76 u32 val;
77 u8 seq;
78
79+ if (dev->recovery.l1_reset_last != dev->recovery.l1_reset) {
80+ dev_info(dev->mt76.dev,"\n%s L1 SER recovery overlap, drop message %08x.",
81+ wiphy_name(dev->mt76.hw->wiphy), cmd);
82+
83+ dev_kfree_skb(skb);
84+ return -EPERM;
85+ }
86+
87 mdev->mcu.timeout = 20 * HZ;
88
89 seq = ++dev->mt76.mcu.msg_seq & 0xf;
90diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
developer05f3b2b2024-08-19 19:17:34 +080091index 9ec2090b..47a316e1 100644
developer66e89bc2024-04-23 14:50:01 +080092--- a/mt7996/mt7996.h
93+++ b/mt7996/mt7996.h
94@@ -397,6 +397,8 @@ struct mt7996_dev {
95 wait_queue_head_t reset_wait;
96 struct {
97 u32 state;
98+ u32 l1_reset;
99+ u32 l1_reset_last;
100 u32 wa_reset_count;
101 u32 wm_reset_count;
102 bool hw_full_reset:1;
103--
developer9237f442024-06-14 17:13:04 +08001042.18.0
developer66e89bc2024-04-23 14:50:01 +0800105