developer | 55a79b5 | 2022-11-18 16:01:14 +0800 | [diff] [blame] | 1 | From 50d41085e1f54e1cb308bd615052aaf5e317c8c5 Mon Sep 17 00:00:00 2001 |
developer | ec56711 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 2 | From: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 3 | Date: Wed, 28 Sep 2022 18:52:54 +0800 |
developer | 047bc18 | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 4 | Subject: [PATCH 3010/3011] mt76: mt7915: drop scatter and gather frame |
developer | ec56711 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 5 | |
| 6 | The scatter and gather frame may be incorrect because WED and WO may |
| 7 | send frames to host driver interleaved. |
| 8 | |
| 9 | Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 10 | --- |
| 11 | dma.c | 9 +++++++++ |
| 12 | dma.h | 1 + |
| 13 | mt76.h | 1 + |
| 14 | 3 files changed, 11 insertions(+) |
| 15 | |
| 16 | diff --git a/dma.c b/dma.c |
developer | 55a79b5 | 2022-11-18 16:01:14 +0800 | [diff] [blame] | 17 | index a7a4538..c106ae4 100644 |
developer | ec56711 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 18 | --- a/dma.c |
| 19 | +++ b/dma.c |
| 20 | @@ -419,6 +419,15 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, |
| 21 | |
| 22 | if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP)) |
| 23 | *drop = true; |
| 24 | + |
| 25 | + if (*more || (q->flags & MT_QFLAG_WED_FRAG)) { |
| 26 | + *drop = true; |
| 27 | + |
| 28 | + if (!(*more) && FIELD_GET(MT_DMA_CTL_WO, desc->buf1)) |
| 29 | + q->flags &= ~MT_QFLAG_WED_FRAG; |
| 30 | + else |
| 31 | + q->flags |= MT_QFLAG_WED_FRAG; |
| 32 | + } |
| 33 | } else { |
| 34 | buf_addr = e->dma_addr[0]; |
| 35 | e->buf = NULL; |
| 36 | diff --git a/dma.h b/dma.h |
developer | 55a79b5 | 2022-11-18 16:01:14 +0800 | [diff] [blame] | 37 | index 083cbca..221fcc8 100644 |
developer | ec56711 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 38 | --- a/dma.h |
| 39 | +++ b/dma.h |
| 40 | @@ -21,6 +21,7 @@ |
| 41 | #define MT_DMA_CTL_DROP BIT(14) |
| 42 | |
| 43 | #define MT_DMA_CTL_TOKEN GENMASK(31, 16) |
| 44 | +#define MT_DMA_CTL_WO BIT(8) |
| 45 | |
| 46 | #define MT_DMA_PPE_CPU_REASON GENMASK(15, 11) |
| 47 | #define MT_DMA_PPE_ENTRY GENMASK(30, 16) |
| 48 | diff --git a/mt76.h b/mt76.h |
developer | 55a79b5 | 2022-11-18 16:01:14 +0800 | [diff] [blame] | 49 | index 8011d4c..9b22551 100644 |
developer | ec56711 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 50 | --- a/mt76.h |
| 51 | +++ b/mt76.h |
| 52 | @@ -32,6 +32,7 @@ |
| 53 | #define MT_QFLAG_WED_RING GENMASK(1, 0) |
| 54 | #define MT_QFLAG_WED_TYPE GENMASK(3, 2) |
| 55 | #define MT_QFLAG_WED BIT(4) |
| 56 | +#define MT_QFLAG_WED_FRAG BIT(5) |
| 57 | |
| 58 | #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ |
| 59 | FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ |
| 60 | -- |
developer | b403ad0 | 2022-11-08 10:16:29 +0800 | [diff] [blame] | 61 | 2.18.0 |
developer | ec56711 | 2022-10-11 11:02:55 +0800 | [diff] [blame] | 62 | |