| From 39ee4e9fb5fd3ce678223147df9d9bef0ce822cd Mon Sep 17 00:00:00 2001 |
| From: Sam Shih <sam.shih@mediatek.com> |
| Date: Fri, 2 Jun 2023 13:06:15 +0800 |
| Subject: [PATCH] |
| [spi-and-storage][999-2333-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB-and-GD5F1GQ5UExxG.patch] |
| |
| --- |
| drivers/mtd/nand/spi/gigadevice.c | 21 ++++++++++++++++++++- |
| 1 file changed, 20 insertions(+), 1 deletion(-) |
| |
| diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c |
| index 937a04ce6..ce88f0c91 100644 |
| --- a/drivers/mtd/nand/spi/gigadevice.c |
| +++ b/drivers/mtd/nand/spi/gigadevice.c |
| @@ -39,6 +39,15 @@ static SPINAND_OP_VARIANTS(read_cache_variants_f, |
| SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); |
| |
| +/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */ |
| +static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants, |
| + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| + |
| static SPINAND_OP_VARIANTS(write_cache_variants, |
| SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| @@ -236,6 +245,16 @@ static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, |
| } |
| |
| static const struct spinand_info gigadevice_spinand_table[] = { |
| + SPINAND_INFO("F50L1G41LB", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), |
| + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + 0, |
| + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, |
| + gd5fxgq4xa_ecc_get_status)), |
| SPINAND_INFO("GD5F1GQ4xA", |
| SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), |
| NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| @@ -290,7 +309,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { |
| SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(4, 512), |
| - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| -- |
| 2.34.1 |
| |