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| From: <chuanjia.liu@mediatek.com> |
| To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com> |
| Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding |
| Date: Thu, 28 May 2020 14:16:45 +0800 |
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| |
| From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com> |
| |
| There are two independent PCIe controllers in MT2712/MT7622 platform, |
| and each of them should contain an independent MSI domain. |
| |
| In current architecture, MSI domain will be inherited from the root |
| bridge, and all of the devices will share the same MSI domain. |
| Hence that, the PCIe devices will not work properly if the irq number |
| which required is more than 32. |
| |
| Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and |
| comply with the hardware design. |
| |
| Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com> |
| --- |
| .../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++ |
| .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++------- |
| 2 files changed, 129 insertions(+), 53 deletions(-) |
| create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml |
| |
| --- /dev/null |
| +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml |
| @@ -0,0 +1,38 @@ |
| +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| +%YAML 1.2 |
| +--- |
| +$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml# |
| +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| + |
| +title: Mediatek PCIECFG controller |
| + |
| +maintainers: |
| + - Chuanjia Liu <chuanjia.liu@mediatek.com> |
| + - Jianjun Wang <jianjun.wang@mediatek.com> |
| + |
| +description: | |
| + The MediaTek PCIECFG controller controls some feature about |
| + LTSSM, ASPM and so on. |
| + |
| +properties: |
| + compatible: |
| + items: |
| + - enum: |
| + - mediatek,mt7622-pciecfg |
| + - mediatek,mt7629-pciecfg |
| + - const: syscon |
| + |
| + reg: |
| + maxItems: 1 |
| + |
| +required: |
| + - compatible |
| + - reg |
| + |
| +examples: |
| + - | |
| + pciecfg: pciecfg@1a140000 { |
| + compatible = "mediatek,mt7622-pciecfg", "syscon"; |
| + reg = <0 0x1a140000 0 0x1000>; |
| + }; |
| +... |
| --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt |
| +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt |
| @@ -8,7 +8,7 @@ Required properties: |
| "mediatek,mt7623-pcie" |
| "mediatek,mt7629-pcie" |
| - device_type: Must be "pci" |
| -- reg: Base addresses and lengths of the PCIe subsys and root ports. |
| +- reg: Base addresses and lengths of the root ports. |
| - reg-names: Names of the above areas to use during resource lookup. |
| - #address-cells: Address representation for root ports (must be 3) |
| - #size-cells: Size representation for root ports (must be 2) |
| @@ -19,10 +19,10 @@ Required properties: |
| - sys_ckN :transaction layer and data link layer clock |
| Required entries for MT2701/MT7623: |
| - free_ck :for reference clock of PCIe subsys |
| - Required entries for MT2712/MT7622: |
| + Required entries for MT2712/MT7622/MT7629: |
| - ahb_ckN :AHB slave interface operating clock for CSR access and RC |
| initiated MMIO access |
| - Required entries for MT7622: |
| + Required entries for MT7622/MT7629: |
| - axi_ckN :application layer MMIO channel operating clock |
| - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when |
| pcie_mac_ck/pcie_pipe_ck is turned off |
| @@ -47,10 +47,13 @@ Required properties for MT7623/MT2701: |
| - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the |
| number of root ports. |
| |
| -Required properties for MT2712/MT7622: |
| +Required properties for MT2712/MT7622/MT7629: |
| -interrupts: A list of interrupt outputs of the controller, must have one |
| entry for each PCIe port |
| |
| +Required properties for MT7622/MT7629: |
| +- mediatek,pcie-subsys: Should be a phandle of the pciecfg node. |
| + |
| In addition, the device tree node must have sub-nodes describing each |
| PCIe port interface, having the following mandatory properties: |
| |
| @@ -143,56 +146,73 @@ Examples for MT7623: |
| |
| Examples for MT2712: |
| |
| - pcie: pcie@11700000 { |
| + pcie1: pcie@112ff000 { |
| compatible = "mediatek,mt2712-pcie"; |
| device_type = "pci"; |
| - reg = <0 0x11700000 0 0x1000>, |
| - <0 0x112ff000 0 0x1000>; |
| - reg-names = "port0", "port1"; |
| + reg = <0 0x112ff000 0 0x1000>; |
| + reg-names = "port1"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, |
| - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, |
| - <&pericfg CLK_PERI_PCIE0>, |
| + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| + interrupt-names = "pcie_irq"; |
| + clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, |
| <&pericfg CLK_PERI_PCIE1>; |
| - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; |
| - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; |
| - phy-names = "pcie-phy0", "pcie-phy1"; |
| + clock-names = "sys_ck1", "ahb_ck1"; |
| + phys = <&u3port1 PHY_TYPE_PCIE>; |
| + phy-names = "pcie-phy1"; |
| bus-range = <0x00 0xff>; |
| - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; |
| + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; |
| + status = "disabled"; |
| |
| - pcie0: pcie@0,0 { |
| - reg = <0x0000 0 0 0 0>; |
| + slot1: pcie@1,0 { |
| + reg = <0x0800 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges; |
| interrupt-map-mask = <0 0 0 7>; |
| - interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| - <0 0 0 2 &pcie_intc0 1>, |
| - <0 0 0 3 &pcie_intc0 2>, |
| - <0 0 0 4 &pcie_intc0 3>; |
| - pcie_intc0: interrupt-controller { |
| + interrupt-map = <0 0 0 1 &pcie_intc1 0>, |
| + <0 0 0 2 &pcie_intc1 1>, |
| + <0 0 0 3 &pcie_intc1 2>, |
| + <0 0 0 4 &pcie_intc1 3>; |
| + pcie_intc1: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| + }; |
| |
| - pcie1: pcie@1,0 { |
| - reg = <0x0800 0 0 0 0>; |
| + pcie0: pcie@11700000 { |
| + compatible = "mediatek,mt2712-pcie"; |
| + device_type = "pci"; |
| + reg = <0 0x11700000 0 0x1000>; |
| + reg-names = "port0"; |
| + #address-cells = <3>; |
| + #size-cells = <2>; |
| + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| + interrupt-names = "pcie_irq"; |
| + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, |
| + <&pericfg CLK_PERI_PCIE0>; |
| + clock-names = "sys_ck0", "ahb_ck0"; |
| + phys = <&u3port0 PHY_TYPE_PCIE>; |
| + phy-names = "pcie-phy0"; |
| + bus-range = <0x00 0xff>; |
| + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; |
| + status = "disabled"; |
| + |
| + slot0: pcie@0,0 { |
| + reg = <0x0000 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges; |
| interrupt-map-mask = <0 0 0 7>; |
| - interrupt-map = <0 0 0 1 &pcie_intc1 0>, |
| - <0 0 0 2 &pcie_intc1 1>, |
| - <0 0 0 3 &pcie_intc1 2>, |
| - <0 0 0 4 &pcie_intc1 3>; |
| - pcie_intc1: interrupt-controller { |
| + interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| + <0 0 0 2 &pcie_intc0 1>, |
| + <0 0 0 3 &pcie_intc0 2>, |
| + <0 0 0 4 &pcie_intc0 3>; |
| + pcie_intc0: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| @@ -202,39 +222,31 @@ Examples for MT2712: |
| |
| Examples for MT7622: |
| |
| - pcie: pcie@1a140000 { |
| + pcie0: pcie@1a143000 { |
| compatible = "mediatek,mt7622-pcie"; |
| device_type = "pci"; |
| - reg = <0 0x1a140000 0 0x1000>, |
| - <0 0x1a143000 0 0x1000>, |
| - <0 0x1a145000 0 0x1000>; |
| - reg-names = "subsys", "port0", "port1"; |
| + reg = <0 0x1a143000 0 0x1000>; |
| + reg-names = "port0"; |
| + mediatek,pcie-cfg = <&pciecfg>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>, |
| - <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; |
| + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; |
| + interrupt-names = "pcie_irq"; |
| clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, |
| - <&pciesys CLK_PCIE_P1_MAC_EN>, |
| <&pciesys CLK_PCIE_P0_AHB_EN>, |
| - <&pciesys CLK_PCIE_P1_AHB_EN>, |
| <&pciesys CLK_PCIE_P0_AUX_EN>, |
| - <&pciesys CLK_PCIE_P1_AUX_EN>, |
| <&pciesys CLK_PCIE_P0_AXI_EN>, |
| - <&pciesys CLK_PCIE_P1_AXI_EN>, |
| <&pciesys CLK_PCIE_P0_OBFF_EN>, |
| - <&pciesys CLK_PCIE_P1_OBFF_EN>, |
| - <&pciesys CLK_PCIE_P0_PIPE_EN>, |
| - <&pciesys CLK_PCIE_P1_PIPE_EN>; |
| - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", |
| - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", |
| - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; |
| - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; |
| - phy-names = "pcie-phy0", "pcie-phy1"; |
| + <&pciesys CLK_PCIE_P0_PIPE_EN>; |
| + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", |
| + "axi_ck0", "obff_ck0", "pipe_ck0"; |
| + |
| power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; |
| bus-range = <0x00 0xff>; |
| - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; |
| + ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x8000000>; |
| + status = "disabled"; |
| |
| - pcie0: pcie@0,0 { |
| + slot0: pcie@0,0 { |
| reg = <0x0000 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| @@ -251,8 +263,34 @@ Examples for MT7622: |
| #interrupt-cells = <1>; |
| }; |
| }; |
| + }; |
| + |
| + pcie1: pcie@1a145000 { |
| + compatible = "mediatek,mt7622-pcie"; |
| + device_type = "pci"; |
| + reg = <0 0x1a145000 0 0x1000>; |
| + reg-names = "port1"; |
| + mediatek,pcie-cfg = <&pciecfg>; |
| + #address-cells = <3>; |
| + #size-cells = <2>; |
| + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; |
| + interrupt-names = "pcie_irq"; |
| + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, |
| + /* designer has connect RC1 with p0_ahb clock */ |
| + <&pciesys CLK_PCIE_P0_AHB_EN>, |
| + <&pciesys CLK_PCIE_P1_AUX_EN>, |
| + <&pciesys CLK_PCIE_P1_AXI_EN>, |
| + <&pciesys CLK_PCIE_P1_OBFF_EN>, |
| + <&pciesys CLK_PCIE_P1_PIPE_EN>; |
| + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", |
| + "axi_ck1", "obff_ck1", "pipe_ck1"; |
| + |
| + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; |
| + bus-range = <0x00 0xff>; |
| + ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>; |
| + status = "disabled"; |
| |
| - pcie1: pcie@1,0 { |
| + slot1: pcie@1,0 { |
| reg = <0x0800 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |