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| From: <chuanjia.liu@mediatek.com> |
| To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com> |
| Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node |
| Date: Thu, 28 May 2020 14:16:48 +0800 |
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| |
| From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com> |
| |
| Remove unused property and add pciecfg node. |
| |
| Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com> |
| --- |
| arch/arm/boot/dts/mt7629-rfb.dts | 3 ++- |
| arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++---------- |
| 2 files changed, 15 insertions(+), 11 deletions(-) |
| |
| --- a/arch/arm/boot/dts/mt7629-rfb.dts |
| +++ b/arch/arm/boot/dts/mt7629-rfb.dts |
| @@ -171,9 +171,10 @@ |
| }; |
| }; |
| |
| -&pcie { |
| +&pcie1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie_pins>; |
| + status = "okay"; |
| }; |
| |
| &pciephy1 { |
| --- a/arch/arm/boot/dts/mt7629.dtsi |
| +++ b/arch/arm/boot/dts/mt7629.dtsi |
| @@ -368,16 +368,21 @@ |
| #reset-cells = <1>; |
| }; |
| |
| - pcie: pcie@1a140000 { |
| + pciecfg: pciecfg@1a140000 { |
| + compatible = "mediatek,mt7629-pciecfg", "syscon"; |
| + reg = <0x1a140000 0x1000>; |
| + }; |
| + |
| + pcie1: pcie@1a145000 { |
| compatible = "mediatek,mt7629-pcie"; |
| device_type = "pci"; |
| - reg = <0x1a140000 0x1000>, |
| - <0x1a145000 0x1000>; |
| - reg-names = "subsys","port1"; |
| + reg = <0x1a145000 0x1000>; |
| + reg-names = "port1"; |
| + mediatek,pcie-cfg = <&pciecfg>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, |
| - <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; |
| + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; |
| + interrupt-names = "pcie_irq"; |
| clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, |
| <&pciesys CLK_PCIE_P0_AHB_EN>, |
| <&pciesys CLK_PCIE_P1_AUX_EN>, |
| @@ -398,21 +403,19 @@ |
| power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; |
| bus-range = <0x00 0xff>; |
| ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; |
| + status = "disabled"; |
| |
| - pcie1: pcie@1,0 { |
| - device_type = "pci"; |
| + slot1: pcie@1,0 { |
| reg = <0x0800 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges; |
| - num-lanes = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie_intc1 0>, |
| <0 0 0 2 &pcie_intc1 1>, |
| <0 0 0 3 &pcie_intc1 2>, |
| <0 0 0 4 &pcie_intc1 3>; |
| - |
| pcie_intc1: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |