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| From: <chuanjia.liu@mediatek.com> |
| To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com> |
| Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base |
| Date: Thu, 28 May 2020 14:16:46 +0800 |
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| srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>, |
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| |
| From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com> |
| |
| Use regmap to get shared pcie-cfg base and change |
| the method to get pcie irq. |
| |
| Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com> |
| --- |
| drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++------- |
| 1 file changed, 18 insertions(+), 7 deletions(-) |
| |
| --- a/drivers/pci/controller/pcie-mediatek.c |
| +++ b/drivers/pci/controller/pcie-mediatek.c |
| @@ -14,6 +14,7 @@ |
| #include <linux/irqchip/chained_irq.h> |
| #include <linux/irqdomain.h> |
| #include <linux/kernel.h> |
| +#include <linux/mfd/syscon.h> |
| #include <linux/msi.h> |
| #include <linux/module.h> |
| #include <linux/of_address.h> |
| @@ -23,6 +24,7 @@ |
| #include <linux/phy/phy.h> |
| #include <linux/platform_device.h> |
| #include <linux/pm_runtime.h> |
| +#include <linux/regmap.h> |
| #include <linux/reset.h> |
| |
| #include "../pci.h" |
| @@ -205,6 +207,7 @@ struct mtk_pcie_port { |
| * struct mtk_pcie - PCIe host information |
| * @dev: pointer to PCIe device |
| * @base: IO mapped register base |
| + * @cfg: IO mapped register map for PCIe config |
| * @free_ck: free-run reference clock |
| * @mem: non-prefetchable memory resource |
| * @ports: pointer to PCIe port information |
| @@ -214,6 +217,7 @@ struct mtk_pcie_port { |
| struct mtk_pcie { |
| struct device *dev; |
| void __iomem *base; |
| + struct regmap *cfg; |
| struct clk *free_ck; |
| |
| struct resource mem; |
| @@ -651,7 +655,7 @@ static int mtk_pcie_setup_irq(struct mtk |
| return err; |
| } |
| |
| - port->irq = platform_get_irq(pdev, port->slot); |
| + port->irq = platform_get_irq_byname(pdev, "pcie_irq"); |
| irq_set_chained_handler_and_data(port->irq, |
| mtk_pcie_intr_handler, port); |
| |
| @@ -666,12 +670,11 @@ static int mtk_pcie_startup_port_v2(stru |
| u32 val; |
| int err; |
| |
| - /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ |
| - if (pcie->base) { |
| - val = readl(pcie->base + PCIE_SYS_CFG_V2); |
| - val |= PCIE_CSR_LTSSM_EN(port->slot) | |
| - PCIE_CSR_ASPM_L1_EN(port->slot); |
| - writel(val, pcie->base + PCIE_SYS_CFG_V2); |
| + /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */ |
| + if (pcie->cfg) { |
| + val = PCIE_CSR_LTSSM_EN(port->slot) | |
| + PCIE_CSR_ASPM_L1_EN(port->slot); |
| + regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); |
| } |
| |
| /* Assert all reset signals */ |
| @@ -977,6 +980,7 @@ static int mtk_pcie_subsys_powerup(struc |
| struct device *dev = pcie->dev; |
| struct platform_device *pdev = to_platform_device(dev); |
| struct resource *regs; |
| + struct device_node *cfg_node; |
| int err; |
| |
| /* get shared registers, which are optional */ |
| @@ -989,6 +993,13 @@ static int mtk_pcie_subsys_powerup(struc |
| } |
| } |
| |
| + cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0); |
| + if (cfg_node) { |
| + pcie->cfg = syscon_node_to_regmap(cfg_node); |
| + if (IS_ERR(pcie->cfg)) |
| + return PTR_ERR(pcie->cfg); |
| + } |
| + |
| pcie->free_ck = devm_clk_get(dev, "free_ck"); |
| if (IS_ERR(pcie->free_ck)) { |
| if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) |