blob: 47b364d9c6ba2fa13b86362a3a6c162feaa508a8 [file] [log] [blame]
From c499d09d496d723dab109aee2e3af8a28278a54c Mon Sep 17 00:00:00 2001
From: "Allen.Ye" <allen.ye@mediatek.com>
Date: Fri, 11 Aug 2023 16:46:53 +0800
Subject: [PATCH 1036/1040] wifi: mt76: mt7915: Disable RegDB when enable
single sku
---
eeprom.c | 3 ++-
mt76.h | 3 +++
mt7915/debugfs.c | 49 +++++++++++++++++++++++++++++++++++++++++++-----
mt7915/init.c | 9 ++++++++-
mt7915/regs.h | 8 ++++----
5 files changed, 61 insertions(+), 11 deletions(-)
diff --git a/eeprom.c b/eeprom.c
index 4189525..38b0a58 100644
--- a/eeprom.c
+++ b/eeprom.c
@@ -216,7 +216,7 @@ static bool mt76_string_prop_find(struct property *prop, const char *str)
return false;
}
-static struct device_node *
+struct device_node *
mt76_find_power_limits_node(struct mt76_dev *dev)
{
struct device_node *np = dev->dev->of_node;
@@ -255,6 +255,7 @@ mt76_find_power_limits_node(struct mt76_dev *dev)
of_node_put(np);
return fallback;
}
+EXPORT_SYMBOL_GPL(mt76_find_power_limits_node);
static const __be32 *
mt76_get_of_array(struct device_node *np, char *name, size_t *len, int min)
diff --git a/mt76.h b/mt76.h
index 05c1874..91da8c5 100644
--- a/mt76.h
+++ b/mt76.h
@@ -1673,6 +1673,9 @@ mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
+struct device_node *
+mt76_find_power_limits_node(struct mt76_dev *dev);
+
s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
struct ieee80211_channel *chan,
struct mt76_power_limits *dest,
diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
index 2bf907c..6dcee10 100644
--- a/mt7915/debugfs.c
+++ b/mt7915/debugfs.c
@@ -1019,10 +1019,16 @@ mt7915_rate_txpower_get(struct file *file, char __user *user_buf,
{
struct mt7915_phy *phy = file->private_data;
struct mt7915_dev *dev = phy->dev;
+ struct ieee80211_channel *chan = phy->mt76->chandef.chan;
+ struct ieee80211_supported_band sband;
s8 txpwr[MT7915_SKU_RATE_NUM];
- static const size_t sz = 2048;
+ static const size_t sz = 4096;
u8 band = phy->mt76->band_idx;
int i, offs = 0, len = 0;
+ u32 target_power = 0;
+ int n_chains = hweight16(phy->mt76->chainmask);
+ int nss_delta = mt76_tx_power_nss_delta(n_chains);
+ int pwr_delta;
ssize_t ret;
char *buf;
u32 reg;
@@ -1081,11 +1087,38 @@ mt7915_rate_txpower_get(struct file *file, char __user *user_buf,
len += scnprintf(buf + len, sz - len, "BW160/");
mt7915_txpower_puts(HE_RU2x996, 17);
- reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_TPC_CTRL_STAT(band) :
- MT_WF_PHY_TPC_CTRL_STAT_MT7916(band);
+ reg = is_mt7915(&dev->mt76) ? MT_WF_IRPI_TPC_CTRL_STAT(band) :
+ MT_WF_IRPI_TPC_CTRL_STAT_MT7916(band);
- len += scnprintf(buf + len, sz - len, "\nTx power (bbp) : %6ld\n",
- mt76_get_field(dev, reg, MT_WF_PHY_TPC_POWER));
+ len += scnprintf(buf + len, sz - len, "\nTx power (bbp) : %6ld [0.5 dBm]\n",
+ mt76_get_field(dev, reg, MT_WF_IRPI_TPC_POWER));
+
+ len += scnprintf(buf + len, sz - len, "RegDB maximum power:\t%d [dBm]\n",
+ chan->max_reg_power);
+
+ if (chan->band == NL80211_BAND_2GHZ)
+ sband = phy->mt76->sband_2g.sband;
+ else if (chan->band == NL80211_BAND_5GHZ)
+ sband = phy->mt76->sband_5g.sband;
+ else if (chan->band == NL80211_BAND_6GHZ)
+ sband = phy->mt76->sband_6g.sband;
+
+ pwr_delta = mt7915_eeprom_get_power_delta(dev, sband.band);
+
+ for (i = 0; i < n_chains; i++) {
+ u32 val;
+
+ val = mt7915_eeprom_get_target_power(dev, chan, i);
+ target_power = max(target_power, val);
+ }
+
+ target_power += pwr_delta + nss_delta;
+ target_power = DIV_ROUND_UP(target_power, 2);
+ len += scnprintf(buf + len, sz - len, "eeprom maximum power:\t%d [dBm]\n",
+ target_power);
+
+ len += scnprintf(buf + len, sz - len, "nss_delta:\t%d [0.5 dBm]\n",
+ nss_delta);
ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
@@ -1262,6 +1295,8 @@ static int
mt7915_txpower_info_show(struct seq_file *file, void *data)
{
struct mt7915_phy *phy = file->private;
+ struct mt76_phy *mphy = phy->mt76;
+ struct mt76_dev *dev = mphy->dev;
struct {
u8 category;
u8 rsv1;
@@ -1303,6 +1338,7 @@ mt7915_txpower_info_show(struct seq_file *file, void *data)
s8 mu_tx_power_manual;
u8 rsv3;
} __packed basic_info = {};
+ struct device_node *np;
int ret;
ret = mt7915_mcu_get_txpower_sku(phy, (s8 *)&basic_info, sizeof(basic_info),
@@ -1337,6 +1373,9 @@ mt7915_txpower_info_show(struct seq_file *file, void *data)
seq_printf(file, " Theraml Compensation Value: %d\n",
basic_info.thermal_compensate_value);
+ np = mt76_find_power_limits_node(dev);
+ seq_printf(file, " RegDB: %s\n", !np ? "enable" : "disable");
+
out:
return ret;
}
diff --git a/mt7915/init.c b/mt7915/init.c
index a942bc2..82fe443 100644
--- a/mt7915/init.c
+++ b/mt7915/init.c
@@ -283,7 +283,9 @@ void __mt7915_init_txpower(struct mt7915_phy *phy,
int nss_delta = mt76_tx_power_nss_delta(n_chains);
int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band);
struct mt76_power_limits limits;
+ struct device_node *np;
+ np = mt76_find_power_limits_node(&dev->mt76);
for (i = 0; i < sband->n_channels; i++) {
struct ieee80211_channel *chan = &sband->channels[i];
u32 target_power = 0;
@@ -302,8 +304,13 @@ void __mt7915_init_txpower(struct mt7915_phy *phy,
target_power);
target_power += nss_delta;
target_power = DIV_ROUND_UP(target_power, 2);
- chan->max_power = min_t(int, chan->max_reg_power,
+
+ /* can NOT find country node in dts */
+ if (!np)
+ chan->max_power = min_t(int, chan->max_reg_power,
target_power);
+ else
+ chan->max_power = target_power;
chan->orig_mpwr = target_power;
}
}
diff --git a/mt7915/regs.h b/mt7915/regs.h
index 1f1f8b9..3c2fd2d 100644
--- a/mt7915/regs.h
+++ b/mt7915/regs.h
@@ -1213,6 +1213,10 @@ enum offs_rev {
#define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16))
#define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16))
+#define MT_WF_IRPI_TPC_CTRL_STAT(_phy) MT_WF_IRPI(0xc794 + ((_phy) << 16))
+#define MT_WF_IRPI_TPC_CTRL_STAT_MT7916(_phy) MT_WF_IRPI(0xc794 + ((_phy) << 20))
+#define MT_WF_IRPI_TPC_POWER GENMASK(31, 24)
+
#define MT_WF_IPI_RESET 0x831a3008
/* PHY */
@@ -1229,10 +1233,6 @@ enum offs_rev {
#define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18)
#define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29)
-#define MT_WF_PHY_TPC_CTRL_STAT(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 16))
-#define MT_WF_PHY_TPC_CTRL_STAT_MT7916(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 20))
-#define MT_WF_PHY_TPC_POWER GENMASK(15, 8)
-
#define MT_MCU_WM_CIRQ_BASE 0x89010000
#define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs))
#define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80)
--
2.18.0