| From 161fde22deceee4e676f62b9d3b0366ffe52dc07 Mon Sep 17 00:00:00 2001 |
| From: "sujuan.chen" <sujuan.chen@mediatek.com> |
| Date: Fri, 6 Oct 2023 14:01:41 +0800 |
| Subject: [PATCH 69/98] wifi: mt76 : wed : change pcie0 R5 to pcie1 to get 6G |
| ICS |
| |
| --- |
| mt7996/dma.c | 4 ++++ |
| mt7996/init.c | 6 ++---- |
| mt7996/mmio.c | 5 ++++- |
| mt7996/regs.h | 6 ++++++ |
| 4 files changed, 16 insertions(+), 5 deletions(-) |
| |
| diff --git a/mt7996/dma.c b/mt7996/dma.c |
| index 23f6f16..2397fe5 100644 |
| --- a/mt7996/dma.c |
| +++ b/mt7996/dma.c |
| @@ -519,6 +519,10 @@ int mt7996_dma_init(struct mt7996_dev *dev) |
| if (mt7996_band_valid(dev, MT_BAND2)) { |
| /* rx data queue for band2 */ |
| rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs; |
| + if (mtk_wed_device_active(wed_hif2) && mtk_wed_get_rx_capa(wed_hif2)) { |
| + dev->mt76.q_rx[MT_RXQ_BAND2].flags = MT_WED_Q_RX(0); |
| + dev->mt76.q_rx[MT_RXQ_BAND2].wed = wed_hif2; |
| + } |
| ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2], |
| MT_RXQ_ID(MT_RXQ_BAND2), |
| MT7996_RX_RING_SIZE, |
| diff --git a/mt7996/init.c b/mt7996/init.c |
| index 1f01f24..5627605 100644 |
| --- a/mt7996/init.c |
| +++ b/mt7996/init.c |
| @@ -619,10 +619,8 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, |
| goto error; |
| |
| if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { |
| - u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2; |
| - |
| - mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask); |
| - mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask); |
| + mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TRX_DONE_EXT); |
| + mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, MT_INT_TRX_DONE_EXT); |
| } |
| |
| return 0; |
| diff --git a/mt7996/mmio.c b/mt7996/mmio.c |
| index 2132b2e..2e395d1 100644 |
| --- a/mt7996/mmio.c |
| +++ b/mt7996/mmio.c |
| @@ -504,12 +504,15 @@ static void mt7996_irq_tasklet(struct tasklet_struct *t) |
| dev->mt76.mmio.irqmask); |
| if (intr1 & MT_INT_RX_TXFREE_EXT) |
| napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]); |
| + |
| + if (intr1 & MT_INT_RX_DONE_BAND2_EXT) |
| + napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]); |
| } |
| |
| if (mtk_wed_device_active(wed)) { |
| mtk_wed_device_irq_set_mask(wed, 0); |
| intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); |
| - intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT); |
| + intr |= (intr1 & ~MT_INT_TRX_DONE_EXT); |
| } else { |
| mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| if (dev->hif2) |
| diff --git a/mt7996/regs.h b/mt7996/regs.h |
| index 38467d9..a0b5270 100644 |
| --- a/mt7996/regs.h |
| +++ b/mt7996/regs.h |
| @@ -501,6 +501,8 @@ enum offs_rev { |
| #define MT_INT_RX_TXFREE_MAIN BIT(17) |
| #define MT_INT_RX_TXFREE_TRI BIT(15) |
| #define MT_INT_MCU_CMD BIT(29) |
| + |
| +#define MT_INT_RX_DONE_BAND2_EXT BIT(23) |
| #define MT_INT_RX_TXFREE_EXT BIT(26) |
| |
| #define MT_INT_RX_DONE_RRO_BAND0 BIT(16) |
| @@ -551,6 +553,10 @@ enum offs_rev { |
| #define MT_INT_TX_DONE_BAND1 BIT(31) |
| #define MT_INT_TX_DONE_BAND2 BIT(15) |
| |
| +#define MT_INT_TRX_DONE_EXT (MT_INT_TX_DONE_BAND2 | \ |
| + MT_INT_RX_DONE_BAND2_EXT | \ |
| + MT_INT_RX_TXFREE_EXT) |
| + |
| #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ |
| MT_INT_TX_MCU(MT_MCUQ_WM) | \ |
| MT_INT_TX_MCU(MT_MCUQ_FWDL)) |
| -- |
| 2.18.0 |
| |