- 71af7f1 feat(spmd): initialize SCR_EL3.EEL2 bit at RESET by Manish Pandey · 4 months ago
- 514a301 fix(ras): restrict ENABLE_FEAT_RAS to have only two states by Manish Pandey · 8 months ago
- 6b5721f feat(ras): use FEAT_IESB for error synchronization by Manish Pandey · 11 months ago
- 4fc00d2 refactor(cm): move EL3 registers to global context by Elizabeth Ho · 11 months ago
- 2e9e6f0 refactor(cm): remove world differentiation for EL2 context restore by Boyan Karatotev · 1 year ago
- 8ae58f0 refactor(cm): clean up SCR_EL3 and CPTR_EL3 initialization by Boyan Karatotev · 1 year, 1 month ago
- 919d3c8 refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only by Boyan Karatotev · 1 year, 4 months ago
- 677ed8a refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init by Boyan Karatotev · 1 year, 4 months ago
- 05504ba feat(pmu): introduce pmuv3 lib/extensions folder by Boyan Karatotev · 1 year, 4 months ago
- 1f55c41 refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED by Andre Przywara · 1 year, 4 months ago
- 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 1 year, 6 months ago
- 259b6d0 Merge changes from topic "panic_cleanup" into integration by Bipin Ravi · 1 year, 3 months ago
- a796b1b refactor(aarch64): rename do_panic and el3_panic by Govindraj Raja · 1 year, 5 months ago
- 66a056e refactor(el3_runtime): introduce save_x30 macro by Manish Pandey · 1 year, 5 months ago
- 0824b45 feat(bl2): add support to separate no-loadable sections by Jiafei Pan · 2 years, 3 months ago
- 928747f fix(el3-runtime): set unset pstate bits to default by Daniel Boulby · 3 years ago
- 9baade3 feat(sme): enable SME functionality by johpow01 · 2 years, 11 months ago
- b0d69e8 fix(pie): invalidate data cache in the entire image range if PIE is enabled by Zelalem Aweke · 2 years, 8 months ago
- 688fbf7 feat(rme): run BL2 in root world when FEAT_RME is enabled by Zelalem Aweke · 2 years, 11 months ago
- 8ce3394 feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · 2 years, 11 months ago
- f7ee064 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · 2 years, 11 months ago
- e1cccb4 feat(trbe): initialize trap settings of trace buffer control registers access by Manish V Badarkhe · 3 years ago
- c450277 feat(sve): enable SVE for the secure world by Max Shvetsov · 3 years, 2 months ago
- 307f34b fix(security): Set MDCR_EL3.MCCD bit by Alexei Fedorov · 3 years, 1 month ago
- f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · 3 years, 6 months ago
- ed20207 Increase type widths to satisfy width requirements by Jimmy Brisson · 3 years, 10 months ago
- e07e808 runtime_exceptions: Update AT speculative workaround by Manish V Badarkhe · 3 years, 11 months ago
- 5dc9e9c Fix compilation error when ENABLE_PIE=1 by Varun Wadekar · 4 years, 1 month ago
- 31a14e1 bl31: Split into two separate memory regions by Samuel Holland · 6 years ago
- c825768 PIE: make call to GDT relocation fixup generalized by Manish Pandey · 4 years, 6 months ago
- add24a4 Explicitly disable the SPME bit in MDCR_EL3 by Petre-Ionut Tudor · 4 years, 8 months ago
- d2f21b8 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · 5 years ago
- 461f8f4 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · 4 years, 10 months ago
- 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · 4 years, 10 months ago
- 594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · 5 years ago
- 3fbd3f5 Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 5 years ago
- 8d1ade6 Reorganize architecture-dependent header files by Antonio Nino Diaz · 5 years ago[Renamed from include/common/aarch64/el3_common_macros.S]
- 0f3a004 Merge pull request #1731 from miyatsu/doc-fix-20181225 by Antonio Niño Díaz · 5 years ago