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git01.mediatek.com / filogic / atf / fc0b8679efd0c90b804bf9fc91376008ff9146d7 / include / lib / el3_runtime
  1. f92c0cb refactor(context mgmt): add cm_prepare_el3_exit_ns function by Zelalem Aweke · Mon Jan 31 16:59:42 2022 -0600
  2. bd17eae refactor(context mgmt): remove registers accessible only from secure state from EL2 context by Zelalem Aweke · Wed Nov 03 13:31:53 2021 -0500
  3. 72b69b8 refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags by Jayanth Dodderi Chidanand · Wed Jan 26 17:14:43 2022 +0000
  4. 13ae0f4 fix(amu): fault handling on EL2 context switch by Jayanth Dodderi Chidanand · Thu Nov 25 14:59:30 2021 +0000
  5. b6301e6 feat(rme): add context management changes for FEAT_RME by Zelalem Aweke · Fri Jul 09 17:54:30 2021 -0500
  6. f91e59f feat(hcx): add build option to enable FEAT_HCX by johpow01 · Wed Aug 04 19:38:18 2021 -0500
  7. f57491e fix(el3_runtime): correct CASSERT for pauth by Olivier Deprez · Thu Aug 19 11:36:26 2021 +0200
  8. c450277 feat(sve): enable SVE for the secure world by Max Shvetsov · Mon Mar 22 11:59:37 2021 +0000
  9. cf784f7 Fix: Remove save/restore of EL2 timer registers by Max Shvetsov · Wed Mar 31 19:00:38 2021 +0100
  10. fba2572 Fix exception handlers in BL31: Use DSB to synchronize pending EA by Madhukar Pappireddy · Fri Jul 24 03:27:12 2020 -0500
  11. 2b0ee97 el3_runtime: Rearrange context offset of EL1 sys registers by Manish V Badarkhe · Tue Jul 28 07:22:30 2020 +0100
  12. 0c16abd Fix exception in save/restore of EL2 registers. by Max Shvetsov · Wed May 13 18:15:39 2020 +0100
  13. d102752 include: fixup 'cm_setup_context' prototype by Varun Wadekar · Wed Apr 01 09:55:49 2020 -0700
  14. 1962891 context: TPIDR_EL2 register not saved/restored by Olivier Deprez · Fri Mar 20 14:22:05 2020 +0100
  15. c9e2c92 SPMD: Adds partially supported EL2 registers. by Max Shvetsov · Mon Feb 17 16:15:47 2020 +0000
  16. bdf502d SPMD: save/restore EL2 system registers. by Max Shvetsov · Tue Feb 25 13:56:19 2020 +0000
  17. 91d8061 coverity: fix MISRA violations by Zelalem · Wed Feb 12 10:37:03 2020 -0600
  18. 1c819c3 Use correct type when reading SCR register by Louis Mayencourt · Fri Jan 24 13:30:28 2020 +0000
  19. f41355c Refactor ARMv8.3 Pointer Authentication support code by Alexei Fedorov · Fri Sep 13 14:11:59 2019 +0100
  20. 1c7c13a Enable MTE support in both secure and non-secure worlds by Justin Chadwell · Thu Jul 18 14:25:33 2019 +0100
  21. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 13 15:17:53 2019 +0100
  22. 8e0ef0f Switch AARCH32/AARCH64 to __aarch64__ by Julius Werner · Tue Jul 09 14:02:43 2019 -0700
  23. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
  24. fb6f2fc Merge pull request #1751 from vwadekar/tegra-scatter-file-support by Antonio Niño Díaz · Fri Mar 01 11:23:58 2019 +0000
  25. 56b68ad Minor changes to documentation and comments by Antonio Nino Diaz · Thu Feb 28 13:35:21 2019 +0000
  26. 4d034c5 Tegra: Support for scatterfile for the BL31 image by Varun Wadekar · Fri Jan 11 14:47:48 2019 -0800
  27. 594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · Thu Jan 31 11:58:00 2019 +0000
  28. 13adfb1 Cleanup context handling library by Antonio Nino Diaz · Wed Jan 30 20:41:31 2019 +0000
  29. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  30. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  31. 864ca6f context_mgmt: Fix MISRA defects by Antonio Nino Diaz · Wed Oct 31 15:25:35 2018 +0000
  32. 9fe40fd Fix MISRA defects in workaround and errata framework by Antonio Nino Diaz · Thu Oct 25 17:11:02 2018 +0100
  33. b4dee44 context_mgmt: Remove deprecated interfaces by Antonio Nino Diaz · Mon Sep 24 17:27:55 2018 +0100
  34. 32ceef5 SDEI: MISRA fixes by Jeenu Viswambharan · Thu Aug 02 10:14:12 2018 +0100
  35. bb1fd5b SDEI: Ensure SDEI handler executes with CVE-2018-3639 mitigation enabled by Dimitris Papastamos · Thu Jun 07 11:29:15 2018 +0100
  36. fe5c421 Merge pull request #1392 from dp-arm/dp/cve_2018_3639 by Dimitris Papastamos · Tue May 29 09:28:05 2018 +0100
  37. 28dce9e context_mgmt: Make cm_init_context_common public by Antonio Nino Diaz · Tue May 22 10:09:10 2018 +0100
  38. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
  39. 96c7df0 AArch64: Introduce External Abort handling by Jeenu Viswambharan · Thu Nov 30 12:54:15 2017 +0000
  40. 0571270 Fix MISRA rule 8.4 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  41. b63c6f1 Optimize/cleanup BPIALL workaround by Dimitris Papastamos · Thu Jan 11 15:29:36 2018 +0000
  42. fa2b736 Merge pull request #1197 from dp-arm/dp/amu by davidcunado-arm · Fri Jan 12 09:02:24 2018 +0000
  43. d1a1841 Add PubSub events for CPU powerdown/powerup by Dimitris Papastamos · Tue Nov 28 15:16:00 2017 +0000
  44. c52ebdc Workaround for CVE-2017-5715 on Cortex A73 and A75 by Dimitris Papastamos · Mon Dec 18 13:46:21 2017 +0000
  45. 5bdbb47 Refactor Statistical Profiling Extensions implementation by Dimitris Papastamos · Fri Oct 13 12:06:06 2017 +0100
  46. d1a1fd4 Move FPEXC32_EL2 to FP Context by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  47. 10a6727 BL31: Introduce Exception Handling Framework by Jeenu Viswambharan · Fri Sep 22 08:32:10 2017 +0100
  48. 31ea969 Merge pull request #1151 from JoelHutton/jh/MISRA-Mandatory by davidcunado-arm · Fri Nov 03 20:59:57 2017 +0000
  49. 43a4d57 Change sizeof to use type of struct not function by Joel Hutton · Fri Oct 20 10:31:14 2017 +0100
  50. a7921b9 aarch64: Add PubSub events to capture security state transitions by Dimitris Papastamos · Fri Oct 13 15:27:58 2017 +0100
  51. 55e56a9 PSCI: Publish CPU ON event by Jeenu Viswambharan · Fri Sep 22 08:32:10 2017 +0100
  52. e3f2200 BL31: Introduce Publish and Subscribe framework by Jeenu Viswambharan · Fri Sep 22 08:32:10 2017 +0100
  53. 4168f2f Init and save / restore of PMCR_EL0 / PMCR by David Cunado · Mon Oct 02 17:41:39 2017 +0100
  54. 97ad6ce cpu log buffer size depends on cache line size by Etienne Carriere · Fri Sep 01 10:22:20 2017 +0200
  55. 09bb548 Merge pull request #978 from etienne-lms/minor-build by danh-arm · Wed Jun 28 13:46:19 2017 +0100
  56. 662bf93 context_mgmt: declare extern cm_set_next_context() for AArch32 by Etienne Carriere · Fri Jun 23 09:37:49 2017 +0200
  57. ee3457b aarch64: Enable Statistical Profiling Extensions for lower ELs by dp-arm · Tue May 23 09:32:49 2017 +0100
  58. c6a11f6 include: add U()/ULL() macros for constants by Varun Wadekar · Thu May 25 18:04:48 2017 -0700
  59. 6715485 Merge pull request #927 from jeenu-arm/state-switch by davidcunado-arm · Thu May 11 16:04:52 2017 +0100
  60. bc1a929 Introduce ARM SiP service to switch execution state by Jeenu Viswambharan · Thu Feb 16 14:55:15 2017 +0000
  61. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  62. 3759e3f Control inclusion of helper code used for asserts by Antonio Nino Diaz · Wed Mar 22 15:48:51 2017 +0000
  63. b911cc7 Re-factor header files for easier PSCI library integration by Soby Mathew · Mon Feb 13 12:46:28 2017 +0000
  64. 3cac786 Add PMF instrumentation points in TF by dp-arm · Mon Sep 19 11:18:44 2016 +0100
  65. 5d36121 AArch32: Add generic changes in BL1 by Yatharth Kochar · Tue Jun 28 17:07:09 2016 +0100
  66. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100
  67. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000