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git01.mediatek.com / filogic / atf / f32d2ad78e7125ade2b00c6730d1e63a950c0c98 / plat / intel / soc / n5x / include
  1. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 1 year, 11 months ago
  2. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years, 5 months ago
  3. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 2 years, 6 months ago
  4. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 7 months ago
  5. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 2 years, 6 months ago
  6. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 2 years, 9 months ago
  7. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 8 months ago