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git01.mediatek.com / filogic / atf / f270d6bfaecd1c576be2852cd95ac60fea3cf55f / plat / nvidia / tegra / common / tegra_sip_calls.c
  1. e0f3dfd Tegra: SiP: 64-bit address for Video Memory base by Harvey Hsieh · Tue Oct 11 18:59:52 2016 +0800
  2. dc79930 Tegra: implement FIQ interrupt handler by Varun Wadekar · Mon Dec 28 16:36:42 2015 -0800
  3. 2330edd Tegra: allow SiP smc calls from Secure World by Wayne Lin · Thu Mar 31 13:49:09 2016 -0700
  4. 923d04a Tegra: handlers for common and SoC-specific SiP calls by Varun Wadekar · Wed Dec 09 18:18:53 2015 -0800[Renamed (82%) from plat/nvidia/tegra/soc/t210/plat_sip_calls.c]
  5. 3acb2b0 Merge pull request #845 from vwadekar/tegra-changes-from-downstream-v1 by davidcunado-arm · Thu Feb 23 17:30:54 2017 +0000