Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / d30211ce384f841d446926ff5dd3bef6a6822296 / lib / cpus
  1. 268e699 Merge pull request #1388 from vwadekar/report-cve-2017-5715 by Dimitris Papastamos · Mon Aug 20 14:57:39 2018 +0100
  2. bc242fa cpus: denver: report CVE_2017_5715 mitigation to higher layers by Varun Wadekar · Fri Jul 06 13:39:52 2018 -0700
  3. 4daa1de DSU erratum 936184 workaround by John Tsichritzis · Mon Jul 23 09:11:59 2018 +0100
  4. a7c4687 Add initial CPU support for Cortex-Helios by Joel Hutton · Wed Jan 10 16:06:07 2018 +0000
  5. 9463cae Add initial CPU support for Cortex-Deimos by Joel Hutton · Fri May 04 15:09:47 2018 +0100
  6. 95f30ab Add end_vector_entry assembler macro by Roberto Vargas · Tue Apr 17 11:31:43 2018 +0100
  7. bb0aa39 cpulib: Add ISBs or comment why they are unneeded by Dimitris Papastamos · Thu Jun 07 13:20:19 2018 +0100
  8. 14f7005 Fix MISRA Rule 5.7 Part 1 by Daniel Boulby · Thu May 03 10:59:09 2018 +0100
  9. 8c18f6a Merge pull request #1397 from dp-arm/dp/cortex-a76 by Dimitris Papastamos · Fri Jun 08 14:01:38 2018 +0100
  10. 312e17e Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76 by Dimitris Papastamos · Wed May 16 09:59:54 2018 +0100
  11. 7ca21db Implement Cortex-Ares 1043202 erratum workaround by Dimitris Papastamos · Mon Mar 26 16:46:01 2018 +0100
  12. 89736dd Add AMU support for Cortex-Ares by Dimitris Papastamos · Tue Feb 13 11:28:02 2018 +0000
  13. ea84d6b Add support for Cortex-Ares and Cortex-A76 CPUs by Isla Mitchell · Thu Aug 03 16:04:46 2017 +0100
  14. 6694633 Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32 by Dimitris Papastamos · Thu May 31 11:38:33 2018 +0100
  15. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
  16. 4a284a4 aarch32: Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu May 17 14:41:13 2018 +0100
  17. e6625ec Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu Apr 05 14:38:26 2018 +0100
  18. 570c06a Rename symbols and files relating to CVE-2017-5715 by Dimitris Papastamos · Fri Apr 06 15:29:34 2018 +0100
  19. e34bd09 Workaround for CVE-2017-5715 on NVIDIA Denver CPUs by Varun Wadekar · Wed Jan 10 17:03:22 2018 -0800
  20. 6e1796e Check presence of fix for errata 835769 in Cortex-A53 by Jonathan Wright · Wed Mar 28 16:55:54 2018 +0100
  21. efb1f33 Check presence of fix for errata 843419 in Cortex-A53 by Jonathan Wright · Wed Mar 28 15:52:03 2018 +0100
  22. 914757c Fixup `SMCCC_ARCH_FEATURES` semantics by Dimitris Papastamos · Mon Mar 12 14:47:09 2018 +0000
  23. 780cc95 Use PFR0 to identify need for mitigation of CVE-2017-5715 by Dimitris Papastamos · Mon Mar 12 13:27:02 2018 +0000
  24. 864364a MISRA fixes for Cortex A75 AMU implementation by Dimitris Papastamos · Tue Feb 27 10:55:39 2018 +0000
  25. 1be747f Refactor AMU support for Cortex A75 by Dimitris Papastamos · Wed Feb 14 10:28:36 2018 +0000
  26. 0b00f8a Factor out CPU AMU helpers by Dimitris Papastamos · Wed Feb 14 10:00:06 2018 +0000
  27. d1e1930 Fixup AArch32 errata printing framework by Soby Mathew · Wed Feb 21 15:48:03 2018 +0000
  28. 8ca3144 Merge pull request #1253 from dp-arm/dp/amu32 by davidcunado-arm · Fri Feb 02 11:14:17 2018 +0000
  29. 0dcdd8d AMU: Implement context save/restore for aarch32 by Joel Hutton · Thu Dec 21 15:21:20 2017 +0000
  30. 2880363 Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75 by Dimitris Papastamos · Mon Jan 08 13:57:39 2018 +0000
  31. b63c6f1 Optimize/cleanup BPIALL workaround by Dimitris Papastamos · Thu Jan 11 15:29:36 2018 +0000
  32. 04285cf Merge pull request #1228 from dp-arm/dp/cve_2017_5715 by davidcunado-arm · Thu Jan 25 00:06:50 2018 +0000
  33. 471fb9b Merge pull request #1229 from manojkumar-arm/manojkumar-arm/ca72-aarch32-reset-fix by davidcunado-arm · Sat Jan 20 17:04:49 2018 +0000
  34. b5d1f8e Merge pull request #1200 from robertovargas-arm/bl2-el3 by davidcunado-arm · Fri Jan 19 13:40:12 2018 +0000
  35. e37c029 lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode by Manoj Kumar · Fri Jan 19 17:51:31 2018 +0530
  36. 8ca0af2 Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 by Dimitris Papastamos · Wed Jan 03 10:48:59 2018 +0000
  37. 858bd61 Print erratum application report for CVE-2017-5715 by Dimitris Papastamos · Tue Jan 16 10:32:47 2018 +0000
  38. 84e02dc Change the default errata format string by Dimitris Papastamos · Tue Jan 16 10:42:20 2018 +0000
  39. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  40. fa2b736 Merge pull request #1197 from dp-arm/dp/amu by davidcunado-arm · Fri Jan 12 09:02:24 2018 +0000
  41. d7e2e9e Add hooks to save/restore AMU context for Cortex A75 by Dimitris Papastamos · Mon Dec 11 11:45:35 2017 +0000
  42. 43e05ec Use PFR0 to identify need for mitigation of CVE-2017-5915 by Dimitris Papastamos · Tue Jan 02 15:53:01 2018 +0000
  43. c52ebdc Workaround for CVE-2017-5715 on Cortex A73 and A75 by Dimitris Papastamos · Mon Dec 18 13:46:21 2017 +0000
  44. 446f7f1 Workaround for CVE-2017-5715 on Cortex A57 and A72 by Dimitris Papastamos · Thu Nov 30 14:53:53 2017 +0000
  45. 4c24bb7 Merge pull request #1168 from matt2048/master by davidcunado-arm · Mon Dec 04 22:39:40 2017 +0000
  46. fcedb69 Implement support for the Activity Monitor Unit on Cortex A75 by Dimitris Papastamos · Mon Oct 16 11:40:10 2017 +0100
  47. 41b0094 Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS by Matt Ma · Wed Nov 22 19:31:28 2017 +0800
  48. 09d26a6 ARMv7: introduce Cortex-A12 by Etienne Carriere · Sun Nov 05 22:56:50 2017 +0100
  49. 010dd1f ARMv7: introduce Cortex-A17 by Etienne Carriere · Sun Nov 05 22:56:41 2017 +0100
  50. f2f7b91 ARMv7: introduce Cortex-A7 by Etienne Carriere · Sun Nov 05 22:56:34 2017 +0100
  51. 37f8cdc ARMv7: introduce Cortex-A5 by Etienne Carriere · Sun Nov 05 22:56:26 2017 +0100
  52. a1249e0 ARMv7: introduce Cortex-A9 by Etienne Carriere · Sun Nov 05 22:56:19 2017 +0100
  53. 4ece755 ARMv7: introduce Cortex-A15 by Etienne Carriere · Sun Nov 05 22:56:10 2017 +0100
  54. c3b4ca1 Cortex-A72: Implement workaround for erratum 859971 by Eleanor Bonnici · Wed Aug 02 18:33:41 2017 +0100
  55. 0c9bd27 Cortex-A57: Implement workaround for erratum 859972 by Eleanor Bonnici · Wed Aug 02 16:35:04 2017 +0100
  56. 41b61be CPU: Correct names of implementation-defined aux regs by Eleanor Bonnici · Wed Aug 09 16:42:40 2017 +0100
  57. 9930501 Fix order of #includes by Isla Mitchell · Tue Jul 11 14:54:08 2017 +0100
  58. d0c8273 Introduce TF_LDFLAGS by Douglas Raillard · Thu Jun 22 14:44:48 2017 +0100
  59. 505f467 Merge pull request #1002 from douglas-raillard-arm/dr/fix_errata_a53 by danh-arm · Wed Jun 28 13:47:40 2017 +0100
  60. 8a354f1 Resolve signed-unsigned comparison issues by David Cunado · Wed Jun 21 16:52:45 2017 +0100
  61. d56fb04 Apply workarounds for A53 Cat A Errata 835769 and 843419 by Douglas Raillard · Mon Jun 19 15:38:02 2017 +0100
  62. 2b40ca6 aarch32: Implement errata workarounds for Cortex A57 by Dimitris Papastamos · Mon Jun 05 14:55:41 2017 +0100
  63. 9c47a5a aarch32: Implement errata workarounds for Cortex A53 by Dimitris Papastamos · Mon Jun 05 13:37:25 2017 +0100
  64. 370542e aarch32: Implement cpu_rev_var_hs() by Dimitris Papastamos · Mon Jun 05 13:36:34 2017 +0100
  65. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · Mon Jun 05 14:54:46 2017 -0700
  66. 66231d1 Tegra: enable 'signed-comparison' compilation warning/errors by Varun Wadekar · Wed Jun 07 09:57:42 2017 -0700
  67. 805c2c7 Add support for Cortex-A75 and Cortex-A55 CPUs by David Wang · Wed Nov 09 16:29:02 2016 +0000
  68. 815faa8 Use a callee-saved register to be AAPCS-compliant by dp-arm · Fri May 05 12:21:03 2017 +0100
  69. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  70. bf360df Merge pull request #910 from dp-arm/dp/AArch32-juno-port by davidcunado-arm · Fri Apr 21 17:10:27 2017 +0100
  71. a9f776c AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor by Yatharth Kochar · Thu Nov 10 16:17:51 2016 +0000
  72. 7c65c1e Remove build option `ASM_ASSERTION` by Antonio Nino Diaz · Thu Apr 20 09:58:28 2017 +0100
  73. 8cbdab2 Merge pull request #870 from douglas-raillard-arm/dr/remove_asm_signed_test by davidcunado-arm · Wed Mar 29 09:58:20 2017 +0100
  74. 00eefd9 Add workaround for ARM Cortex-A53 erratum 855873 by Andre Przywara · Thu Oct 06 16:54:53 2016 +0100
  75. 9d92e8c Replace ASM signed tests with unsigned by Douglas Raillard · Tue Mar 07 16:36:14 2017 +0000
  76. c4364f6 Merge pull request #856 from antonio-nino-diaz-arm/an/dynamic-xlat by davidcunado-arm · Thu Mar 16 12:42:32 2017 +0000
  77. 3f13c35 Apply workaround for errata 813419 of Cortex-A57 by Antonio Nino Diaz · Fri Feb 24 11:39:22 2017 +0000
  78. 0a7e27c Merge pull request #853 from vwadekar/tegra-changes-from-downstream-v3 by davidcunado-arm · Thu Mar 02 15:27:33 2017 +0000
  79. 8f87cc3 cpus: denver: remove barrier from denver_enable_dco() by Varun Wadekar · Fri May 06 16:35:30 2016 -0700
  80. 1cc176b Merge pull request #848 from douglas-raillard-arm/dr/improve_errata_doc by danh-arm · Tue Feb 28 12:07:32 2017 +0000
  81. d43583c cpus: denver: disable DCO operations from platform code by Varun Wadekar · Mon Feb 22 11:09:41 2016 -0800
  82. c847f66 Clarify errata ERRATA_A53_836870 documentation by Douglas Raillard · Wed Feb 15 17:38:43 2017 +0000
  83. 3c337a6 cpus: Add support for all Denver variants by Varun Wadekar · Thu Sep 03 17:15:06 2015 +0530
  84. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · Tue Jan 03 11:01:51 2017 +0000
  85. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  86. 1f5f812 Correct system include order by David Cunado · Tue Jan 17 14:40:15 2017 +0000
  87. ee5eb80 Add provision to extend CPU operations at more levels by Jeenu Viswambharan · Fri Nov 18 12:58:28 2016 +0000
  88. adb7027 AArch32: Fix the stack alignment issue by Soby Mathew · Tue Dec 06 12:10:51 2016 +0000
  89. a4c219a AArch32: Add support for ARM Cortex-A32 MPCore Processor by Yatharth Kochar · Tue Jul 12 15:47:03 2016 +0100
  90. f528faf AArch32: Common changes needed for BL1/BL2 by Yatharth Kochar · Tue Jun 28 16:58:26 2016 +0100
  91. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100
  92. 6a72a91 bl31: Add error reporting registers by Naga Sureshkumar Relli · Fri Jul 01 12:52:41 2016 +0530
  93. 63af687 Add support for ARM Cortex-A73 MPCore Processor by Yatharth Kochar · Tue Feb 09 12:00:03 2016 +0000
  94. 143ef1a Add support for Cortex-A57 erratum 833471 workaround by Sandrine Bailleux · Thu Apr 21 11:10:52 2016 +0100
  95. adcbd55 Add support for Cortex-A57 erratum 826977 workaround by Sandrine Bailleux · Thu Apr 14 14:24:13 2016 +0100
  96. 48cbe85 Add support for Cortex-A57 erratum 829520 workaround by Sandrine Bailleux · Thu Apr 14 14:18:07 2016 +0100
  97. c11116f Add support for Cortex-A57 erratum 828024 workaround by Sandrine Bailleux · Thu Apr 14 14:04:48 2016 +0100
  98. a7e0c53 Add support for Cortex-A57 erratum 826974 workaround by Sandrine Bailleux · Thu Apr 14 13:32:31 2016 +0100
  99. afa8a78 Fix wording in cpu-ops.mk comments by Sandrine Bailleux · Thu Apr 14 12:59:42 2016 +0100
  100. 6b28c57 Make cpu operations warning a VERBOSE print by Soby Mathew · Mon Mar 21 10:36:47 2016 +0000