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git01.mediatek.com / filogic / atf / cc28b9da6904ee1ef577e8d172d4b656146ed53d / include / arch / aarch64 / el3_common_macros.S
  1. c450277 feat(sve): enable SVE for the secure world by Max Shvetsov · 3 years, 8 months ago
  2. 307f34b fix(security): Set MDCR_EL3.MCCD bit by Alexei Fedorov · 3 years, 6 months ago
  3. f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · 4 years ago
  4. ed20207 Increase type widths to satisfy width requirements by Jimmy Brisson · 4 years, 3 months ago
  5. e07e808 runtime_exceptions: Update AT speculative workaround by Manish V Badarkhe · 4 years, 4 months ago
  6. 5dc9e9c Fix compilation error when ENABLE_PIE=1 by Varun Wadekar · 4 years, 6 months ago
  7. 31a14e1 bl31: Split into two separate memory regions by Samuel Holland · 6 years ago
  8. c825768 PIE: make call to GDT relocation fixup generalized by Manish Pandey · 5 years ago
  9. add24a4 Explicitly disable the SPME bit in MDCR_EL3 by Petre-Ionut Tudor · 5 years ago
  10. d2f21b8 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · 5 years ago
  11. 461f8f4 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · 5 years ago
  12. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · 5 years ago
  13. 594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · 6 years ago
  14. 3fbd3f5 Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 6 years ago
  15. 8d1ade6 Reorganize architecture-dependent header files by Antonio Nino Diaz · 6 years ago[Renamed from include/common/aarch64/el3_common_macros.S]
  16. 0f3a004 Merge pull request #1731 from miyatsu/doc-fix-20181225 by Antonio Niño Díaz · 6 years ago