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git01.mediatek.com / filogic / atf / c7a7cc34bc39abff227ebeed012a83f118d2fe1f / bl31 / aarch64
  1. c7a7cc3 Merge "AArch64: Disable Secure Cycle Counter" into integration by Paul Beesley · 5 years ago
  2. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · 5 years ago
  3. c4dfb3b AArch64: Align crash reporting output by Alexei Fedorov · 5 years ago
  4. b5b903c Fix BL31 crash reporting on AArch64 only machines by Imre Kis · 5 years ago
  5. 90f2e88 Add support for Branch Target Identification by Alexei Fedorov · 5 years ago
  6. d87233a Rework smc_unknown return code path in smc_handler by Madhukar Pappireddy · 6 years ago
  7. dd894cc Fix restoration of PAuth context by Alexei Fedorov · 6 years ago
  8. 81de7ab PIE: Fix reloc at the beginning of bl31 entrypoint by Louis Mayencourt · 6 years ago
  9. 3287c4f Restore PAuth context in case of unknown SMC call by Alexei Fedorov · 6 years ago
  10. e71d26c BL31: Enable pointer authentication support in warm boot path by Alexei Fedorov · 6 years ago
  11. 47a9064 BL31: Enable pointer authentication support by Antonio Nino Diaz · 6 years ago
  12. 25cda67 Add support for pointer authentication by Antonio Nino Diaz · 6 years ago
  13. 594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · 6 years ago
  14. 0e402d3 Remove support for the SMC Calling Convention 2.0 by Antonio Nino Diaz · 6 years ago
  15. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  16. f939a6a SPM: Introduce SMC handlers for SPCI and SPRT by Antonio Nino Diaz · 6 years ago
  17. d1198ad BL31: Use helper function to save registers in SMC handler by Soby Mathew · 6 years ago
  18. 4e28c20 PIE: Position Independant Executable support for BL31 by Soby Mathew · 6 years ago
  19. f0b14cf Remove some MISRA defects in common code by Antonio Nino Diaz · 6 years ago
  20. 911fcc9 RAS: Introduce handler for EL3 EAs by Jeenu Viswambharan · 6 years ago
  21. 93bc4bd RAS: Introduce handler for Double Faults by Jeenu Viswambharan · 7 years ago
  22. 9d4c9c1 RAS: Introduce handler for Uncontainable errors by Jeenu Viswambharan · 7 years ago
  23. 476c29f RAS: Validate stack pointer after error handling by Jeenu Viswambharan · 7 years ago
  24. e86a247 RAS: Move EA handling to a separate file by Jeenu Viswambharan · 6 years ago
  25. 95f30ab Add end_vector_entry assembler macro by Roberto Vargas · 7 years ago
  26. e834ee1 DynamIQ: Enable MMU without using stack by Jeenu Viswambharan · 7 years ago
  27. 9a7ce2f AArch64: Introduce RAS handling by Jeenu Viswambharan · 7 years ago
  28. 96c7df0 AArch64: Introduce External Abort handling by Jeenu Viswambharan · 7 years ago
  29. 23d05a8 AArch64: Refactor GP register restore to separate function by Jeenu Viswambharan · 7 years ago
  30. 35c8cfc Add support for the SMC Calling Convention 2.0 by Antonio Nino Diaz · 7 years ago
  31. 9c274f8 Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatch by davidcunado-arm · 7 years ago
  32. 7c2a3ca Add comments about mismatched TCR_ELx and xlat tables by Antonio Nino Diaz · 7 years ago
  33. 73308d0 Introduce the new BL handover interface by Soby Mathew · 7 years ago
  34. e4794b7 Redefine SMC_UNK as -1 instead of 0xFFFFFFFF by Antonio Nino Diaz · 7 years ago
  35. 0415951 runtime_exceptions: Save x4-x29 unconditionally by Dimitris Papastamos · 7 years ago
  36. d79d40d Merge pull request #1193 from jwerner-chromium/JW_coreboot by davidcunado-arm · 7 years ago
  37. 446f7f1 Workaround for CVE-2017-5715 on Cortex A57 and A72 by Dimitris Papastamos · 7 years ago
  38. 02eb727 utils_def: Add REGSZ and make BIT() assembly-compatible by Julius Werner · 7 years ago
  39. d1a1fd4 Move FPEXC32_EL2 to FP Context by David Cunado · 7 years ago
  40. 67ebde7 Fix x30 reporting for unhandled exceptions by Julius Werner · 7 years ago
  41. fee8653 Fully initialise essential control registers by David Cunado · 8 years ago
  42. fa3cf0b Use SPDX license identifiers by dp-arm · 8 years ago
  43. 043fe9c PSCI: Build option to enable D-Caches early in warmboot by Soby Mathew · 8 years ago
  44. d3ec543 Add and use plat_crash_console_flush() API by Antonio Nino Diaz · 8 years ago
  45. 1fecc8d Merge pull request #860 from jeenu-arm/hw-asstd-coh by davidcunado-arm · 8 years ago
  46. 4ef91f1 Simplify translation tables headers dependencies by Antonio Nino Diaz · 8 years ago
  47. 4614496 Enable data caches early with hardware-assisted coherency by Jeenu Viswambharan · 8 years ago
  48. 68aef10 Define and use no_ret macro where no return is expected by Jeenu Viswambharan · 8 years ago
  49. 0980eed Cosmetic change to exception table by Douglas Raillard · 8 years ago
  50. 3cac786 Add PMF instrumentation points in TF by dp-arm · 8 years ago
  51. d019487 Introduce PSCI Library Interface by Soby Mathew · 9 years ago
  52. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · 9 years ago
  53. 9e6ad6c Introduce some helper macros for exception vectors by Sandrine Bailleux · 8 years ago
  54. 391a76e Add 32 bit version of plat_get_syscnt_freq by Antonio Nino Diaz · 9 years ago
  55. 2c7ed5b Dump platform-defined regs in crash reporting by Gerald Lejeune · 9 years ago
  56. 851dc7e Add ISR_EL1 to crash report by Gerald Lejeune · 9 years ago
  57. 632d6df Enable asynchronous abort exceptions during boot by Gerald Lejeune · 9 years ago
  58. 1f21bcf Remove all non-configurable dead loops by Antonio Nino Diaz · 9 years ago
  59. f4119ec Miscellaneous doc fixes for v1.2 by Sandrine Bailleux · 9 years ago
  60. 7d19941 Remove dashes from image names: 'BL3-x' --> 'BL3x' by Juan Castillo · 9 years ago
  61. 6c0566c Move context management code to common location by Yatharth Kochar · 9 years ago
  62. e77e116 Fix issue in Floating point register restore by Soby Mathew · 9 years ago
  63. 8f67649 Merge pull request #443 from achingupta/sb/el3_payloads-cb_single_cpu by danh-arm · 9 years ago
  64. b21b02f Introduce COLD_BOOT_SINGLE_CPU build option by Sandrine Bailleux · 9 years ago
  65. c5204fa Remove the IMF_READ_INTERRUPT_ID build option by Soby Mathew · 9 years ago
  66. e9c4a64 Make generic code work in presence of system caches by Achin Gupta · 9 years ago
  67. 3700a92 PSCI: Migrate TF to the new platform API and CM helpers by Soby Mathew · 9 years ago
  68. 9ccbc03 Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1 by danh-arm · 9 years ago
  69. 449dbd5 Introduce PROGRAMMABLE_RESET_ADDRESS build option by Sandrine Bailleux · 9 years ago
  70. acde8b0 Rationalize reset handling code by Sandrine Bailleux · 10 years ago
  71. 979992e Fix handling of spurious interrupts in BL3_1 by Achin Gupta · 10 years ago
  72. a877c25 Add support to indicate size and end of assembly functions by Kévin Petit · 10 years ago
  73. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · 10 years ago
  74. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · 10 years ago
  75. 2ae2043 Remove coherent memory from the BL memory maps by Soby Mathew · 10 years ago
  76. 046cd3f Miscellaneous documentation fixes by Sandrine Bailleux · 10 years ago
  77. 38b4bc9 Add CPU specific crash reporting handlers by Soby Mathew · 10 years ago
  78. 8e2f287 Add CPU specific power management operations by Soby Mathew · 10 years ago
  79. c704cbc Introduce framework for CPU specific operations by Soby Mathew · 10 years ago
  80. ed1744e Unmask SError interrupt and clear SCR_EL3.EA bit by Achin Gupta · 10 years ago
  81. 534ae7f Merge pull request #179 from jcastillo-arm/jc/tf-issues/219 by danh-arm · 10 years ago
  82. b3dbeb0 Call platform_is_primary_cpu() only from reset handler by Juan Castillo · 10 years ago
  83. 2ed46e9 Optimize EL3 register state stored in cpu_context structure by Soby Mathew · 10 years ago
  84. 45c31c4 Merge pull request #172 from soby-mathew/sm/asm_assert by danh-arm · 10 years ago
  85. 0da9593 Add CPUECTLR_EL1 and Snoop Control register to crash reporting by Soby Mathew · 10 years ago
  86. c1adbbc Rework the crash reporting in BL3-1 to use less stack by Soby Mathew · 10 years ago
  87. 9f09835 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · 10 years ago
  88. e1aa516 Remove coherent stack usage from the warm boot path by Achin Gupta · 10 years ago
  89. f4a9709 Remove coherent stack usage from the cold boot path by Achin Gupta · 10 years ago
  90. 258e94f Allow FP register context to be optional at build time by Juan Castillo · 10 years ago
  91. f268c72 Merge pull request #151 from vikramkanigiri/vk/t133-code-readability by Andrew Thoelke · 10 years ago
  92. cf79bf5 Simplify entry point information generation code on FVP by Vikram Kanigiri · 10 years ago
  93. 4e12607 Initialise CPU contexts from entry_point_info by Andrew Thoelke · 10 years ago
  94. 4d2d553 Remove early_exceptions from BL3-1 by Andrew Thoelke · 10 years ago
  95. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · 10 years ago
  96. e385767 Merge pull request #133 from athoelke/at/crash-reporting-opt by danh-arm · 10 years ago
  97. 385f4d4 Make the BL3-1 crash reporting optional by Andrew Thoelke · 10 years ago
  98. af1ef2b Include 'platform_def.h' header file in 'crash_reporting.S' by Sandrine Bailleux · 10 years ago
  99. 93c89ec Fix compilation issue for IMF_READ_INTERRUPT_ID build flag by Soby Mathew · 10 years ago
  100. 799f0ab Pass 'cookie' parameter to interrupt handler in BL3-1 by Soby Mathew · 10 years ago