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filogic
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atf
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c4c4dec69a5dfa00394e7add5038d4e3e040478c
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plat
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nvidia
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tegra
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common
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aarch64
09a22e7
tegra: add support for multi console interface
by Ambroise Vincent
· Wed May 29 14:04:16 2019 +0100
fa99b22
Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position
by Varun Wadekar
· Wed Aug 23 16:02:06 2017 -0700
21c4272
Tegra: remove duplicate code from CPU's power on path
by Varun Wadekar
· Tue Aug 15 15:38:01 2017 -0700
d417cea
Tegra: read-modify-write ACTLR_ELx registers
by Steven Kao
· Wed Jun 14 14:02:23 2017 +0800
6dc0d76
Tegra210: skip the BTB invalidate workaround for B01 SKUs
by Harvey Hsieh
· Mon Apr 24 19:35:51 2017 +0800
fbdfce1
Tegra: support to set the L2 ECC and Parity enable bit
by Harvey Hsieh
· Wed Nov 23 19:13:08 2016 +0800
1eb64a1
Add plat_crash_console_flush to platforms without it
by Antonio Nino Diaz
· Wed Oct 17 15:29:34 2018 +0100
91b11c3
Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR*
by Eleanor Bonnici
· Thu Aug 10 14:46:26 2017 +0100
b4c75e9
Add new alignment parameter to func assembler macro
by Julius Werner
· Tue Aug 01 15:16:36 2017 -0700
e363146
Fix order of remaining platform #includes
by Isla Mitchell
· Fri Jul 14 10:46:32 2017 +0100
1384a16
Unique names for defines in the CPU libraries
by Varun Wadekar
· Mon Jun 05 14:54:46 2017 -0700
fa3cf0b
Use SPDX license identifiers
by dp-arm
· Wed May 03 09:38:09 2017 +0100
4e6ae18
Tegra: no need to re-init the same console
by Varun Wadekar
· Tue Apr 04 13:40:12 2017 -0700
2bb9f47
Tegra: replace ASM signed tests with unsigned
by Douglas Raillard
· Mon Mar 20 10:38:29 2017 +0000
69ce101
Tegra: enable ECC/Parity protection for Cortex-A57 CPUs
by Varun Wadekar
· Thu May 12 13:43:33 2016 -0700
25e658e
Tegra: include platform_def.h to access UART macros
by Varun Wadekar
· Tue Apr 26 11:38:38 2016 -0700
1ec441e
Tegra: relocate code to BL31_BASE during cold boot
by Varun Wadekar
· Thu Mar 24 15:34:24 2016 -0700
d2014c6
Tegra: init normal/crash console for platforms
by Varun Wadekar
· Thu Oct 29 10:37:28 2015 +0530
39f87d1
Tegra: use ClusterId for calculating core position
by Varun Wadekar
· Tue Sep 22 13:45:07 2015 +0530
b24dea9
Tegra: enable processor retention and L2/CPUECTLR access
by Varun Wadekar
· Tue Sep 22 13:33:56 2015 +0530
e7ae6db
Disable PL011 UART before configuring it
by Juan Castillo
· Thu Nov 26 14:52:15 2015 +0000
a78bb1b
Tegra: remove support for legacy platform APIs
by Varun Wadekar
· Fri Aug 07 10:03:00 2015 +0530
4e9c231
Tegra210: wait for 512 timer ticks before retention entry
by Varun Wadekar
· Fri Aug 21 15:56:02 2015 +0530
d1b6150
Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs
by Varun Wadekar
· Thu Jul 16 09:46:28 2015 +0530
b316e24
Support for NVIDIA's Tegra T210 SoCs
by Varun Wadekar
· Tue May 19 16:48:04 2015 +0530