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git01.mediatek.com / filogic / atf / c14205d8f82ec1798eeae1fa9bd0afdcbca76e43
  1. c14205d feat(st-sdmmc2): manage cards power cycle by Yann Gautier · Fri May 10 16:01:34 2019 +0200
  2. fc7b805 feat(stm32mp1): register fixed regulator by Pascal Paillet · Fri Jan 29 14:48:49 2021 +0100
  3. 8b330ce feat(st-drivers): introduce fixed regulator driver by Pascal Paillet · Wed Jan 20 17:09:10 2021 +0100
  4. 296e1ab refactor(st): update CPU and VDD voltage get by Yann Gautier · Fri Sep 17 16:08:12 2021 +0200
  5. 1b7e8ff refactor(stm32mp1-fdts): update regulator description by Pascal Paillet · Thu Jan 07 18:05:46 2021 +0100
  6. 5e36dbb refactor(st-pmic): use regulator framework for DDR init by Pascal Paillet · Tue Dec 15 19:05:09 2020 +0100
  7. e6f1032 feat(st-pmic): register the PMIC to regulator framework by Yann Gautier · Mon Sep 27 14:31:40 2021 +0200
  8. 0b10b65 refactor(st-pmic): split initialize_pmic() by Nicolas Le Bayon · Mon Nov 18 13:13:36 2019 +0100
  9. b1279e7 feat(stm32mp1): add regulator framework compilation by Yann Gautier · Wed Dec 15 13:16:15 2021 +0100
  10. 79503b8 feat(regulator): add a regulator framework by Pascal Paillet · Tue Dec 15 18:26:39 2020 +0100
  11. c18c454 feat(stpmic1): add new services by Pascal Paillet · Tue Dec 15 18:28:34 2020 +0100
  12. f76731f feat(stpmic1): add USB OTG regulators by Etienne Carriere · Fri Jan 10 08:31:13 2020 +0100
  13. 342865a refactor(st-pmic): improve driver usage by Nicolas Le Bayon · Fri Nov 15 15:56:06 2019 +0100
  14. f5188ee refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean by Nicolas Le Bayon · Thu Sep 19 11:24:50 2019 +0200
  15. 45c1e58 refactor(stm32mp1): re-order drivers init by Yann Gautier · Thu Sep 17 11:54:52 2020 +0200
  16. ab853c2 Merge "fix(errata): workaround for Cortex X2 erratum 2002765" into integration by Bipin Ravi · Wed Dec 22 01:12:32 2021 +0100
  17. 28e8cfe Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration by Bipin Ravi · Wed Dec 22 01:10:54 2021 +0100
  18. 5e2abbe Merge "fix(doc): update TF-A v2.7 release date in the release information page" into integration by Mark Dykes · Tue Dec 21 19:08:44 2021 +0100
  19. 68edfdc fix(doc): update TF-A v2.7 release date in the release information page by Bipin Ravi · Tue Dec 21 09:14:48 2021 -0600
  20. d001b27 Merge "fix(stm32mp1): correct include order" into integration by Madhukar Pappireddy · Fri Dec 17 20:04:33 2021 +0100
  21. 0afef36 fix(errata): workaround for Cortex X2 erratum 2002765 by johpow01 · Thu Dec 02 13:25:50 2021 -0600
  22. 40f4133 Merge changes from topic "morello_plat_support" into integration by Madhukar Pappireddy · Fri Dec 17 15:10:52 2021 +0100
  23. 0c81088 fix(stm32mp1): correct include order by Yann Gautier · Fri Dec 17 09:53:04 2021 +0100
  24. 15f10bd fix(errata): workaround for Cortex X2 erratum 2083908 by johpow01 · Wed Dec 01 17:40:39 2021 -0600
  25. 8e9c9c5 Merge "feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support" into integration by Madhukar Pappireddy · Thu Dec 16 17:18:01 2021 +0100
  26. 05489b9 Merge "fix(amu): add default value for ENABLE_FEAT_FGT and ENABLE_FEAT_ECV flags" into integration by Olivier Deprez · Thu Dec 16 16:34:28 2021 +0100
  27. b7682b4 feat(morello): expose scmi protocols in fdts by Anurag Koul · Fri Dec 03 10:16:47 2021 +0000
  28. 118ad71 fix(morello): change the AP runtime UART address by Chandni Cherukuri · Thu Dec 02 11:22:59 2021 +0530
  29. 066afc2 feat(morello): add support for nt_fw_config by sah01 · Thu Nov 18 10:04:27 2021 +0000
  30. 3c5bb04 feat(morello): split platform_info sds struct by sah01 · Thu Dec 02 06:37:04 2021 +0000
  31. 5887612 feat(morello): add changes to enable TBBR boot by Manoj Kumar · Sun Jan 10 16:12:24 2021 +0000
  32. 460e377 Merge "docs(ff-a): boot order field of SPs manifest" into integration by Madhukar Pappireddy · Thu Dec 16 15:17:08 2021 +0100
  33. d4d951a feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support by Gary Morrison · Wed Nov 10 14:40:15 2021 -0600
  34. 70c9c0b fix(amu): add default value for ENABLE_FEAT_FGT and ENABLE_FEAT_ECV flags by Jayanth Dodderi Chidanand · Wed Dec 15 16:52:10 2021 +0000
  35. 855fc88 docs(ff-a): boot order field of SPs manifest by J-Alves · Tue Dec 14 16:02:27 2021 +0000
  36. 9952970 feat(morello): add DTS for Morello SoC platform by Manoj Kumar · Wed Sep 15 12:42:49 2021 +0530
  37. dff7f6c feat(morello): configure DMC-Bing mode by Chandni Cherukuri · Tue Nov 30 20:35:35 2021 +0530
  38. b19e62a feat(morello): zero out the DDR memory space by Manoj Kumar · Thu Aug 26 10:49:02 2021 +0530
  39. c7ea5f3 feat(morello): add TARGET_PLATFORM flag by Manoj Kumar · Thu Aug 26 10:56:16 2021 +0530
  40. 6f749e2 fix(morello): fix SoC reference clock frequency by Anurag Koul · Wed Aug 25 19:34:20 2021 +0530
  41. 0e6ddbc fix(arm): use PLAT instead of TARGET_PLATFORM by Chandni Cherukuri · Sat Dec 11 14:16:17 2021 +0530
  42. 8bac9f9 Merge changes from topic "fconf_get_index" into integration by Madhukar Pappireddy · Tue Dec 14 20:58:09 2021 +0100
  43. 64edaa3 Merge changes from topic "st_uart_update" into integration by Madhukar Pappireddy · Tue Dec 14 18:25:39 2021 +0100
  44. 3d8497c feat(st): protect UART during platform init by Yann Gautier · Mon Oct 18 16:06:22 2021 +0200
  45. 414f17c feat(stm32mp1): update console management for SP_min by Yann Gautier · Mon Oct 18 15:50:05 2021 +0200
  46. 66baa96 refactor(stm32mp1): improve console management in BL2 by Yann Gautier · Mon Oct 18 14:01:00 2021 +0200
  47. 7a81912 feat(plat/st): add a function to configure console by Yann Gautier · Mon Oct 18 15:26:33 2021 +0200
  48. aaee061 feat(stm32mp1): add stm32_get_boot_interface function by Yann Gautier · Wed Dec 16 12:04:06 2020 +0100
  49. 6eef525 refactor(stm32mp1): move stm32_save_boot_interface() by Yann Gautier · Fri Dec 10 17:04:40 2021 +0100
  50. cd16df3 fix(stm32mp1): deconfigure UART RX pins by Yann Gautier · Fri Jun 04 14:04:05 2021 +0200
  51. 2b79c37 feat(stm32_gpio): add a function to reset a pin by Yann Gautier · Fri Jun 11 10:54:56 2021 +0200
  52. 27f589d refactor(stm32mp1): sort compilation flags by Yann Gautier · Fri Oct 15 17:59:38 2021 +0200
  53. 19cdaa8 feat(stm32mp1): add sign-compare warning by Yann Gautier · Tue Nov 10 15:09:55 2020 +0100
  54. 0e2c001 Merge "fix(scmi): make msg_header variable volatile" into integration by Madhukar Pappireddy · Mon Dec 13 20:12:02 2021 +0100
  55. fd64835 feat(stm32mp1): skip TOS_FW_CONFIG if not in FIP by Yann Gautier · Mon Dec 13 15:24:41 2021 +0100
  56. 5a57e25 feat(fconf): add a helper to get image index by Yann Gautier · Mon Dec 13 15:22:45 2021 +0100
  57. 2d17705 Merge changes from topic "jc/AMUv1" into integration by Manish Pandey · Mon Dec 13 13:52:37 2021 +0100
  58. 0f5e0bb Merge "feat(plat/zynqmp): disable the -mbranch-protection flag" into integration by Madhukar Pappireddy · Fri Dec 10 19:07:40 2021 +0100
  59. 683122e Merge changes from topic "a3700-comphy-fixes-1" into integration by Madhukar Pappireddy · Fri Dec 10 16:06:16 2021 +0100
  60. 7e3035e Merge changes from topic "mb_critical_data" into integration by Manish Pandey · Fri Dec 10 14:37:06 2021 +0100
  61. 4959cc2 Merge "feat(stm32mp1): preserve the PLL4 settings for USB boot" into integration by Manish Pandey · Fri Dec 10 14:19:15 2021 +0100
  62. 76ff363 docs(build-options): add build macros for features FGT,AMUv1 and ECV by Jayanth Dodderi Chidanand · Sun Dec 05 19:21:14 2021 +0000
  63. 13ae0f4 fix(amu): fault handling on EL2 context switch by Jayanth Dodderi Chidanand · Thu Nov 25 14:59:30 2021 +0000
  64. 3764d34 Merge "fix(rmmd/sve): enable/disable SVE/FPU for Realms" into integration by Alexei Fedorov · Fri Dec 10 13:28:48 2021 +0100
  65. f9d518a feat(plat/zynqmp): disable the -mbranch-protection flag by Venkatesh Yadav Abbarapu · Mon Dec 06 21:28:34 2021 -0700
  66. 2e9e015 Merge "fix(rmmd): align RMI and GTSI FIDs with SMCCC" into integration by Alexei Fedorov · Fri Dec 10 12:20:36 2021 +0100
  67. 957d7ea Merge "refactor(measured-boot): add generic macros for using Crypto library" into integration by Madhukar Pappireddy · Fri Dec 10 01:25:26 2021 +0100
  68. c25225a fix(rmmd/sve): enable/disable SVE/FPU for Realms by Subhasish Ghosh · Thu Dec 09 15:41:37 2021 +0000
  69. 0131988 Merge "fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN" into integration by Madhukar Pappireddy · Thu Dec 09 15:03:19 2021 +0100
  70. 938e0dd Merge "refactor(plat/synquacer): update PSCI system_off handling" into integration by Madhukar Pappireddy · Thu Dec 09 15:03:06 2021 +0100
  71. 1132db8 refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants by Marek Behún · Wed Dec 08 01:33:38 2021 +0100
  72. b531ca7 refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants by Marek Behún · Wed Dec 08 01:29:50 2021 +0100
  73. e58e733 refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants by Marek Behún · Wed Dec 08 01:27:38 2021 +0100
  74. d6d3247 refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants by Marek Behún · Wed Dec 08 01:24:36 2021 +0100
  75. d0da334 refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants by Marek Behún · Wed Dec 08 01:20:50 2021 +0100
  76. 6355cdb refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants by Marek Behún · Wed Dec 08 00:15:29 2021 +0100
  77. 5a90dc3 refactor(drivers/marvell/comphy-3700): unify Generation Settings register values by Marek Behún · Wed Dec 08 01:12:00 2021 +0100
  78. ff8afbe refactor(drivers/marvell/comphy-3700): unify Generation Settings register names by Marek Behún · Wed Dec 08 00:52:28 2021 +0100
  79. 781babd4 refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes by Marek Behún · Wed Dec 08 00:46:00 2021 +0100
  80. 0284c8a refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes by Marek Behún · Wed Dec 08 00:37:34 2021 +0100
  81. 4457e65b refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG by Marek Behún · Thu Dec 02 20:04:57 2021 +0100
  82. 88315c5 refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition by Marek Behún · Thu Dec 02 20:29:30 2021 +0100
  83. 9a0e4d9 refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G by Marek Behún · Wed Dec 01 13:45:42 2021 +0100
  84. fc38732 refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant by Marek Behún · Tue Dec 07 23:59:30 2021 +0100
  85. c8b27ce fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics by Marek Behún · Wed Dec 01 18:11:44 2021 +0100
  86. 96ea8fe fix(drivers/marvell/comphy-3700): use reg_set() according to update semantics by Marek Behún · Wed Dec 01 18:03:09 2021 +0100
  87. bca8b6c fix(drivers/marvell/comphy-3700): fix comments about selector register values by Marek Behún · Thu Dec 02 19:23:09 2021 +0100
  88. 593edd5 fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register by Marek Behún · Thu Dec 02 19:14:37 2021 +0100
  89. da9b3d5 fix(drivers/marvell/comphy-3700): fix reference clock selection value names by Marek Behún · Wed Dec 01 13:23:11 2021 +0100
  90. 126f457 fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant by Marek Behún · Wed Dec 01 17:36:46 2021 +0100
  91. d2a1c03 fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name by Marek Behún · Wed Dec 01 14:01:13 2021 +0100
  92. 71d145e fix(drivers/marvell/comphy-3700): fix Generation Setting registers names by Marek Behún · Wed Dec 01 12:39:10 2021 +0100
  93. c823712 fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name by Marek Behún · Tue Dec 07 23:26:17 2021 +0100
  94. 526a637 fix(scmi): make msg_header variable volatile by sah01 · Wed Dec 08 06:29:59 2021 +0000
  95. 931c6ef docs(measured-boot): add a platform function for critical data by Manish V Badarkhe · Thu Oct 21 09:06:18 2021 +0100
  96. 1ffa009 feat(fvp): measure critical data by Manish V Badarkhe · Wed Oct 20 22:06:40 2021 +0100
  97. e112a5a refactor(measured-boot): add generic macros for using Crypto library by Manish V Badarkhe · Wed Oct 06 23:41:50 2021 +0100
  98. 8cc642c fix(rmmd): align RMI and GTSI FIDs with SMCCC by Subhasish Ghosh · Sun Nov 14 17:19:09 2021 +0000
  99. 166f598 Merge "refactor(measured boot): rename a macro INVALID_ID to EVLOG_INVALID_ID" into integration by Sandrine Bailleux · Wed Dec 08 08:16:53 2021 +0100
  100. efded08 Merge "fix(docs): update the v2.6 change-log" into integration by Madhukar Pappireddy · Tue Dec 07 19:01:56 2021 +0100