Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
atf
/
c0dc40e224c89595113d35dade50640e17a20603
/
plat
/
intel
/
soc
/
n5x
/
include
/
n5x_clock_manager.h
a9fca83
fix(intel): fix Agilex and N5X clock manager to main PLL C0
by Jit Loon Lim
· 1 year, 9 months ago
f48707a
feat(intel): implement timer init divider via CPU frequency for N5X
by Sieu Mun Tang
· 2 years, 3 months ago