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git01.mediatek.com / filogic / atf / b68e286bbdde9a191a048a0620216f399e58ed6b / plat / intel / soc / agilex
  1. 461f8f4 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · 5 years ago
  2. 91071fc intel: agilex: Fix psci power domain off by Hadi Asyrafi · 5 years ago
  3. cc077d9 Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration by Paul Beesley · 5 years ago
  4. 5d7c656 intel: agilex: HMC driver calculate DDR size by Hadi Asyrafi · 5 years ago
  5. 56c4901 intel: agilex: Clear PLL lostlock bypass mode by Hadi Asyrafi · 5 years ago
  6. ad90712 Merge "intel: agilex: Fix memory controller driver" into integration by Paul Beesley · 5 years ago
  7. 83fe38e intel: agilex: Fix memory controller driver by Hadi Asyrafi · 5 years ago
  8. a813fed intel: agilex: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  9. 462c6c4 Merge changes from topic "intel-plat-refactor" into integration by Sandrine Bailleux · 5 years ago
  10. 309ac01 intel: Platform common code refactor by Hadi Asyrafi · 5 years ago
  11. 6a240c7 intel: Platform common code refactor by Hadi Asyrafi · 5 years ago
  12. e944d22 intel: agilex: Fix BL31 memory mapping by Hadi Asyrafi · 5 years ago
  13. a724e43 intel: agilex: Fix build error by Ambroise Vincent · 5 years ago
  14. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · 5 years ago